2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/limits.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/physmem.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
125 #include <sys/sbuf.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
131 #include <sys/_unrhdr.h>
135 #include <vm/vm_param.h>
136 #include <vm/vm_kern.h>
137 #include <vm/vm_page.h>
138 #include <vm/vm_map.h>
139 #include <vm/vm_object.h>
140 #include <vm/vm_extern.h>
141 #include <vm/vm_pageout.h>
142 #include <vm/vm_pager.h>
143 #include <vm/vm_phys.h>
144 #include <vm/vm_radix.h>
145 #include <vm/vm_reserv.h>
146 #include <vm/vm_dumpset.h>
149 #include <machine/machdep.h>
150 #include <machine/md_var.h>
151 #include <machine/pcb.h>
153 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
154 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2)
156 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
157 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
158 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
159 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
161 #define NUL0E L0_ENTRIES
162 #define NUL1E (NUL0E * NL1PG)
163 #define NUL2E (NUL1E * NL2PG)
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pmap_l0_pindex(v) (NUL2E + NUL1E + ((v) >> L0_SHIFT))
182 #define pmap_l1_pindex(v) (NUL2E + ((v) >> L1_SHIFT))
183 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
185 static struct md_page *
186 pa_to_pvh(vm_paddr_t pa)
188 struct vm_phys_seg *seg;
191 for (segind = 0; segind < vm_phys_nsegs; segind++) {
192 seg = &vm_phys_segs[segind];
193 if (pa >= seg->start && pa < seg->end)
194 return ((struct md_page *)seg->md_first +
195 pmap_l2_pindex(pa) - pmap_l2_pindex(seg->start));
197 panic("pa 0x%jx not within vm_phys_segs", (uintmax_t)pa);
200 static struct md_page *
201 page_to_pvh(vm_page_t m)
203 struct vm_phys_seg *seg;
205 seg = &vm_phys_segs[m->segind];
206 return ((struct md_page *)seg->md_first +
207 pmap_l2_pindex(VM_PAGE_TO_PHYS(m)) - pmap_l2_pindex(seg->start));
210 #define NPV_LIST_LOCKS MAXCPU
212 #define PHYS_TO_PV_LIST_LOCK(pa) \
213 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
215 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
216 struct rwlock **_lockp = (lockp); \
217 struct rwlock *_new_lock; \
219 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
220 if (_new_lock != *_lockp) { \
221 if (*_lockp != NULL) \
222 rw_wunlock(*_lockp); \
223 *_lockp = _new_lock; \
228 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
229 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
231 #define RELEASE_PV_LIST_LOCK(lockp) do { \
232 struct rwlock **_lockp = (lockp); \
234 if (*_lockp != NULL) { \
235 rw_wunlock(*_lockp); \
240 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
241 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
244 * The presence of this flag indicates that the mapping is writeable.
245 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise
246 * it is dirty. This flag may only be set on managed mappings.
248 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
249 * as a software managed bit.
251 #define ATTR_SW_DBM ATTR_DBM
253 struct pmap kernel_pmap_store;
255 /* Used for mapping ACPI memory before VM is initialized */
256 #define PMAP_PREINIT_MAPPING_COUNT 32
257 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
258 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
259 static int vm_initialized = 0; /* No need to use pre-init maps when set */
262 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
263 * Always map entire L2 block for simplicity.
264 * VA of L2 block = preinit_map_va + i * L2_SIZE
266 static struct pmap_preinit_mapping {
270 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
272 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
273 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
274 vm_offset_t kernel_vm_end = 0;
277 * Data for the pv entry allocation mechanism.
279 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
280 static struct mtx pv_chunks_mutex;
281 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
282 static struct md_page *pv_table;
283 static struct md_page pv_dummy;
285 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
286 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
287 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
289 /* This code assumes all L1 DMAP entries will be used */
290 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
291 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
293 extern pt_entry_t pagetable_l0_ttbr1[];
295 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
296 static vm_paddr_t physmap[PHYSMAP_SIZE];
297 static u_int physmap_idx;
299 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
300 "VM/pmap parameters");
303 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
304 * that it has currently allocated to a pmap, a cursor ("asid_next") to
305 * optimize its search for a free ASID in the bit vector, and an epoch number
306 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
307 * ASIDs that are not currently active on a processor.
309 * The current epoch number is always in the range [0, INT_MAX). Negative
310 * numbers and INT_MAX are reserved for special cases that are described
319 struct mtx asid_set_mutex;
322 static struct asid_set asids;
323 static struct asid_set vmids;
325 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
327 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asids.asid_bits, 0,
328 "The number of bits in an ASID");
329 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asids.asid_next, 0,
330 "The last allocated ASID plus one");
331 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asids.asid_epoch, 0,
332 "The current epoch number");
334 static SYSCTL_NODE(_vm_pmap, OID_AUTO, vmid, CTLFLAG_RD, 0, "VMID allocator");
335 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, bits, CTLFLAG_RD, &vmids.asid_bits, 0,
336 "The number of bits in an VMID");
337 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, next, CTLFLAG_RD, &vmids.asid_next, 0,
338 "The last allocated VMID plus one");
339 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, epoch, CTLFLAG_RD, &vmids.asid_epoch, 0,
340 "The current epoch number");
342 void (*pmap_clean_stage2_tlbi)(void);
343 void (*pmap_invalidate_vpipt_icache)(void);
346 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
347 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
348 * dynamically allocated ASIDs have a non-negative epoch number.
350 * An invalid ASID is represented by -1.
352 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
353 * which indicates that an ASID should never be allocated to the pmap, and
354 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
355 * allocated when the pmap is next activated.
357 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
358 ((u_long)(epoch) << 32)))
359 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
360 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
362 #define TLBI_VA_SHIFT 12
363 #define TLBI_VA_MASK ((1ul << 44) - 1)
364 #define TLBI_VA(addr) (((addr) >> TLBI_VA_SHIFT) & TLBI_VA_MASK)
365 #define TLBI_VA_L3_INCR (L3_SIZE >> TLBI_VA_SHIFT)
367 static int superpages_enabled = 1;
368 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
369 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
370 "Are large page mappings enabled?");
373 * Internal flags for pmap_enter()'s helper functions.
375 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
376 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
378 static void free_pv_chunk(struct pv_chunk *pc);
379 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
380 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
381 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
382 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
383 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
386 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
387 static bool pmap_activate_int(pmap_t pmap);
388 static void pmap_alloc_asid(pmap_t pmap);
389 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
390 vm_prot_t prot, int mode, bool skip_unmapped);
391 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
392 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
393 vm_offset_t va, struct rwlock **lockp);
394 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
395 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
396 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
397 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
398 u_int flags, vm_page_t m, struct rwlock **lockp);
399 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
400 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
401 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
402 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
403 static void pmap_reset_asid_set(pmap_t pmap);
404 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
405 vm_page_t m, struct rwlock **lockp);
407 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
408 struct rwlock **lockp);
410 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
411 struct spglist *free);
412 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
413 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
416 * These load the old table data and store the new value.
417 * They need to be atomic as the System MMU may write to the table at
418 * the same time as the CPU.
420 #define pmap_clear(table) atomic_store_64(table, 0)
421 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
422 #define pmap_load(table) (*table)
423 #define pmap_load_clear(table) atomic_swap_64(table, 0)
424 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
425 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
426 #define pmap_store(table, entry) atomic_store_64(table, entry)
428 /********************/
429 /* Inline functions */
430 /********************/
433 pagecopy(void *s, void *d)
436 memcpy(d, s, PAGE_SIZE);
439 static __inline pd_entry_t *
440 pmap_l0(pmap_t pmap, vm_offset_t va)
443 return (&pmap->pm_l0[pmap_l0_index(va)]);
446 static __inline pd_entry_t *
447 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
451 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
452 return (&l1[pmap_l1_index(va)]);
455 static __inline pd_entry_t *
456 pmap_l1(pmap_t pmap, vm_offset_t va)
460 l0 = pmap_l0(pmap, va);
461 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
464 return (pmap_l0_to_l1(l0, va));
467 static __inline pd_entry_t *
468 pmap_l1_to_l2(pd_entry_t *l1p, vm_offset_t va)
474 KASSERT(ADDR_IS_CANONICAL(va),
475 ("%s: Address not in canonical form: %lx", __func__, va));
477 * The valid bit may be clear if pmap_update_entry() is concurrently
478 * modifying the entry, so for KVA only the entry type may be checked.
480 KASSERT(ADDR_IS_KERNEL(va) || (l1 & ATTR_DESCR_VALID) != 0,
481 ("%s: L1 entry %#lx for %#lx is invalid", __func__, l1, va));
482 KASSERT((l1 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
483 ("%s: L1 entry %#lx for %#lx is a leaf", __func__, l1, va));
484 l2p = (pd_entry_t *)PHYS_TO_DMAP(l1 & ~ATTR_MASK);
485 return (&l2p[pmap_l2_index(va)]);
488 static __inline pd_entry_t *
489 pmap_l2(pmap_t pmap, vm_offset_t va)
493 l1 = pmap_l1(pmap, va);
494 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
497 return (pmap_l1_to_l2(l1, va));
500 static __inline pt_entry_t *
501 pmap_l2_to_l3(pd_entry_t *l2p, vm_offset_t va)
508 KASSERT(ADDR_IS_CANONICAL(va),
509 ("%s: Address not in canonical form: %lx", __func__, va));
511 * The valid bit may be clear if pmap_update_entry() is concurrently
512 * modifying the entry, so for KVA only the entry type may be checked.
514 KASSERT(ADDR_IS_KERNEL(va) || (l2 & ATTR_DESCR_VALID) != 0,
515 ("%s: L2 entry %#lx for %#lx is invalid", __func__, l2, va));
516 KASSERT((l2 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE,
517 ("%s: L2 entry %#lx for %#lx is a leaf", __func__, l2, va));
518 l3p = (pt_entry_t *)PHYS_TO_DMAP(l2 & ~ATTR_MASK);
519 return (&l3p[pmap_l3_index(va)]);
523 * Returns the lowest valid pde for a given virtual address.
524 * The next level may or may not point to a valid page or block.
526 static __inline pd_entry_t *
527 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
529 pd_entry_t *l0, *l1, *l2, desc;
531 l0 = pmap_l0(pmap, va);
532 desc = pmap_load(l0) & ATTR_DESCR_MASK;
533 if (desc != L0_TABLE) {
538 l1 = pmap_l0_to_l1(l0, va);
539 desc = pmap_load(l1) & ATTR_DESCR_MASK;
540 if (desc != L1_TABLE) {
545 l2 = pmap_l1_to_l2(l1, va);
546 desc = pmap_load(l2) & ATTR_DESCR_MASK;
547 if (desc != L2_TABLE) {
557 * Returns the lowest valid pte block or table entry for a given virtual
558 * address. If there are no valid entries return NULL and set the level to
559 * the first invalid level.
561 static __inline pt_entry_t *
562 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
564 pd_entry_t *l1, *l2, desc;
567 l1 = pmap_l1(pmap, va);
572 desc = pmap_load(l1) & ATTR_DESCR_MASK;
573 if (desc == L1_BLOCK) {
578 if (desc != L1_TABLE) {
583 l2 = pmap_l1_to_l2(l1, va);
584 desc = pmap_load(l2) & ATTR_DESCR_MASK;
585 if (desc == L2_BLOCK) {
590 if (desc != L2_TABLE) {
596 l3 = pmap_l2_to_l3(l2, va);
597 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
604 pmap_ps_enabled(pmap_t pmap __unused)
607 return (superpages_enabled != 0);
611 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
612 pd_entry_t **l2, pt_entry_t **l3)
614 pd_entry_t *l0p, *l1p, *l2p;
616 if (pmap->pm_l0 == NULL)
619 l0p = pmap_l0(pmap, va);
622 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
625 l1p = pmap_l0_to_l1(l0p, va);
628 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
634 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
637 l2p = pmap_l1_to_l2(l1p, va);
640 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
645 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
648 *l3 = pmap_l2_to_l3(l2p, va);
654 pmap_l3_valid(pt_entry_t l3)
657 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
660 CTASSERT(L1_BLOCK == L2_BLOCK);
663 pmap_pte_memattr(pmap_t pmap, vm_memattr_t memattr)
667 if (pmap->pm_stage == PM_STAGE1) {
668 val = ATTR_S1_IDX(memattr);
669 if (memattr == VM_MEMATTR_DEVICE)
677 case VM_MEMATTR_DEVICE:
678 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_DEVICE_nGnRnE) |
679 ATTR_S2_XN(ATTR_S2_XN_ALL));
680 case VM_MEMATTR_UNCACHEABLE:
681 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_NC));
682 case VM_MEMATTR_WRITE_BACK:
683 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WB));
684 case VM_MEMATTR_WRITE_THROUGH:
685 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WT));
687 panic("%s: invalid memory attribute %x", __func__, memattr);
692 pmap_pte_prot(pmap_t pmap, vm_prot_t prot)
697 if (pmap->pm_stage == PM_STAGE1) {
698 if ((prot & VM_PROT_EXECUTE) == 0)
700 if ((prot & VM_PROT_WRITE) == 0)
701 val |= ATTR_S1_AP(ATTR_S1_AP_RO);
703 if ((prot & VM_PROT_WRITE) != 0)
704 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
705 if ((prot & VM_PROT_READ) != 0)
706 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_READ);
707 if ((prot & VM_PROT_EXECUTE) == 0)
708 val |= ATTR_S2_XN(ATTR_S2_XN_ALL);
715 * Checks if the PTE is dirty.
718 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte)
721 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
723 if (pmap->pm_stage == PM_STAGE1) {
724 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0,
725 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
727 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
728 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM));
731 return ((pte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
732 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE));
736 pmap_resident_count_inc(pmap_t pmap, int count)
739 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
740 pmap->pm_stats.resident_count += count;
744 pmap_resident_count_dec(pmap_t pmap, int count)
747 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
748 KASSERT(pmap->pm_stats.resident_count >= count,
749 ("pmap %p resident count underflow %ld %d", pmap,
750 pmap->pm_stats.resident_count, count));
751 pmap->pm_stats.resident_count -= count;
755 pmap_early_vtophys(vm_offset_t va)
759 pa_page = arm64_address_translate_s1e1r(va) & PAR_PA_MASK;
760 return (pa_page | (va & PAR_LOW_MASK));
763 /* State of the bootstrapped DMAP page tables */
764 struct dmap_bootstrap_state {
773 vm_offset_t freemempos;
777 pmap_bootstrap_dmap_l0_table(struct dmap_bootstrap_state *state)
782 /* Link the level 0 table to a level 1 table */
783 l0_slot = pmap_l0_index(state->va);
784 if (l0_slot != state->l0_slot) {
785 MPASS(state->l0_slot < l0_slot ||
786 state->l0_slot == L0_ENTRIES);
788 /* Create a new L0 table entry */
789 state->l0_slot = l0_slot;
790 state->l1 = (pt_entry_t *)state->freemempos;
791 memset(state->l1, 0, PAGE_SIZE);
792 state->freemempos += PAGE_SIZE;
794 /* Reset lower levels */
797 state->l1_slot = Ln_ENTRIES;
798 state->l2_slot = Ln_ENTRIES;
800 l1_pa = pmap_early_vtophys((vm_offset_t)state->l1);
801 MPASS((l1_pa & Ln_TABLE_MASK) == 0);
802 MPASS(pagetable_l0_ttbr1[l0_slot] == 0);
803 pmap_store(&pagetable_l0_ttbr1[l0_slot], l1_pa |
804 TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0 | L0_TABLE);
806 KASSERT(state->l1 != NULL, ("%s: NULL l1", __func__));
810 pmap_bootstrap_dmap_l1_table(struct dmap_bootstrap_state *state)
815 /* Make sure there is a valid L0 -> L1 table */
816 pmap_bootstrap_dmap_l0_table(state);
818 /* Link the level 1 table to a level 2 table */
819 l1_slot = pmap_l1_index(state->va);
820 if (l1_slot != state->l1_slot) {
821 MPASS(state->l1_slot < l1_slot ||
822 state->l1_slot == Ln_ENTRIES);
824 /* Create a new L1 table entry */
825 state->l1_slot = l1_slot;
826 state->l2 = (pt_entry_t *)state->freemempos;
827 memset(state->l2, 0, PAGE_SIZE);
828 state->freemempos += PAGE_SIZE;
830 /* Reset lower levels */
832 state->l2_slot = Ln_ENTRIES;
834 l2_pa = pmap_early_vtophys((vm_offset_t)state->l2);
835 MPASS((l2_pa & Ln_TABLE_MASK) == 0);
836 MPASS(state->l1[l1_slot] == 0);
837 pmap_store(&state->l1[l1_slot], l2_pa | TATTR_PXN_TABLE |
840 KASSERT(state->l2 != NULL, ("%s: NULL l2", __func__));
844 pmap_bootstrap_dmap_l2_table(struct dmap_bootstrap_state *state)
849 /* Make sure there is a valid L1 -> L2 table */
850 pmap_bootstrap_dmap_l1_table(state);
852 /* Link the level 2 table to a level 3 table */
853 l2_slot = pmap_l2_index(state->va);
854 if (l2_slot != state->l2_slot) {
855 MPASS(state->l2_slot < l2_slot ||
856 state->l2_slot == Ln_ENTRIES);
858 /* Create a new L2 table entry */
859 state->l2_slot = l2_slot;
860 state->l3 = (pt_entry_t *)state->freemempos;
861 memset(state->l3, 0, PAGE_SIZE);
862 state->freemempos += PAGE_SIZE;
864 l3_pa = pmap_early_vtophys((vm_offset_t)state->l3);
865 MPASS((l3_pa & Ln_TABLE_MASK) == 0);
866 MPASS(state->l2[l2_slot] == 0);
867 pmap_store(&state->l2[l2_slot], l3_pa | TATTR_PXN_TABLE |
870 KASSERT(state->l3 != NULL, ("%s: NULL l3", __func__));
874 pmap_bootstrap_dmap_l2_block(struct dmap_bootstrap_state *state, int i)
879 if ((physmap[i + 1] - state->pa) < L2_SIZE)
882 /* Make sure there is a valid L1 table */
883 pmap_bootstrap_dmap_l1_table(state);
885 MPASS((state->va & L2_OFFSET) == 0);
887 state->va < DMAP_MAX_ADDRESS &&
888 (physmap[i + 1] - state->pa) >= L2_SIZE;
889 state->va += L2_SIZE, state->pa += L2_SIZE) {
891 * Stop if we are about to walk off the end of what the
892 * current L1 slot can address.
894 if (!first && (state->pa & L1_OFFSET) == 0)
898 l2_slot = pmap_l2_index(state->va);
899 MPASS((state->pa & L2_OFFSET) == 0);
900 MPASS(state->l2[l2_slot] == 0);
901 pmap_store(&state->l2[l2_slot], state->pa | ATTR_DEFAULT |
902 ATTR_S1_XN | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
905 MPASS(state->va == (state->pa - dmap_phys_base + DMAP_MIN_ADDRESS));
909 pmap_bootstrap_dmap_l3_page(struct dmap_bootstrap_state *state, int i)
914 if ((physmap[i + 1] - state->pa) < L3_SIZE)
917 /* Make sure there is a valid L2 table */
918 pmap_bootstrap_dmap_l2_table(state);
920 MPASS((state->va & L3_OFFSET) == 0);
922 state->va < DMAP_MAX_ADDRESS &&
923 (physmap[i + 1] - state->pa) >= L3_SIZE;
924 state->va += L3_SIZE, state->pa += L3_SIZE) {
926 * Stop if we are about to walk off the end of what the
927 * current L2 slot can address.
929 if (!first && (state->pa & L2_OFFSET) == 0)
933 l3_slot = pmap_l3_index(state->va);
934 MPASS((state->pa & L3_OFFSET) == 0);
935 MPASS(state->l3[l3_slot] == 0);
936 pmap_store(&state->l3[l3_slot], state->pa | ATTR_DEFAULT |
937 ATTR_S1_XN | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
940 MPASS(state->va == (state->pa - dmap_phys_base + DMAP_MIN_ADDRESS));
944 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
945 vm_offset_t freemempos)
947 struct dmap_bootstrap_state state;
950 dmap_phys_base = min_pa & ~L1_OFFSET;
954 state.l1 = state.l2 = state.l3 = NULL;
955 state.l0_slot = L0_ENTRIES;
956 state.l1_slot = Ln_ENTRIES;
957 state.l2_slot = Ln_ENTRIES;
958 state.freemempos = freemempos;
960 for (i = 0; i < (physmap_idx * 2); i += 2) {
961 state.pa = physmap[i] & ~L3_OFFSET;
962 state.va = state.pa - dmap_phys_base + DMAP_MIN_ADDRESS;
964 /* Create L3 mappings at the start of the region */
965 if ((state.pa & L2_OFFSET) != 0)
966 pmap_bootstrap_dmap_l3_page(&state, i);
967 MPASS(state.pa <= physmap[i + 1]);
969 /* Create L2 mappings at the start of the region */
970 if ((state.pa & L1_OFFSET) != 0)
971 pmap_bootstrap_dmap_l2_block(&state, i);
972 MPASS(state.pa <= physmap[i + 1]);
974 /* Create the main L1 block mappings */
975 for (; state.va < DMAP_MAX_ADDRESS &&
976 (physmap[i + 1] - state.pa) >= L1_SIZE;
977 state.va += L1_SIZE, state.pa += L1_SIZE) {
978 /* Make sure there is a valid L1 table */
979 pmap_bootstrap_dmap_l0_table(&state);
980 MPASS((state.pa & L1_OFFSET) == 0);
981 pmap_store(&state.l1[pmap_l1_index(state.va)],
982 state.pa | ATTR_DEFAULT | ATTR_S1_XN |
983 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
986 MPASS(state.pa <= physmap[i + 1]);
988 /* Create L2 mappings at the end of the region */
989 pmap_bootstrap_dmap_l2_block(&state, i);
990 MPASS(state.pa <= physmap[i + 1]);
992 /* Create L3 mappings at the end of the region */
993 pmap_bootstrap_dmap_l3_page(&state, i);
994 MPASS(state.pa == physmap[i + 1]);
996 if (state.pa > dmap_phys_max) {
997 dmap_phys_max = state.pa;
998 dmap_max_addr = state.va;
1004 return (state.freemempos);
1008 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
1015 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
1017 l1 = (pd_entry_t *)l1pt;
1018 l1_slot = pmap_l1_index(va);
1021 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
1022 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
1024 pa = pmap_early_vtophys(l2pt);
1025 pmap_store(&l1[l1_slot],
1026 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
1030 /* Clean the L2 page table */
1031 memset((void *)l2_start, 0, l2pt - l2_start);
1037 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
1044 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
1046 l2 = pmap_l2(kernel_pmap, va);
1047 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
1048 l2_slot = pmap_l2_index(va);
1051 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
1052 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
1054 pa = pmap_early_vtophys(l3pt);
1055 pmap_store(&l2[l2_slot],
1056 (pa & ~Ln_TABLE_MASK) | ATTR_S1_UXN | L2_TABLE);
1060 /* Clean the L2 page table */
1061 memset((void *)l3_start, 0, l3pt - l3_start);
1067 * Bootstrap the system enough to run with virtual memory.
1070 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
1073 vm_offset_t freemempos;
1074 vm_offset_t dpcpu, msgbufpv;
1075 vm_paddr_t start_pa, pa, min_pa;
1076 uint64_t kern_delta;
1079 /* Verify that the ASID is set through TTBR0. */
1080 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
1081 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
1083 kern_delta = KERNBASE - kernstart;
1085 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
1086 printf("%lx\n", l1pt);
1087 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
1089 /* Set this early so we can use the pagetable walking functions */
1090 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
1091 PMAP_LOCK_INIT(kernel_pmap);
1092 kernel_pmap->pm_l0_paddr = l0pt - kern_delta;
1093 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
1094 kernel_pmap->pm_stage = PM_STAGE1;
1095 kernel_pmap->pm_levels = 4;
1096 kernel_pmap->pm_ttbr = kernel_pmap->pm_l0_paddr;
1097 kernel_pmap->pm_asid_set = &asids;
1099 /* Assume the address we were loaded to is a valid physical address */
1100 min_pa = KERNBASE - kern_delta;
1102 physmap_idx = physmem_avail(physmap, nitems(physmap));
1106 * Find the minimum physical address. physmap is sorted,
1107 * but may contain empty ranges.
1109 for (i = 0; i < physmap_idx * 2; i += 2) {
1110 if (physmap[i] == physmap[i + 1])
1112 if (physmap[i] <= min_pa)
1113 min_pa = physmap[i];
1116 freemempos = KERNBASE + kernlen;
1117 freemempos = roundup2(freemempos, PAGE_SIZE);
1119 /* Create a direct map region early so we can use it for pa -> va */
1120 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
1122 start_pa = pa = KERNBASE - kern_delta;
1125 * Create the l2 tables up to VM_MAX_KERNEL_ADDRESS. We assume that the
1126 * loader allocated the first and only l2 page table page used to map
1127 * the kernel, preloaded files and module metadata.
1129 freemempos = pmap_bootstrap_l2(l1pt, KERNBASE + L1_SIZE, freemempos);
1130 /* And the l3 tables for the early devmap */
1131 freemempos = pmap_bootstrap_l3(l1pt,
1132 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
1136 #define alloc_pages(var, np) \
1137 (var) = freemempos; \
1138 freemempos += (np * PAGE_SIZE); \
1139 memset((char *)(var), 0, ((np) * PAGE_SIZE));
1141 /* Allocate dynamic per-cpu area. */
1142 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
1143 dpcpu_init((void *)dpcpu, 0);
1145 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
1146 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
1147 msgbufp = (void *)msgbufpv;
1149 /* Reserve some VA space for early BIOS/ACPI mapping */
1150 preinit_map_va = roundup2(freemempos, L2_SIZE);
1152 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
1153 virtual_avail = roundup2(virtual_avail, L1_SIZE);
1154 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
1155 kernel_vm_end = virtual_avail;
1157 pa = pmap_early_vtophys(freemempos);
1159 physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
1165 * Initialize a vm_page's machine-dependent fields.
1168 pmap_page_init(vm_page_t m)
1171 TAILQ_INIT(&m->md.pv_list);
1172 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
1176 pmap_init_asids(struct asid_set *set, int bits)
1180 set->asid_bits = bits;
1183 * We may be too early in the overall initialization process to use
1186 set->asid_set_size = 1 << set->asid_bits;
1187 set->asid_set = (bitstr_t *)kmem_malloc(bitstr_size(set->asid_set_size),
1189 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
1190 bit_set(set->asid_set, i);
1191 set->asid_next = ASID_FIRST_AVAILABLE;
1192 mtx_init(&set->asid_set_mutex, "asid set", NULL, MTX_SPIN);
1196 * Initialize the pmap module.
1197 * Called by vm_init, to initialize any structures that the pmap
1198 * system needs to map virtual memory.
1203 struct vm_phys_seg *seg, *next_seg;
1204 struct md_page *pvh;
1207 int i, pv_npg, vmid_bits;
1210 * Are large page mappings enabled?
1212 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
1213 if (superpages_enabled) {
1214 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1215 ("pmap_init: can't assign to pagesizes[1]"));
1216 pagesizes[1] = L2_SIZE;
1217 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
1218 ("pmap_init: can't assign to pagesizes[2]"));
1219 pagesizes[2] = L1_SIZE;
1223 * Initialize the ASID allocator.
1225 pmap_init_asids(&asids,
1226 (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8);
1229 mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
1232 if (ID_AA64MMFR1_VMIDBits_VAL(mmfr1) ==
1233 ID_AA64MMFR1_VMIDBits_16)
1235 pmap_init_asids(&vmids, vmid_bits);
1239 * Initialize the pv chunk list mutex.
1241 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1244 * Initialize the pool of pv list locks.
1246 for (i = 0; i < NPV_LIST_LOCKS; i++)
1247 rw_init(&pv_list_locks[i], "pmap pv list");
1250 * Calculate the size of the pv head table for superpages.
1253 for (i = 0; i < vm_phys_nsegs; i++) {
1254 seg = &vm_phys_segs[i];
1255 pv_npg += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1256 pmap_l2_pindex(seg->start);
1260 * Allocate memory for the pv head table for superpages.
1262 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1264 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1265 for (i = 0; i < pv_npg; i++)
1266 TAILQ_INIT(&pv_table[i].pv_list);
1267 TAILQ_INIT(&pv_dummy.pv_list);
1270 * Set pointers from vm_phys_segs to pv_table.
1272 for (i = 0, pvh = pv_table; i < vm_phys_nsegs; i++) {
1273 seg = &vm_phys_segs[i];
1274 seg->md_first = pvh;
1275 pvh += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) -
1276 pmap_l2_pindex(seg->start);
1279 * If there is a following segment, and the final
1280 * superpage of this segment and the initial superpage
1281 * of the next segment are the same then adjust the
1282 * pv_table entry for that next segment down by one so
1283 * that the pv_table entries will be shared.
1285 if (i + 1 < vm_phys_nsegs) {
1286 next_seg = &vm_phys_segs[i + 1];
1287 if (pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1 ==
1288 pmap_l2_pindex(next_seg->start)) {
1297 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1298 "2MB page mapping counters");
1300 static u_long pmap_l2_demotions;
1301 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1302 &pmap_l2_demotions, 0, "2MB page demotions");
1304 static u_long pmap_l2_mappings;
1305 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1306 &pmap_l2_mappings, 0, "2MB page mappings");
1308 static u_long pmap_l2_p_failures;
1309 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1310 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1312 static u_long pmap_l2_promotions;
1313 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1314 &pmap_l2_promotions, 0, "2MB page promotions");
1317 * If the given value for "final_only" is false, then any cached intermediate-
1318 * level entries, i.e., L{0,1,2}_TABLE entries, are invalidated in addition to
1319 * any cached final-level entry, i.e., either an L{1,2}_BLOCK or L3_PAGE entry.
1320 * Otherwise, just the cached final-level entry is invalidated.
1322 static __inline void
1323 pmap_invalidate_kernel(uint64_t r, bool final_only)
1326 __asm __volatile("tlbi vaale1is, %0" : : "r" (r));
1328 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1331 static __inline void
1332 pmap_invalidate_user(uint64_t r, bool final_only)
1335 __asm __volatile("tlbi vale1is, %0" : : "r" (r));
1337 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1341 * Invalidates any cached final- and optionally intermediate-level TLB entries
1342 * for the specified virtual address in the given virtual address space.
1344 static __inline void
1345 pmap_invalidate_page(pmap_t pmap, vm_offset_t va, bool final_only)
1349 PMAP_ASSERT_STAGE1(pmap);
1353 if (pmap == kernel_pmap) {
1354 pmap_invalidate_kernel(r, final_only);
1356 r |= ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1357 pmap_invalidate_user(r, final_only);
1364 * Invalidates any cached final- and optionally intermediate-level TLB entries
1365 * for the specified virtual address range in the given virtual address space.
1367 static __inline void
1368 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1371 uint64_t end, r, start;
1373 PMAP_ASSERT_STAGE1(pmap);
1376 if (pmap == kernel_pmap) {
1377 start = TLBI_VA(sva);
1379 for (r = start; r < end; r += TLBI_VA_L3_INCR)
1380 pmap_invalidate_kernel(r, final_only);
1382 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1383 start |= TLBI_VA(sva);
1384 end |= TLBI_VA(eva);
1385 for (r = start; r < end; r += TLBI_VA_L3_INCR)
1386 pmap_invalidate_user(r, final_only);
1393 * Invalidates all cached intermediate- and final-level TLB entries for the
1394 * given virtual address space.
1396 static __inline void
1397 pmap_invalidate_all(pmap_t pmap)
1401 PMAP_ASSERT_STAGE1(pmap);
1404 if (pmap == kernel_pmap) {
1405 __asm __volatile("tlbi vmalle1is");
1407 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1408 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1415 * Routine: pmap_extract
1417 * Extract the physical page address associated
1418 * with the given map/virtual_address pair.
1421 pmap_extract(pmap_t pmap, vm_offset_t va)
1423 pt_entry_t *pte, tpte;
1430 * Find the block or page map for this virtual address. pmap_pte
1431 * will return either a valid block/page entry, or NULL.
1433 pte = pmap_pte(pmap, va, &lvl);
1435 tpte = pmap_load(pte);
1436 pa = tpte & ~ATTR_MASK;
1439 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1440 ("pmap_extract: Invalid L1 pte found: %lx",
1441 tpte & ATTR_DESCR_MASK));
1442 pa |= (va & L1_OFFSET);
1445 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1446 ("pmap_extract: Invalid L2 pte found: %lx",
1447 tpte & ATTR_DESCR_MASK));
1448 pa |= (va & L2_OFFSET);
1451 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1452 ("pmap_extract: Invalid L3 pte found: %lx",
1453 tpte & ATTR_DESCR_MASK));
1454 pa |= (va & L3_OFFSET);
1463 * Routine: pmap_extract_and_hold
1465 * Atomically extract and hold the physical page
1466 * with the given pmap and virtual address pair
1467 * if that mapping permits the given protection.
1470 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1472 pt_entry_t *pte, tpte;
1480 pte = pmap_pte(pmap, va, &lvl);
1482 tpte = pmap_load(pte);
1484 KASSERT(lvl > 0 && lvl <= 3,
1485 ("pmap_extract_and_hold: Invalid level %d", lvl));
1486 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1487 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1488 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1489 tpte & ATTR_DESCR_MASK));
1492 if ((prot & VM_PROT_WRITE) == 0)
1494 else if (pmap->pm_stage == PM_STAGE1 &&
1495 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW))
1497 else if (pmap->pm_stage == PM_STAGE2 &&
1498 ((tpte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
1499 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)))
1505 off = va & L1_OFFSET;
1508 off = va & L2_OFFSET;
1514 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1515 if (m != NULL && !vm_page_wire_mapped(m))
1524 * Walks the page tables to translate a kernel virtual address to a
1525 * physical address. Returns true if the kva is valid and stores the
1526 * physical address in pa if it is not NULL.
1529 pmap_klookup(vm_offset_t va, vm_paddr_t *pa)
1531 pt_entry_t *pte, tpte;
1536 * Disable interrupts so we don't get interrupted between asking
1537 * for address translation, and getting the result back.
1539 intr = intr_disable();
1540 par = arm64_address_translate_s1e1r(va);
1543 if (PAR_SUCCESS(par)) {
1545 *pa = (par & PAR_PA_MASK) | (va & PAR_LOW_MASK);
1550 * Fall back to walking the page table. The address translation
1551 * instruction may fail when the page is in a break-before-make
1552 * sequence. As we only clear the valid bit in said sequence we
1553 * can walk the page table to find the physical address.
1556 pte = pmap_l1(kernel_pmap, va);
1561 * A concurrent pmap_update_entry() will clear the entry's valid bit
1562 * but leave the rest of the entry unchanged. Therefore, we treat a
1563 * non-zero entry as being valid, and we ignore the valid bit when
1564 * determining whether the entry maps a block, page, or table.
1566 tpte = pmap_load(pte);
1569 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
1571 *pa = (tpte & ~ATTR_MASK) | (va & L1_OFFSET);
1574 pte = pmap_l1_to_l2(&tpte, va);
1575 tpte = pmap_load(pte);
1578 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
1580 *pa = (tpte & ~ATTR_MASK) | (va & L2_OFFSET);
1583 pte = pmap_l2_to_l3(&tpte, va);
1584 tpte = pmap_load(pte);
1588 *pa = (tpte & ~ATTR_MASK) | (va & L3_OFFSET);
1593 pmap_kextract(vm_offset_t va)
1597 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1598 return (DMAP_TO_PHYS(va));
1600 if (pmap_klookup(va, &pa) == false)
1605 /***************************************************
1606 * Low level mapping routines.....
1607 ***************************************************/
1610 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1613 pt_entry_t *pte, attr;
1617 KASSERT((pa & L3_OFFSET) == 0,
1618 ("pmap_kenter: Invalid physical address"));
1619 KASSERT((sva & L3_OFFSET) == 0,
1620 ("pmap_kenter: Invalid virtual address"));
1621 KASSERT((size & PAGE_MASK) == 0,
1622 ("pmap_kenter: Mapping is not page-sized"));
1624 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1625 ATTR_S1_IDX(mode) | L3_PAGE;
1628 pde = pmap_pde(kernel_pmap, va, &lvl);
1629 KASSERT(pde != NULL,
1630 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1631 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1633 pte = pmap_l2_to_l3(pde, va);
1634 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1640 pmap_invalidate_range(kernel_pmap, sva, va, true);
1644 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1647 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
1651 * Remove a page from the kernel pagetables.
1654 pmap_kremove(vm_offset_t va)
1659 pte = pmap_pte(kernel_pmap, va, &lvl);
1660 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1661 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1664 pmap_invalidate_page(kernel_pmap, va, true);
1668 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1674 KASSERT((sva & L3_OFFSET) == 0,
1675 ("pmap_kremove_device: Invalid virtual address"));
1676 KASSERT((size & PAGE_MASK) == 0,
1677 ("pmap_kremove_device: Mapping is not page-sized"));
1681 pte = pmap_pte(kernel_pmap, va, &lvl);
1682 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1684 ("Invalid device pagetable level: %d != 3", lvl));
1690 pmap_invalidate_range(kernel_pmap, sva, va, true);
1694 * Used to map a range of physical addresses into kernel
1695 * virtual address space.
1697 * The value passed in '*virt' is a suggested virtual address for
1698 * the mapping. Architectures which can support a direct-mapped
1699 * physical to virtual region can return the appropriate address
1700 * within that region, leaving '*virt' unchanged. Other
1701 * architectures should map the pages starting at '*virt' and
1702 * update '*virt' with the first usable address after the mapped
1706 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1708 return PHYS_TO_DMAP(start);
1712 * Add a list of wired pages to the kva
1713 * this routine is only used for temporary
1714 * kernel mappings that do not need to have
1715 * page modification or references recorded.
1716 * Note that old mappings are simply written
1717 * over. The page *must* be wired.
1718 * Note: SMP coherent. Uses a ranged shootdown IPI.
1721 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1724 pt_entry_t *pte, pa;
1730 for (i = 0; i < count; i++) {
1731 pde = pmap_pde(kernel_pmap, va, &lvl);
1732 KASSERT(pde != NULL,
1733 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1735 ("pmap_qenter: Invalid level %d", lvl));
1738 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
1739 ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1740 ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE;
1741 pte = pmap_l2_to_l3(pde, va);
1742 pmap_load_store(pte, pa);
1746 pmap_invalidate_range(kernel_pmap, sva, va, true);
1750 * This routine tears out page mappings from the
1751 * kernel -- it is meant only for temporary mappings.
1754 pmap_qremove(vm_offset_t sva, int count)
1760 KASSERT(ADDR_IS_CANONICAL(sva),
1761 ("%s: Address not in canonical form: %lx", __func__, sva));
1762 KASSERT(ADDR_IS_KERNEL(sva), ("usermode va %lx", sva));
1765 while (count-- > 0) {
1766 pte = pmap_pte(kernel_pmap, va, &lvl);
1768 ("Invalid device pagetable level: %d != 3", lvl));
1775 pmap_invalidate_range(kernel_pmap, sva, va, true);
1778 /***************************************************
1779 * Page table page management routines.....
1780 ***************************************************/
1782 * Schedule the specified unused page table page to be freed. Specifically,
1783 * add the page to the specified list of pages that will be released to the
1784 * physical memory manager after the TLB has been updated.
1786 static __inline void
1787 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1788 boolean_t set_PG_ZERO)
1792 m->flags |= PG_ZERO;
1794 m->flags &= ~PG_ZERO;
1795 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1799 * Decrements a page table page's reference count, which is used to record the
1800 * number of valid page table entries within the page. If the reference count
1801 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1802 * page table page was unmapped and FALSE otherwise.
1804 static inline boolean_t
1805 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1809 if (m->ref_count == 0) {
1810 _pmap_unwire_l3(pmap, va, m, free);
1817 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1820 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1822 * unmap the page table page
1824 if (m->pindex >= (NUL2E + NUL1E)) {
1828 l0 = pmap_l0(pmap, va);
1830 } else if (m->pindex >= NUL2E) {
1834 l1 = pmap_l1(pmap, va);
1840 l2 = pmap_l2(pmap, va);
1843 pmap_resident_count_dec(pmap, 1);
1844 if (m->pindex < NUL2E) {
1845 /* We just released an l3, unhold the matching l2 */
1846 pd_entry_t *l1, tl1;
1849 l1 = pmap_l1(pmap, va);
1850 tl1 = pmap_load(l1);
1851 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1852 pmap_unwire_l3(pmap, va, l2pg, free);
1853 } else if (m->pindex < (NUL2E + NUL1E)) {
1854 /* We just released an l2, unhold the matching l1 */
1855 pd_entry_t *l0, tl0;
1858 l0 = pmap_l0(pmap, va);
1859 tl0 = pmap_load(l0);
1860 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1861 pmap_unwire_l3(pmap, va, l1pg, free);
1863 pmap_invalidate_page(pmap, va, false);
1866 * Put page on a list so that it is released after
1867 * *ALL* TLB shootdown is done
1869 pmap_add_delayed_free_list(m, free, TRUE);
1873 * After removing a page table entry, this routine is used to
1874 * conditionally free the page, and manage the reference count.
1877 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1878 struct spglist *free)
1882 KASSERT(ADDR_IS_CANONICAL(va),
1883 ("%s: Address not in canonical form: %lx", __func__, va));
1884 if (ADDR_IS_KERNEL(va))
1886 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1887 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1888 return (pmap_unwire_l3(pmap, va, mpte, free));
1892 * Release a page table page reference after a failed attempt to create a
1896 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
1898 struct spglist free;
1901 if (pmap_unwire_l3(pmap, va, mpte, &free))
1902 vm_page_free_pages_toq(&free, true);
1906 pmap_pinit0(pmap_t pmap)
1909 PMAP_LOCK_INIT(pmap);
1910 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1911 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
1912 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1913 vm_radix_init(&pmap->pm_root);
1914 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
1915 pmap->pm_stage = PM_STAGE1;
1916 pmap->pm_levels = 4;
1917 pmap->pm_ttbr = pmap->pm_l0_paddr;
1918 pmap->pm_asid_set = &asids;
1920 PCPU_SET(curpmap, pmap);
1924 pmap_pinit_stage(pmap_t pmap, enum pmap_stage stage, int levels)
1929 * allocate the l0 page
1931 m = vm_page_alloc_noobj(VM_ALLOC_WAITOK | VM_ALLOC_WIRED |
1933 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(m);
1934 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1936 vm_radix_init(&pmap->pm_root);
1937 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1938 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
1940 MPASS(levels == 3 || levels == 4);
1941 pmap->pm_levels = levels;
1942 pmap->pm_stage = stage;
1945 pmap->pm_asid_set = &asids;
1948 pmap->pm_asid_set = &vmids;
1951 panic("%s: Invalid pmap type %d", __func__, stage);
1955 /* XXX Temporarily disable deferred ASID allocation. */
1956 pmap_alloc_asid(pmap);
1959 * Allocate the level 1 entry to use as the root. This will increase
1960 * the refcount on the level 1 page so it won't be removed until
1961 * pmap_release() is called.
1963 if (pmap->pm_levels == 3) {
1965 m = _pmap_alloc_l3(pmap, NUL2E + NUL1E, NULL);
1968 pmap->pm_ttbr = VM_PAGE_TO_PHYS(m);
1974 pmap_pinit(pmap_t pmap)
1977 return (pmap_pinit_stage(pmap, PM_STAGE1, 4));
1981 * This routine is called if the desired page table page does not exist.
1983 * If page table page allocation fails, this routine may sleep before
1984 * returning NULL. It sleeps only if a lock pointer was given.
1986 * Note: If a page allocation fails at page table level two or three,
1987 * one or two pages may be held during the wait, only to be released
1988 * afterwards. This conservative approach is easily argued to avoid
1992 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1994 vm_page_t m, l1pg, l2pg;
1996 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1999 * Allocate a page table page.
2001 if ((m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2002 if (lockp != NULL) {
2003 RELEASE_PV_LIST_LOCK(lockp);
2010 * Indicate the need to retry. While waiting, the page table
2011 * page may have been allocated.
2015 m->pindex = ptepindex;
2018 * Because of AArch64's weak memory consistency model, we must have a
2019 * barrier here to ensure that the stores for zeroing "m", whether by
2020 * pmap_zero_page() or an earlier function, are visible before adding
2021 * "m" to the page table. Otherwise, a page table walk by another
2022 * processor's MMU could see the mapping to "m" and a stale, non-zero
2028 * Map the pagetable page into the process address space, if
2029 * it isn't already there.
2032 if (ptepindex >= (NUL2E + NUL1E)) {
2033 pd_entry_t *l0p, l0e;
2034 vm_pindex_t l0index;
2036 l0index = ptepindex - (NUL2E + NUL1E);
2037 l0p = &pmap->pm_l0[l0index];
2038 KASSERT((pmap_load(l0p) & ATTR_DESCR_VALID) == 0,
2039 ("%s: L0 entry %#lx is valid", __func__, pmap_load(l0p)));
2040 l0e = VM_PAGE_TO_PHYS(m) | L0_TABLE;
2043 * Mark all kernel memory as not accessible from userspace
2044 * and userspace memory as not executable from the kernel.
2045 * This has been done for the bootstrap L0 entries in
2048 if (pmap == kernel_pmap)
2049 l0e |= TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0;
2051 l0e |= TATTR_PXN_TABLE;
2052 pmap_store(l0p, l0e);
2053 } else if (ptepindex >= NUL2E) {
2054 vm_pindex_t l0index, l1index;
2055 pd_entry_t *l0, *l1;
2058 l1index = ptepindex - NUL2E;
2059 l0index = l1index >> Ln_ENTRIES_SHIFT;
2061 l0 = &pmap->pm_l0[l0index];
2062 tl0 = pmap_load(l0);
2064 /* recurse for allocating page dir */
2065 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
2067 vm_page_unwire_noq(m);
2068 vm_page_free_zero(m);
2072 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
2076 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
2077 l1 = &l1[ptepindex & Ln_ADDR_MASK];
2078 KASSERT((pmap_load(l1) & ATTR_DESCR_VALID) == 0,
2079 ("%s: L1 entry %#lx is valid", __func__, pmap_load(l1)));
2080 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
2082 vm_pindex_t l0index, l1index;
2083 pd_entry_t *l0, *l1, *l2;
2084 pd_entry_t tl0, tl1;
2086 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
2087 l0index = l1index >> Ln_ENTRIES_SHIFT;
2089 l0 = &pmap->pm_l0[l0index];
2090 tl0 = pmap_load(l0);
2092 /* recurse for allocating page dir */
2093 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
2095 vm_page_unwire_noq(m);
2096 vm_page_free_zero(m);
2099 tl0 = pmap_load(l0);
2100 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
2101 l1 = &l1[l1index & Ln_ADDR_MASK];
2103 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
2104 l1 = &l1[l1index & Ln_ADDR_MASK];
2105 tl1 = pmap_load(l1);
2107 /* recurse for allocating page dir */
2108 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
2110 vm_page_unwire_noq(m);
2111 vm_page_free_zero(m);
2115 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
2120 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
2121 l2 = &l2[ptepindex & Ln_ADDR_MASK];
2122 KASSERT((pmap_load(l2) & ATTR_DESCR_VALID) == 0,
2123 ("%s: L2 entry %#lx is valid", __func__, pmap_load(l2)));
2124 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
2127 pmap_resident_count_inc(pmap, 1);
2133 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp,
2134 struct rwlock **lockp)
2136 pd_entry_t *l1, *l2;
2138 vm_pindex_t l2pindex;
2140 KASSERT(ADDR_IS_CANONICAL(va),
2141 ("%s: Address not in canonical form: %lx", __func__, va));
2144 l1 = pmap_l1(pmap, va);
2145 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
2146 l2 = pmap_l1_to_l2(l1, va);
2147 if (!ADDR_IS_KERNEL(va)) {
2148 /* Add a reference to the L2 page. */
2149 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
2153 } else if (!ADDR_IS_KERNEL(va)) {
2154 /* Allocate a L2 page. */
2155 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
2156 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
2163 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
2164 l2 = &l2[pmap_l2_index(va)];
2166 panic("pmap_alloc_l2: missing page table page for va %#lx",
2173 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2175 vm_pindex_t ptepindex;
2176 pd_entry_t *pde, tpde;
2184 * Calculate pagetable page index
2186 ptepindex = pmap_l2_pindex(va);
2189 * Get the page directory entry
2191 pde = pmap_pde(pmap, va, &lvl);
2194 * If the page table page is mapped, we just increment the hold count,
2195 * and activate it. If we get a level 2 pde it will point to a level 3
2203 pte = pmap_l0_to_l1(pde, va);
2204 KASSERT(pmap_load(pte) == 0,
2205 ("pmap_alloc_l3: TODO: l0 superpages"));
2210 pte = pmap_l1_to_l2(pde, va);
2211 KASSERT(pmap_load(pte) == 0,
2212 ("pmap_alloc_l3: TODO: l1 superpages"));
2216 tpde = pmap_load(pde);
2218 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
2224 panic("pmap_alloc_l3: Invalid level %d", lvl);
2228 * Here if the pte page isn't mapped, or if it has been deallocated.
2230 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
2231 if (m == NULL && lockp != NULL)
2237 /***************************************************
2238 * Pmap allocation/deallocation routines.
2239 ***************************************************/
2242 * Release any resources held by the given physical map.
2243 * Called when a pmap initialized by pmap_pinit is being released.
2244 * Should only be called if the map contains no valid mappings.
2247 pmap_release(pmap_t pmap)
2250 struct spglist free;
2251 struct asid_set *set;
2255 if (pmap->pm_levels != 4) {
2256 PMAP_ASSERT_STAGE2(pmap);
2257 KASSERT(pmap->pm_stats.resident_count == 1,
2258 ("pmap_release: pmap resident count %ld != 0",
2259 pmap->pm_stats.resident_count));
2260 KASSERT((pmap->pm_l0[0] & ATTR_DESCR_VALID) == ATTR_DESCR_VALID,
2261 ("pmap_release: Invalid l0 entry: %lx", pmap->pm_l0[0]));
2264 m = PHYS_TO_VM_PAGE(pmap->pm_ttbr);
2266 rv = pmap_unwire_l3(pmap, 0, m, &free);
2269 vm_page_free_pages_toq(&free, true);
2272 KASSERT(pmap->pm_stats.resident_count == 0,
2273 ("pmap_release: pmap resident count %ld != 0",
2274 pmap->pm_stats.resident_count));
2275 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2276 ("pmap_release: pmap has reserved page table page(s)"));
2278 set = pmap->pm_asid_set;
2279 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
2282 * Allow the ASID to be reused. In stage 2 VMIDs we don't invalidate
2283 * the entries when removing them so rely on a later tlb invalidation.
2284 * this will happen when updating the VMID generation. Because of this
2285 * we don't reuse VMIDs within a generation.
2287 if (pmap->pm_stage == PM_STAGE1) {
2288 mtx_lock_spin(&set->asid_set_mutex);
2289 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) {
2290 asid = COOKIE_TO_ASID(pmap->pm_cookie);
2291 KASSERT(asid >= ASID_FIRST_AVAILABLE &&
2292 asid < set->asid_set_size,
2293 ("pmap_release: pmap cookie has out-of-range asid"));
2294 bit_clear(set->asid_set, asid);
2296 mtx_unlock_spin(&set->asid_set_mutex);
2299 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
2300 vm_page_unwire_noq(m);
2301 vm_page_free_zero(m);
2305 kvm_size(SYSCTL_HANDLER_ARGS)
2307 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2309 return sysctl_handle_long(oidp, &ksize, 0, req);
2311 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2312 0, 0, kvm_size, "LU",
2316 kvm_free(SYSCTL_HANDLER_ARGS)
2318 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2320 return sysctl_handle_long(oidp, &kfree, 0, req);
2322 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
2323 0, 0, kvm_free, "LU",
2324 "Amount of KVM free");
2327 * grow the number of kernel page table entries, if needed
2330 pmap_growkernel(vm_offset_t addr)
2334 pd_entry_t *l0, *l1, *l2;
2336 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2338 addr = roundup2(addr, L2_SIZE);
2339 if (addr - 1 >= vm_map_max(kernel_map))
2340 addr = vm_map_max(kernel_map);
2341 while (kernel_vm_end < addr) {
2342 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
2343 KASSERT(pmap_load(l0) != 0,
2344 ("pmap_growkernel: No level 0 kernel entry"));
2346 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
2347 if (pmap_load(l1) == 0) {
2348 /* We need a new PDP entry */
2349 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT |
2350 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2352 panic("pmap_growkernel: no memory to grow kernel");
2353 nkpg->pindex = kernel_vm_end >> L1_SHIFT;
2354 /* See the dmb() in _pmap_alloc_l3(). */
2356 paddr = VM_PAGE_TO_PHYS(nkpg);
2357 pmap_store(l1, paddr | L1_TABLE);
2358 continue; /* try again */
2360 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
2361 if (pmap_load(l2) != 0) {
2362 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2363 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2364 kernel_vm_end = vm_map_max(kernel_map);
2370 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED |
2373 panic("pmap_growkernel: no memory to grow kernel");
2374 nkpg->pindex = kernel_vm_end >> L2_SHIFT;
2375 /* See the dmb() in _pmap_alloc_l3(). */
2377 paddr = VM_PAGE_TO_PHYS(nkpg);
2378 pmap_store(l2, paddr | L2_TABLE);
2380 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2381 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2382 kernel_vm_end = vm_map_max(kernel_map);
2388 /***************************************************
2389 * page management routines.
2390 ***************************************************/
2392 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2393 CTASSERT(_NPCM == 3);
2394 CTASSERT(_NPCPV == 168);
2396 static __inline struct pv_chunk *
2397 pv_to_chunk(pv_entry_t pv)
2400 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2403 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2405 #define PC_FREE0 0xfffffffffffffffful
2406 #define PC_FREE1 0xfffffffffffffffful
2407 #define PC_FREE2 0x000000fffffffffful
2409 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2412 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2414 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2415 "Current number of pv entry chunks");
2416 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2417 "Current number of pv entry chunks allocated");
2418 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2419 "Current number of pv entry chunks frees");
2420 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2421 "Number of times tried to get a chunk page but failed.");
2423 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2424 static int pv_entry_spare;
2426 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2427 "Current number of pv entry frees");
2428 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2429 "Current number of pv entry allocs");
2430 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2431 "Current number of pv entries");
2432 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2433 "Current number of spare pv entries");
2437 * We are in a serious low memory condition. Resort to
2438 * drastic measures to free some pages so we can allocate
2439 * another pv entry chunk.
2441 * Returns NULL if PV entries were reclaimed from the specified pmap.
2443 * We do not, however, unmap 2mpages because subsequent accesses will
2444 * allocate per-page pv entries until repromotion occurs, thereby
2445 * exacerbating the shortage of free pv entries.
2448 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2450 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
2451 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
2452 struct md_page *pvh;
2454 pmap_t next_pmap, pmap;
2455 pt_entry_t *pte, tpte;
2459 struct spglist free;
2461 int bit, field, freed, lvl;
2462 static int active_reclaims = 0;
2464 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2465 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2470 bzero(&pc_marker_b, sizeof(pc_marker_b));
2471 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
2472 pc_marker = (struct pv_chunk *)&pc_marker_b;
2473 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
2475 mtx_lock(&pv_chunks_mutex);
2477 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
2478 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
2479 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
2480 SLIST_EMPTY(&free)) {
2481 next_pmap = pc->pc_pmap;
2482 if (next_pmap == NULL) {
2484 * The next chunk is a marker. However, it is
2485 * not our marker, so active_reclaims must be
2486 * > 1. Consequently, the next_chunk code
2487 * will not rotate the pv_chunks list.
2491 mtx_unlock(&pv_chunks_mutex);
2494 * A pv_chunk can only be removed from the pc_lru list
2495 * when both pv_chunks_mutex is owned and the
2496 * corresponding pmap is locked.
2498 if (pmap != next_pmap) {
2499 if (pmap != NULL && pmap != locked_pmap)
2502 /* Avoid deadlock and lock recursion. */
2503 if (pmap > locked_pmap) {
2504 RELEASE_PV_LIST_LOCK(lockp);
2506 mtx_lock(&pv_chunks_mutex);
2508 } else if (pmap != locked_pmap) {
2509 if (PMAP_TRYLOCK(pmap)) {
2510 mtx_lock(&pv_chunks_mutex);
2513 pmap = NULL; /* pmap is not locked */
2514 mtx_lock(&pv_chunks_mutex);
2515 pc = TAILQ_NEXT(pc_marker, pc_lru);
2517 pc->pc_pmap != next_pmap)
2525 * Destroy every non-wired, 4 KB page mapping in the chunk.
2528 for (field = 0; field < _NPCM; field++) {
2529 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2530 inuse != 0; inuse &= ~(1UL << bit)) {
2531 bit = ffsl(inuse) - 1;
2532 pv = &pc->pc_pventry[field * 64 + bit];
2534 pde = pmap_pde(pmap, va, &lvl);
2537 pte = pmap_l2_to_l3(pde, va);
2538 tpte = pmap_load(pte);
2539 if ((tpte & ATTR_SW_WIRED) != 0)
2541 tpte = pmap_load_clear(pte);
2542 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
2543 if (pmap_pte_dirty(pmap, tpte))
2545 if ((tpte & ATTR_AF) != 0) {
2546 pmap_invalidate_page(pmap, va, true);
2547 vm_page_aflag_set(m, PGA_REFERENCED);
2549 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2550 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2552 if (TAILQ_EMPTY(&m->md.pv_list) &&
2553 (m->flags & PG_FICTITIOUS) == 0) {
2554 pvh = page_to_pvh(m);
2555 if (TAILQ_EMPTY(&pvh->pv_list)) {
2556 vm_page_aflag_clear(m,
2560 pc->pc_map[field] |= 1UL << bit;
2561 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2566 mtx_lock(&pv_chunks_mutex);
2569 /* Every freed mapping is for a 4 KB page. */
2570 pmap_resident_count_dec(pmap, freed);
2571 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2572 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2573 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2574 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2575 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2576 pc->pc_map[2] == PC_FREE2) {
2577 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2578 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2579 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2580 /* Entire chunk is free; return it. */
2581 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2582 dump_drop_page(m_pc->phys_addr);
2583 mtx_lock(&pv_chunks_mutex);
2584 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2587 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2588 mtx_lock(&pv_chunks_mutex);
2589 /* One freed pv entry in locked_pmap is sufficient. */
2590 if (pmap == locked_pmap)
2594 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2595 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2596 if (active_reclaims == 1 && pmap != NULL) {
2598 * Rotate the pv chunks list so that we do not
2599 * scan the same pv chunks that could not be
2600 * freed (because they contained a wired
2601 * and/or superpage mapping) on every
2602 * invocation of reclaim_pv_chunk().
2604 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2605 MPASS(pc->pc_pmap != NULL);
2606 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2607 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2611 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2612 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2614 mtx_unlock(&pv_chunks_mutex);
2615 if (pmap != NULL && pmap != locked_pmap)
2617 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2618 m_pc = SLIST_FIRST(&free);
2619 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2620 /* Recycle a freed page table page. */
2621 m_pc->ref_count = 1;
2623 vm_page_free_pages_toq(&free, true);
2628 * free the pv_entry back to the free list
2631 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2633 struct pv_chunk *pc;
2634 int idx, field, bit;
2636 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2637 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2638 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2639 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2640 pc = pv_to_chunk(pv);
2641 idx = pv - &pc->pc_pventry[0];
2644 pc->pc_map[field] |= 1ul << bit;
2645 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2646 pc->pc_map[2] != PC_FREE2) {
2647 /* 98% of the time, pc is already at the head of the list. */
2648 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2649 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2650 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2654 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2659 free_pv_chunk(struct pv_chunk *pc)
2663 mtx_lock(&pv_chunks_mutex);
2664 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2665 mtx_unlock(&pv_chunks_mutex);
2666 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2667 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2668 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2669 /* entire chunk is free, return it */
2670 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2671 dump_drop_page(m->phys_addr);
2672 vm_page_unwire_noq(m);
2677 * Returns a new PV entry, allocating a new PV chunk from the system when
2678 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2679 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2682 * The given PV list lock may be released.
2685 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2689 struct pv_chunk *pc;
2692 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2693 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2695 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2697 for (field = 0; field < _NPCM; field++) {
2698 if (pc->pc_map[field]) {
2699 bit = ffsl(pc->pc_map[field]) - 1;
2703 if (field < _NPCM) {
2704 pv = &pc->pc_pventry[field * 64 + bit];
2705 pc->pc_map[field] &= ~(1ul << bit);
2706 /* If this was the last item, move it to tail */
2707 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2708 pc->pc_map[2] == 0) {
2709 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2710 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2713 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2714 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2718 /* No free items, allocate another chunk */
2719 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
2721 if (lockp == NULL) {
2722 PV_STAT(pc_chunk_tryfail++);
2725 m = reclaim_pv_chunk(pmap, lockp);
2729 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2730 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2731 dump_add_page(m->phys_addr);
2732 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2734 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2735 pc->pc_map[1] = PC_FREE1;
2736 pc->pc_map[2] = PC_FREE2;
2737 mtx_lock(&pv_chunks_mutex);
2738 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2739 mtx_unlock(&pv_chunks_mutex);
2740 pv = &pc->pc_pventry[0];
2741 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2742 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2743 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2748 * Ensure that the number of spare PV entries in the specified pmap meets or
2749 * exceeds the given count, "needed".
2751 * The given PV list lock may be released.
2754 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2756 struct pch new_tail;
2757 struct pv_chunk *pc;
2762 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2763 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2766 * Newly allocated PV chunks must be stored in a private list until
2767 * the required number of PV chunks have been allocated. Otherwise,
2768 * reclaim_pv_chunk() could recycle one of these chunks. In
2769 * contrast, these chunks must be added to the pmap upon allocation.
2771 TAILQ_INIT(&new_tail);
2774 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2775 bit_count((bitstr_t *)pc->pc_map, 0,
2776 sizeof(pc->pc_map) * NBBY, &free);
2780 if (avail >= needed)
2783 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2784 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
2786 m = reclaim_pv_chunk(pmap, lockp);
2791 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2792 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2793 dump_add_page(m->phys_addr);
2794 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2796 pc->pc_map[0] = PC_FREE0;
2797 pc->pc_map[1] = PC_FREE1;
2798 pc->pc_map[2] = PC_FREE2;
2799 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2800 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2801 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2804 * The reclaim might have freed a chunk from the current pmap.
2805 * If that chunk contained available entries, we need to
2806 * re-count the number of available entries.
2811 if (!TAILQ_EMPTY(&new_tail)) {
2812 mtx_lock(&pv_chunks_mutex);
2813 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2814 mtx_unlock(&pv_chunks_mutex);
2819 * First find and then remove the pv entry for the specified pmap and virtual
2820 * address from the specified pv list. Returns the pv entry if found and NULL
2821 * otherwise. This operation can be performed on pv lists for either 4KB or
2822 * 2MB page mappings.
2824 static __inline pv_entry_t
2825 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2829 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2830 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2831 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2840 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2841 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2842 * entries for each of the 4KB page mappings.
2845 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2846 struct rwlock **lockp)
2848 struct md_page *pvh;
2849 struct pv_chunk *pc;
2851 vm_offset_t va_last;
2855 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2856 KASSERT((va & L2_OFFSET) == 0,
2857 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2858 KASSERT((pa & L2_OFFSET) == 0,
2859 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2860 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2863 * Transfer the 2mpage's pv entry for this mapping to the first
2864 * page's pv list. Once this transfer begins, the pv list lock
2865 * must not be released until the last pv entry is reinstantiated.
2867 pvh = pa_to_pvh(pa);
2868 pv = pmap_pvh_remove(pvh, pmap, va);
2869 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2870 m = PHYS_TO_VM_PAGE(pa);
2871 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2873 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2874 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2875 va_last = va + L2_SIZE - PAGE_SIZE;
2877 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2878 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2879 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2880 for (field = 0; field < _NPCM; field++) {
2881 while (pc->pc_map[field]) {
2882 bit = ffsl(pc->pc_map[field]) - 1;
2883 pc->pc_map[field] &= ~(1ul << bit);
2884 pv = &pc->pc_pventry[field * 64 + bit];
2888 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2889 ("pmap_pv_demote_l2: page %p is not managed", m));
2890 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2896 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2897 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2900 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2901 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2902 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2904 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2905 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2909 * First find and then destroy the pv entry for the specified pmap and virtual
2910 * address. This operation can be performed on pv lists for either 4KB or 2MB
2914 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2918 pv = pmap_pvh_remove(pvh, pmap, va);
2919 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2920 free_pv_entry(pmap, pv);
2924 * Conditionally create the PV entry for a 4KB page mapping if the required
2925 * memory can be allocated without resorting to reclamation.
2928 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2929 struct rwlock **lockp)
2933 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2934 /* Pass NULL instead of the lock pointer to disable reclamation. */
2935 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2937 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2938 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2946 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2947 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2948 * false if the PV entry cannot be allocated without resorting to reclamation.
2951 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2952 struct rwlock **lockp)
2954 struct md_page *pvh;
2958 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2959 /* Pass NULL instead of the lock pointer to disable reclamation. */
2960 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2961 NULL : lockp)) == NULL)
2964 pa = l2e & ~ATTR_MASK;
2965 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2966 pvh = pa_to_pvh(pa);
2967 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2973 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2975 pt_entry_t newl2, oldl2;
2979 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2980 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2981 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2983 ml3 = pmap_remove_pt_page(pmap, va);
2985 panic("pmap_remove_kernel_l2: Missing pt page");
2987 ml3pa = VM_PAGE_TO_PHYS(ml3);
2988 newl2 = ml3pa | L2_TABLE;
2991 * If this page table page was unmapped by a promotion, then it
2992 * contains valid mappings. Zero it to invalidate those mappings.
2994 if (ml3->valid != 0)
2995 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2998 * Demote the mapping. The caller must have already invalidated the
2999 * mapping (i.e., the "break" in break-before-make).
3001 oldl2 = pmap_load_store(l2, newl2);
3002 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
3003 __func__, l2, oldl2));
3007 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
3010 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
3011 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
3013 struct md_page *pvh;
3015 vm_page_t m, ml3, mt;
3017 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3018 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
3019 old_l2 = pmap_load_clear(l2);
3020 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3021 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
3024 * Since a promotion must break the 4KB page mappings before making
3025 * the 2MB page mapping, a pmap_invalidate_page() suffices.
3027 pmap_invalidate_page(pmap, sva, true);
3029 if (old_l2 & ATTR_SW_WIRED)
3030 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
3031 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
3032 if (old_l2 & ATTR_SW_MANAGED) {
3033 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
3034 pvh = page_to_pvh(m);
3035 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
3036 pmap_pvh_free(pvh, pmap, sva);
3037 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) {
3038 if (pmap_pte_dirty(pmap, old_l2))
3040 if (old_l2 & ATTR_AF)
3041 vm_page_aflag_set(mt, PGA_REFERENCED);
3042 if (TAILQ_EMPTY(&mt->md.pv_list) &&
3043 TAILQ_EMPTY(&pvh->pv_list))
3044 vm_page_aflag_clear(mt, PGA_WRITEABLE);
3047 if (pmap == kernel_pmap) {
3048 pmap_remove_kernel_l2(pmap, l2, sva);
3050 ml3 = pmap_remove_pt_page(pmap, sva);
3052 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
3053 ("pmap_remove_l2: l3 page not promoted"));
3054 pmap_resident_count_dec(pmap, 1);
3055 KASSERT(ml3->ref_count == NL3PG,
3056 ("pmap_remove_l2: l3 page ref count error"));
3058 pmap_add_delayed_free_list(ml3, free, FALSE);
3061 return (pmap_unuse_pt(pmap, sva, l1e, free));
3065 * pmap_remove_l3: do the things to unmap a page in a process
3068 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
3069 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
3071 struct md_page *pvh;
3075 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3076 old_l3 = pmap_load_clear(l3);
3077 pmap_invalidate_page(pmap, va, true);
3078 if (old_l3 & ATTR_SW_WIRED)
3079 pmap->pm_stats.wired_count -= 1;
3080 pmap_resident_count_dec(pmap, 1);
3081 if (old_l3 & ATTR_SW_MANAGED) {
3082 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
3083 if (pmap_pte_dirty(pmap, old_l3))
3085 if (old_l3 & ATTR_AF)
3086 vm_page_aflag_set(m, PGA_REFERENCED);
3087 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3088 pmap_pvh_free(&m->md, pmap, va);
3089 if (TAILQ_EMPTY(&m->md.pv_list) &&
3090 (m->flags & PG_FICTITIOUS) == 0) {
3091 pvh = page_to_pvh(m);
3092 if (TAILQ_EMPTY(&pvh->pv_list))
3093 vm_page_aflag_clear(m, PGA_WRITEABLE);
3096 return (pmap_unuse_pt(pmap, va, l2e, free));
3100 * Remove the specified range of addresses from the L3 page table that is
3101 * identified by the given L2 entry.
3104 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
3105 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
3107 struct md_page *pvh;
3108 struct rwlock *new_lock;
3109 pt_entry_t *l3, old_l3;
3113 KASSERT(ADDR_IS_CANONICAL(sva),
3114 ("%s: Start address not in canonical form: %lx", __func__, sva));
3115 KASSERT(ADDR_IS_CANONICAL(eva) || eva == VM_MAX_USER_ADDRESS,
3116 ("%s: End address not in canonical form: %lx", __func__, eva));
3118 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3119 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
3120 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
3121 l3pg = !ADDR_IS_KERNEL(sva) ? PHYS_TO_VM_PAGE(l2e & ~ATTR_MASK) : NULL;
3123 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
3124 if (!pmap_l3_valid(pmap_load(l3))) {
3126 pmap_invalidate_range(pmap, va, sva, true);
3131 old_l3 = pmap_load_clear(l3);
3132 if ((old_l3 & ATTR_SW_WIRED) != 0)
3133 pmap->pm_stats.wired_count--;
3134 pmap_resident_count_dec(pmap, 1);
3135 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
3136 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
3137 if (pmap_pte_dirty(pmap, old_l3))
3139 if ((old_l3 & ATTR_AF) != 0)
3140 vm_page_aflag_set(m, PGA_REFERENCED);
3141 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
3142 if (new_lock != *lockp) {
3143 if (*lockp != NULL) {
3145 * Pending TLB invalidations must be
3146 * performed before the PV list lock is
3147 * released. Otherwise, a concurrent
3148 * pmap_remove_all() on a physical page
3149 * could return while a stale TLB entry
3150 * still provides access to that page.
3153 pmap_invalidate_range(pmap, va,
3162 pmap_pvh_free(&m->md, pmap, sva);
3163 if (TAILQ_EMPTY(&m->md.pv_list) &&
3164 (m->flags & PG_FICTITIOUS) == 0) {
3165 pvh = page_to_pvh(m);
3166 if (TAILQ_EMPTY(&pvh->pv_list))
3167 vm_page_aflag_clear(m, PGA_WRITEABLE);
3170 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) {
3172 * _pmap_unwire_l3() has already invalidated the TLB
3173 * entries at all levels for "sva". So, we need not
3174 * perform "sva += L3_SIZE;" here. Moreover, we need
3175 * not perform "va = sva;" if "sva" is at the start
3176 * of a new valid range consisting of a single page.
3184 pmap_invalidate_range(pmap, va, sva, true);
3188 * Remove the given range of addresses from the specified map.
3190 * It is assumed that the start and end are properly
3191 * rounded to the page size.
3194 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3196 struct rwlock *lock;
3197 vm_offset_t va_next;
3198 pd_entry_t *l0, *l1, *l2;
3199 pt_entry_t l3_paddr;
3200 struct spglist free;
3203 * Perform an unsynchronized read. This is, however, safe.
3205 if (pmap->pm_stats.resident_count == 0)
3213 for (; sva < eva; sva = va_next) {
3214 if (pmap->pm_stats.resident_count == 0)
3217 l0 = pmap_l0(pmap, sva);
3218 if (pmap_load(l0) == 0) {
3219 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3225 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3228 l1 = pmap_l0_to_l1(l0, sva);
3229 if (pmap_load(l1) == 0)
3231 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
3232 KASSERT(va_next <= eva,
3233 ("partial update of non-transparent 1G page "
3234 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
3235 pmap_load(l1), sva, eva, va_next));
3236 MPASS(pmap != kernel_pmap);
3237 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
3239 pmap_invalidate_page(pmap, sva, true);
3240 pmap_resident_count_dec(pmap, L1_SIZE / PAGE_SIZE);
3241 pmap_unuse_pt(pmap, sva, pmap_load(l0), &free);
3246 * Calculate index for next page table.
3248 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3252 l2 = pmap_l1_to_l2(l1, sva);
3256 l3_paddr = pmap_load(l2);
3258 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
3259 if (sva + L2_SIZE == va_next && eva >= va_next) {
3260 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
3263 } else if (pmap_demote_l2_locked(pmap, l2, sva,
3266 l3_paddr = pmap_load(l2);
3270 * Weed out invalid mappings.
3272 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
3276 * Limit our scan to either the end of the va represented
3277 * by the current page table page, or to the end of the
3278 * range being removed.
3283 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
3289 vm_page_free_pages_toq(&free, true);
3293 * Routine: pmap_remove_all
3295 * Removes this physical page from
3296 * all physical maps in which it resides.
3297 * Reflects back modify bits to the pager.
3300 * Original versions of this routine were very
3301 * inefficient because they iteratively called
3302 * pmap_remove (slow...)
3306 pmap_remove_all(vm_page_t m)
3308 struct md_page *pvh;
3311 struct rwlock *lock;
3312 pd_entry_t *pde, tpde;
3313 pt_entry_t *pte, tpte;
3315 struct spglist free;
3316 int lvl, pvh_gen, md_gen;
3318 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3319 ("pmap_remove_all: page %p is not managed", m));
3321 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3322 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
3325 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3327 if (!PMAP_TRYLOCK(pmap)) {
3328 pvh_gen = pvh->pv_gen;
3332 if (pvh_gen != pvh->pv_gen) {
3338 pte = pmap_pte(pmap, va, &lvl);
3339 KASSERT(pte != NULL,
3340 ("pmap_remove_all: no page table entry found"));
3342 ("pmap_remove_all: invalid pte level %d", lvl));
3343 pmap_demote_l2_locked(pmap, pte, va, &lock);
3346 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3348 PMAP_ASSERT_STAGE1(pmap);
3349 if (!PMAP_TRYLOCK(pmap)) {
3350 pvh_gen = pvh->pv_gen;
3351 md_gen = m->md.pv_gen;
3355 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
3360 pmap_resident_count_dec(pmap, 1);
3362 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3363 KASSERT(pde != NULL,
3364 ("pmap_remove_all: no page directory entry found"));
3366 ("pmap_remove_all: invalid pde level %d", lvl));
3367 tpde = pmap_load(pde);
3369 pte = pmap_l2_to_l3(pde, pv->pv_va);
3370 tpte = pmap_load_clear(pte);
3371 if (tpte & ATTR_SW_WIRED)
3372 pmap->pm_stats.wired_count--;
3373 if ((tpte & ATTR_AF) != 0) {
3374 pmap_invalidate_page(pmap, pv->pv_va, true);
3375 vm_page_aflag_set(m, PGA_REFERENCED);
3379 * Update the vm_page_t clean and reference bits.
3381 if (pmap_pte_dirty(pmap, tpte))
3383 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
3384 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3386 free_pv_entry(pmap, pv);
3389 vm_page_aflag_clear(m, PGA_WRITEABLE);
3391 vm_page_free_pages_toq(&free, true);
3395 * Masks and sets bits in a level 2 page table entries in the specified pmap
3398 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
3404 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3405 PMAP_ASSERT_STAGE1(pmap);
3406 KASSERT((sva & L2_OFFSET) == 0,
3407 ("pmap_protect_l2: sva is not 2mpage aligned"));
3408 old_l2 = pmap_load(l2);
3409 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3410 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
3413 * Return if the L2 entry already has the desired access restrictions
3416 if ((old_l2 & mask) == nbits)
3419 while (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
3423 * When a dirty read/write superpage mapping is write protected,
3424 * update the dirty field of each of the superpage's constituent 4KB
3427 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
3428 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3429 pmap_pte_dirty(pmap, old_l2)) {
3430 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
3431 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3436 * Since a promotion must break the 4KB page mappings before making
3437 * the 2MB page mapping, a pmap_invalidate_page() suffices.
3439 pmap_invalidate_page(pmap, sva, true);
3443 * Masks and sets bits in last level page table entries in the specified
3447 pmap_mask_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, pt_entry_t mask,
3448 pt_entry_t nbits, bool invalidate)
3450 vm_offset_t va, va_next;
3451 pd_entry_t *l0, *l1, *l2;
3452 pt_entry_t *l3p, l3;
3455 for (; sva < eva; sva = va_next) {
3456 l0 = pmap_l0(pmap, sva);
3457 if (pmap_load(l0) == 0) {
3458 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3464 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3467 l1 = pmap_l0_to_l1(l0, sva);
3468 if (pmap_load(l1) == 0)
3470 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
3471 KASSERT(va_next <= eva,
3472 ("partial update of non-transparent 1G page "
3473 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
3474 pmap_load(l1), sva, eva, va_next));
3475 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0);
3476 if ((pmap_load(l1) & mask) != nbits) {
3477 pmap_store(l1, (pmap_load(l1) & ~mask) | nbits);
3479 pmap_invalidate_page(pmap, sva, true);
3484 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3488 l2 = pmap_l1_to_l2(l1, sva);
3489 if (pmap_load(l2) == 0)
3492 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3493 if (sva + L2_SIZE == va_next && eva >= va_next) {
3494 pmap_protect_l2(pmap, l2, sva, mask, nbits);
3496 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3499 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3500 ("pmap_protect: Invalid L2 entry after demotion"));
3506 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3508 l3 = pmap_load(l3p);
3511 * Go to the next L3 entry if the current one is
3512 * invalid or already has the desired access
3513 * restrictions in place. (The latter case occurs
3514 * frequently. For example, in a "buildworld"
3515 * workload, almost 1 out of 4 L3 entries already
3516 * have the desired restrictions.)
3518 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3519 if (va != va_next) {
3521 pmap_invalidate_range(pmap,
3528 while (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) |
3533 * When a dirty read/write mapping is write protected,
3534 * update the page's dirty field.
3536 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3537 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3538 pmap_pte_dirty(pmap, l3))
3539 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
3544 if (va != va_next && invalidate)
3545 pmap_invalidate_range(pmap, va, sva, true);
3551 * Set the physical protection on the
3552 * specified range of this map as requested.
3555 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3557 pt_entry_t mask, nbits;
3559 PMAP_ASSERT_STAGE1(pmap);
3560 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3561 if (prot == VM_PROT_NONE) {
3562 pmap_remove(pmap, sva, eva);
3567 if ((prot & VM_PROT_WRITE) == 0) {
3568 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM;
3569 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO);
3571 if ((prot & VM_PROT_EXECUTE) == 0) {
3573 nbits |= ATTR_S1_XN;
3578 pmap_mask_set(pmap, sva, eva, mask, nbits, true);
3582 pmap_disable_promotion(vm_offset_t sva, vm_size_t size)
3585 MPASS((sva & L3_OFFSET) == 0);
3586 MPASS(((sva + size) & L3_OFFSET) == 0);
3588 pmap_mask_set(kernel_pmap, sva, sva + size, ATTR_SW_NO_PROMOTE,
3589 ATTR_SW_NO_PROMOTE, false);
3593 * Inserts the specified page table page into the specified pmap's collection
3594 * of idle page table pages. Each of a pmap's page table pages is responsible
3595 * for mapping a distinct range of virtual addresses. The pmap's collection is
3596 * ordered by this virtual address range.
3598 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3601 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3604 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3605 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3606 return (vm_radix_insert(&pmap->pm_root, mpte));
3610 * Removes the page table page mapping the specified virtual address from the
3611 * specified pmap's collection of idle page table pages, and returns it.
3612 * Otherwise, returns NULL if there is no page table page corresponding to the
3613 * specified virtual address.
3615 static __inline vm_page_t
3616 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3619 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3620 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
3624 * Performs a break-before-make update of a pmap entry. This is needed when
3625 * either promoting or demoting pages to ensure the TLB doesn't get into an
3626 * inconsistent state.
3629 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3630 vm_offset_t va, vm_size_t size)
3634 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3636 if ((newpte & ATTR_SW_NO_PROMOTE) != 0)
3637 panic("%s: Updating non-promote pte", __func__);
3640 * Ensure we don't get switched out with the page table in an
3641 * inconsistent state. We also need to ensure no interrupts fire
3642 * as they may make use of an address we are about to invalidate.
3644 intr = intr_disable();
3647 * Clear the old mapping's valid bit, but leave the rest of the entry
3648 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3649 * lookup the physical address.
3651 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3654 * When promoting, the L{1,2}_TABLE entry that is being replaced might
3655 * be cached, so we invalidate intermediate entries as well as final
3658 pmap_invalidate_range(pmap, va, va + size, false);
3660 /* Create the new mapping */
3661 pmap_store(pte, newpte);
3667 #if VM_NRESERVLEVEL > 0
3669 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3670 * replace the many pv entries for the 4KB page mappings by a single pv entry
3671 * for the 2MB page mapping.
3674 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3675 struct rwlock **lockp)
3677 struct md_page *pvh;
3679 vm_offset_t va_last;
3682 KASSERT((pa & L2_OFFSET) == 0,
3683 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3684 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3687 * Transfer the first page's pv entry for this mapping to the 2mpage's
3688 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3689 * a transfer avoids the possibility that get_pv_entry() calls
3690 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3691 * mappings that is being promoted.
3693 m = PHYS_TO_VM_PAGE(pa);
3694 va = va & ~L2_OFFSET;
3695 pv = pmap_pvh_remove(&m->md, pmap, va);
3696 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3697 pvh = page_to_pvh(m);
3698 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3700 /* Free the remaining NPTEPG - 1 pv entries. */
3701 va_last = va + L2_SIZE - PAGE_SIZE;
3705 pmap_pvh_free(&m->md, pmap, va);
3706 } while (va < va_last);
3710 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3711 * single level 2 table entry to a single 2MB page mapping. For promotion
3712 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3713 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3714 * identical characteristics.
3717 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3718 struct rwlock **lockp)
3720 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3724 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3725 PMAP_ASSERT_STAGE1(pmap);
3727 sva = va & ~L2_OFFSET;
3728 firstl3 = pmap_l2_to_l3(l2, sva);
3729 newl2 = pmap_load(firstl3);
3731 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF ||
3732 (newl2 & ATTR_SW_NO_PROMOTE) != 0) {
3733 atomic_add_long(&pmap_l2_p_failures, 1);
3734 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3735 " in pmap %p", va, pmap);
3740 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3741 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3743 * When the mapping is clean, i.e., ATTR_S1_AP_RO is set,
3744 * ATTR_SW_DBM can be cleared without a TLB invalidation.
3746 if (!atomic_fcmpset_64(firstl3, &newl2, newl2 & ~ATTR_SW_DBM))
3748 newl2 &= ~ATTR_SW_DBM;
3751 pa = newl2 + L2_SIZE - PAGE_SIZE;
3752 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3753 oldl3 = pmap_load(l3);
3755 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3756 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3758 * When the mapping is clean, i.e., ATTR_S1_AP_RO is
3759 * set, ATTR_SW_DBM can be cleared without a TLB
3762 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3765 oldl3 &= ~ATTR_SW_DBM;
3768 atomic_add_long(&pmap_l2_p_failures, 1);
3769 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3770 " in pmap %p", va, pmap);
3777 * Save the page table page in its current state until the L2
3778 * mapping the superpage is demoted by pmap_demote_l2() or
3779 * destroyed by pmap_remove_l3().
3781 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3782 KASSERT(mpte >= vm_page_array &&
3783 mpte < &vm_page_array[vm_page_array_size],
3784 ("pmap_promote_l2: page table page is out of range"));
3785 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3786 ("pmap_promote_l2: page table page's pindex is wrong"));
3787 if (pmap_insert_pt_page(pmap, mpte, true)) {
3788 atomic_add_long(&pmap_l2_p_failures, 1);
3790 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3795 if ((newl2 & ATTR_SW_MANAGED) != 0)
3796 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3798 newl2 &= ~ATTR_DESCR_MASK;
3801 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3803 atomic_add_long(&pmap_l2_promotions, 1);
3804 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3807 #endif /* VM_NRESERVLEVEL > 0 */
3810 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
3813 pd_entry_t *l0p, *l1p, *l2p, origpte;
3816 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3817 KASSERT(psind > 0 && psind < MAXPAGESIZES,
3818 ("psind %d unexpected", psind));
3819 KASSERT(((newpte & ~ATTR_MASK) & (pagesizes[psind] - 1)) == 0,
3820 ("unaligned phys address %#lx newpte %#lx psind %d",
3821 (newpte & ~ATTR_MASK), newpte, psind));
3825 l0p = pmap_l0(pmap, va);
3826 if ((pmap_load(l0p) & ATTR_DESCR_VALID) == 0) {
3827 mp = _pmap_alloc_l3(pmap, pmap_l0_pindex(va), NULL);
3829 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
3830 return (KERN_RESOURCE_SHORTAGE);
3836 l1p = pmap_l0_to_l1(l0p, va);
3837 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
3838 origpte = pmap_load(l1p);
3840 l1p = pmap_l0_to_l1(l0p, va);
3841 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va));
3842 origpte = pmap_load(l1p);
3843 if ((origpte & ATTR_DESCR_VALID) == 0) {
3844 mp = PHYS_TO_VM_PAGE(pmap_load(l0p) &
3849 KASSERT((origpte & ATTR_DESCR_VALID) == 0 ||
3850 ((origpte & ATTR_DESCR_MASK) == L1_BLOCK &&
3851 (origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK)),
3852 ("va %#lx changing 1G phys page l1 %#lx newpte %#lx",
3853 va, origpte, newpte));
3854 pmap_store(l1p, newpte);
3855 } else /* (psind == 1) */ {
3856 l2p = pmap_l2(pmap, va);
3858 mp = _pmap_alloc_l3(pmap, pmap_l1_pindex(va), NULL);
3860 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
3861 return (KERN_RESOURCE_SHORTAGE);
3867 l2p = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
3868 l2p = &l2p[pmap_l2_index(va)];
3869 origpte = pmap_load(l2p);
3871 l1p = pmap_l1(pmap, va);
3872 origpte = pmap_load(l2p);
3873 if ((origpte & ATTR_DESCR_VALID) == 0) {
3874 mp = PHYS_TO_VM_PAGE(pmap_load(l1p) &
3879 KASSERT((origpte & ATTR_DESCR_VALID) == 0 ||
3880 ((origpte & ATTR_DESCR_MASK) == L2_BLOCK &&
3881 (origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK)),
3882 ("va %#lx changing 2M phys page l2 %#lx newpte %#lx",
3883 va, origpte, newpte));
3884 pmap_store(l2p, newpte);
3888 if ((origpte & ATTR_DESCR_VALID) == 0)
3889 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE);
3890 if ((newpte & ATTR_SW_WIRED) != 0 && (origpte & ATTR_SW_WIRED) == 0)
3891 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
3892 else if ((newpte & ATTR_SW_WIRED) == 0 &&
3893 (origpte & ATTR_SW_WIRED) != 0)
3894 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
3896 return (KERN_SUCCESS);
3900 * Add a single SMMU entry. This function does not sleep.
3903 pmap_senter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3904 vm_prot_t prot, u_int flags)
3907 pt_entry_t new_l3, orig_l3;
3913 PMAP_ASSERT_STAGE1(pmap);
3914 KASSERT(va < VM_MAXUSER_ADDRESS, ("wrong address space"));
3916 va = trunc_page(va);
3917 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT |
3918 ATTR_S1_IDX(VM_MEMATTR_DEVICE) | L3_PAGE);
3919 if ((prot & VM_PROT_WRITE) == 0)
3920 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3921 new_l3 |= ATTR_S1_XN; /* Execute never. */
3922 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER);
3923 new_l3 |= ATTR_S1_nG; /* Non global. */
3925 CTR2(KTR_PMAP, "pmap_senter: %.16lx -> %.16lx", va, pa);
3930 * In the case that a page table page is not
3931 * resident, we are creating it here.
3934 pde = pmap_pde(pmap, va, &lvl);
3935 if (pde != NULL && lvl == 2) {
3936 l3 = pmap_l2_to_l3(pde, va);
3938 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va), NULL);
3940 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3941 rv = KERN_RESOURCE_SHORTAGE;
3947 orig_l3 = pmap_load(l3);
3948 KASSERT(!pmap_l3_valid(orig_l3), ("l3 is valid"));
3951 pmap_store(l3, new_l3);
3952 pmap_resident_count_inc(pmap, 1);
3963 * Remove a single SMMU entry.
3966 pmap_sremove(pmap_t pmap, vm_offset_t va)
3974 pte = pmap_pte(pmap, va, &lvl);
3976 ("Invalid SMMU pagetable level: %d != 3", lvl));
3979 pmap_resident_count_dec(pmap, 1);
3991 * Remove all the allocated L1, L2 pages from SMMU pmap.
3992 * All the L3 entires must be cleared in advance, otherwise
3993 * this function panics.
3996 pmap_sremove_pages(pmap_t pmap)
3998 pd_entry_t l0e, *l1, l1e, *l2, l2e;
3999 pt_entry_t *l3, l3e;
4000 vm_page_t m, m0, m1;
4009 for (sva = VM_MINUSER_ADDRESS, i = pmap_l0_index(sva);
4010 (i < Ln_ENTRIES && sva < VM_MAXUSER_ADDRESS); i++) {
4011 l0e = pmap->pm_l0[i];
4012 if ((l0e & ATTR_DESCR_VALID) == 0) {
4016 pa0 = l0e & ~ATTR_MASK;
4017 m0 = PHYS_TO_VM_PAGE(pa0);
4018 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa0);
4020 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
4022 if ((l1e & ATTR_DESCR_VALID) == 0) {
4026 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
4030 pa1 = l1e & ~ATTR_MASK;
4031 m1 = PHYS_TO_VM_PAGE(pa1);
4032 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa1);
4034 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
4036 if ((l2e & ATTR_DESCR_VALID) == 0) {
4040 pa = l2e & ~ATTR_MASK;
4041 m = PHYS_TO_VM_PAGE(pa);
4042 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
4044 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
4045 l++, sva += L3_SIZE) {
4047 if ((l3e & ATTR_DESCR_VALID) == 0)
4049 panic("%s: l3e found for va %jx\n",
4053 vm_page_unwire_noq(m1);
4054 vm_page_unwire_noq(m);
4055 pmap_resident_count_dec(pmap, 1);
4060 vm_page_unwire_noq(m0);
4061 pmap_resident_count_dec(pmap, 1);
4066 pmap_resident_count_dec(pmap, 1);
4068 pmap_clear(&pmap->pm_l0[i]);
4071 KASSERT(pmap->pm_stats.resident_count == 0,
4072 ("Invalid resident count %jd", pmap->pm_stats.resident_count));
4078 * Insert the given physical page (p) at
4079 * the specified virtual address (v) in the
4080 * target physical map with the protection requested.
4082 * If specified, the page will be wired down, meaning
4083 * that the related pte can not be reclaimed.
4085 * NB: This is the only routine which MAY NOT lazy-evaluate
4086 * or lose information. That is, this routine must actually
4087 * insert this page into the given map NOW.
4090 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4091 u_int flags, int8_t psind)
4093 struct rwlock *lock;
4095 pt_entry_t new_l3, orig_l3;
4096 pt_entry_t *l2, *l3;
4103 KASSERT(ADDR_IS_CANONICAL(va),
4104 ("%s: Address not in canonical form: %lx", __func__, va));
4106 va = trunc_page(va);
4107 if ((m->oflags & VPO_UNMANAGED) == 0)
4108 VM_PAGE_OBJECT_BUSY_ASSERT(m);
4109 pa = VM_PAGE_TO_PHYS(m);
4110 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | L3_PAGE);
4111 new_l3 |= pmap_pte_memattr(pmap, m->md.pv_memattr);
4112 new_l3 |= pmap_pte_prot(pmap, prot);
4114 if ((flags & PMAP_ENTER_WIRED) != 0)
4115 new_l3 |= ATTR_SW_WIRED;
4116 if (pmap->pm_stage == PM_STAGE1) {
4117 if (!ADDR_IS_KERNEL(va))
4118 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4120 new_l3 |= ATTR_S1_UXN;
4121 if (pmap != kernel_pmap)
4122 new_l3 |= ATTR_S1_nG;
4125 * Clear the access flag on executable mappings, this will be
4126 * set later when the page is accessed. The fault handler is
4127 * required to invalidate the I-cache.
4129 * TODO: Switch to the valid flag to allow hardware management
4130 * of the access flag. Much of the pmap code assumes the
4131 * valid flag is set and fails to destroy the old page tables
4132 * correctly if it is clear.
4134 if (prot & VM_PROT_EXECUTE)
4137 if ((m->oflags & VPO_UNMANAGED) == 0) {
4138 new_l3 |= ATTR_SW_MANAGED;
4139 if ((prot & VM_PROT_WRITE) != 0) {
4140 new_l3 |= ATTR_SW_DBM;
4141 if ((flags & VM_PROT_WRITE) == 0) {
4142 if (pmap->pm_stage == PM_STAGE1)
4143 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
4146 ~ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
4151 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
4155 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
4156 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
4157 ("managed largepage va %#lx flags %#x", va, flags));
4161 else /* (psind == 1) */
4163 rv = pmap_enter_largepage(pmap, va, new_l3, flags, psind);
4167 /* Assert the required virtual and physical alignment. */
4168 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
4169 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
4170 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
4177 * In the case that a page table page is not
4178 * resident, we are creating it here.
4181 pde = pmap_pde(pmap, va, &lvl);
4182 if (pde != NULL && lvl == 2) {
4183 l3 = pmap_l2_to_l3(pde, va);
4184 if (!ADDR_IS_KERNEL(va) && mpte == NULL) {
4185 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
4189 } else if (pde != NULL && lvl == 1) {
4190 l2 = pmap_l1_to_l2(pde, va);
4191 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
4192 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
4193 l3 = &l3[pmap_l3_index(va)];
4194 if (!ADDR_IS_KERNEL(va)) {
4195 mpte = PHYS_TO_VM_PAGE(
4196 pmap_load(l2) & ~ATTR_MASK);
4201 /* We need to allocate an L3 table. */
4203 if (!ADDR_IS_KERNEL(va)) {
4204 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4207 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
4208 * to handle the possibility that a superpage mapping for "va"
4209 * was created while we slept.
4211 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
4212 nosleep ? NULL : &lock);
4213 if (mpte == NULL && nosleep) {
4214 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
4215 rv = KERN_RESOURCE_SHORTAGE;
4220 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
4223 orig_l3 = pmap_load(l3);
4224 opa = orig_l3 & ~ATTR_MASK;
4228 * Is the specified virtual address already mapped?
4230 if (pmap_l3_valid(orig_l3)) {
4232 * Only allow adding new entries on stage 2 tables for now.
4233 * This simplifies cache invalidation as we may need to call
4234 * into EL2 to perform such actions.
4236 PMAP_ASSERT_STAGE1(pmap);
4238 * Wiring change, just update stats. We don't worry about
4239 * wiring PT pages as they remain resident as long as there
4240 * are valid mappings in them. Hence, if a user page is wired,
4241 * the PT page will be also.
4243 if ((flags & PMAP_ENTER_WIRED) != 0 &&
4244 (orig_l3 & ATTR_SW_WIRED) == 0)
4245 pmap->pm_stats.wired_count++;
4246 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
4247 (orig_l3 & ATTR_SW_WIRED) != 0)
4248 pmap->pm_stats.wired_count--;
4251 * Remove the extra PT page reference.
4255 KASSERT(mpte->ref_count > 0,
4256 ("pmap_enter: missing reference to page table page,"
4261 * Has the physical page changed?
4265 * No, might be a protection or wiring change.
4267 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
4268 (new_l3 & ATTR_SW_DBM) != 0)
4269 vm_page_aflag_set(m, PGA_WRITEABLE);
4274 * The physical page has changed. Temporarily invalidate
4277 orig_l3 = pmap_load_clear(l3);
4278 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
4279 ("pmap_enter: unexpected pa update for %#lx", va));
4280 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
4281 om = PHYS_TO_VM_PAGE(opa);
4284 * The pmap lock is sufficient to synchronize with
4285 * concurrent calls to pmap_page_test_mappings() and
4286 * pmap_ts_referenced().
4288 if (pmap_pte_dirty(pmap, orig_l3))
4290 if ((orig_l3 & ATTR_AF) != 0) {
4291 pmap_invalidate_page(pmap, va, true);
4292 vm_page_aflag_set(om, PGA_REFERENCED);
4294 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4295 pv = pmap_pvh_remove(&om->md, pmap, va);
4296 if ((m->oflags & VPO_UNMANAGED) != 0)
4297 free_pv_entry(pmap, pv);
4298 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
4299 TAILQ_EMPTY(&om->md.pv_list) &&
4300 ((om->flags & PG_FICTITIOUS) != 0 ||
4301 TAILQ_EMPTY(&page_to_pvh(om)->pv_list)))
4302 vm_page_aflag_clear(om, PGA_WRITEABLE);
4304 KASSERT((orig_l3 & ATTR_AF) != 0,
4305 ("pmap_enter: unmanaged mapping lacks ATTR_AF"));
4306 pmap_invalidate_page(pmap, va, true);
4311 * Increment the counters.
4313 if ((new_l3 & ATTR_SW_WIRED) != 0)
4314 pmap->pm_stats.wired_count++;
4315 pmap_resident_count_inc(pmap, 1);
4318 * Enter on the PV list if part of our managed memory.
4320 if ((m->oflags & VPO_UNMANAGED) == 0) {
4322 pv = get_pv_entry(pmap, &lock);
4325 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4326 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4328 if ((new_l3 & ATTR_SW_DBM) != 0)
4329 vm_page_aflag_set(m, PGA_WRITEABLE);
4333 if (pmap->pm_stage == PM_STAGE1) {
4335 * Sync icache if exec permission and attribute
4336 * VM_MEMATTR_WRITE_BACK is set. Do it now, before the mapping
4337 * is stored and made valid for hardware table walk. If done
4338 * later, then other can access this page before caches are
4339 * properly synced. Don't do it for kernel memory which is
4340 * mapped with exec permission even if the memory isn't going
4341 * to hold executable code. The only time when icache sync is
4342 * needed is after kernel module is loaded and the relocation
4343 * info is processed. And it's done in elf_cpu_load_file().
4345 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4346 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
4347 (opa != pa || (orig_l3 & ATTR_S1_XN))) {
4348 PMAP_ASSERT_STAGE1(pmap);
4349 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4352 cpu_dcache_wb_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4356 * Update the L3 entry
4358 if (pmap_l3_valid(orig_l3)) {
4359 PMAP_ASSERT_STAGE1(pmap);
4360 KASSERT(opa == pa, ("pmap_enter: invalid update"));
4361 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
4362 /* same PA, different attributes */
4363 orig_l3 = pmap_load_store(l3, new_l3);
4364 pmap_invalidate_page(pmap, va, true);
4365 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
4366 pmap_pte_dirty(pmap, orig_l3))
4371 * This can happens if multiple threads simultaneously
4372 * access not yet mapped page. This bad for performance
4373 * since this can cause full demotion-NOP-promotion
4375 * Another possible reasons are:
4376 * - VM and pmap memory layout are diverged
4377 * - tlb flush is missing somewhere and CPU doesn't see
4380 CTR4(KTR_PMAP, "%s: already mapped page - "
4381 "pmap %p va 0x%#lx pte 0x%lx",
4382 __func__, pmap, va, new_l3);
4386 pmap_store(l3, new_l3);
4390 #if VM_NRESERVLEVEL > 0
4392 * Try to promote from level 3 pages to a level 2 superpage. This
4393 * currently only works on stage 1 pmaps as pmap_promote_l2 looks at
4394 * stage 1 specific fields and performs a break-before-make sequence
4395 * that is incorrect a stage 2 pmap.
4397 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
4398 pmap_ps_enabled(pmap) && pmap->pm_stage == PM_STAGE1 &&
4399 (m->flags & PG_FICTITIOUS) == 0 &&
4400 vm_reserv_level_iffullpop(m) == 0) {
4401 pmap_promote_l2(pmap, pde, va, &lock);
4414 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
4415 * if successful. Returns false if (1) a page table page cannot be allocated
4416 * without sleeping, (2) a mapping already exists at the specified virtual
4417 * address, or (3) a PV entry cannot be allocated without reclaiming another
4421 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4422 struct rwlock **lockp)
4426 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4427 PMAP_ASSERT_STAGE1(pmap);
4428 KASSERT(ADDR_IS_CANONICAL(va),
4429 ("%s: Address not in canonical form: %lx", __func__, va));
4431 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
4432 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) |
4434 if ((m->oflags & VPO_UNMANAGED) == 0) {
4435 new_l2 |= ATTR_SW_MANAGED;
4438 if ((prot & VM_PROT_EXECUTE) == 0 ||
4439 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4440 new_l2 |= ATTR_S1_XN;
4441 if (!ADDR_IS_KERNEL(va))
4442 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4444 new_l2 |= ATTR_S1_UXN;
4445 if (pmap != kernel_pmap)
4446 new_l2 |= ATTR_S1_nG;
4447 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
4448 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, m, lockp) ==
4453 * Returns true if every page table entry in the specified page table is
4457 pmap_every_pte_zero(vm_paddr_t pa)
4459 pt_entry_t *pt_end, *pte;
4461 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
4462 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
4463 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
4471 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
4472 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
4473 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
4474 * a mapping already exists at the specified virtual address. Returns
4475 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
4476 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
4477 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
4480 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
4481 vm_page_t m, struct rwlock **lockp)
4483 struct spglist free;
4484 pd_entry_t *l2, old_l2;
4487 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4488 KASSERT(ADDR_IS_CANONICAL(va),
4489 ("%s: Address not in canonical form: %lx", __func__, va));
4491 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags &
4492 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
4493 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
4495 return (KERN_RESOURCE_SHORTAGE);
4499 * If there are existing mappings, either abort or remove them.
4501 if ((old_l2 = pmap_load(l2)) != 0) {
4502 KASSERT(l2pg == NULL || l2pg->ref_count > 1,
4503 ("pmap_enter_l2: l2pg's ref count is too low"));
4504 if ((flags & PMAP_ENTER_NOREPLACE) != 0 &&
4505 (!ADDR_IS_KERNEL(va) ||
4506 (old_l2 & ATTR_DESCR_MASK) == L2_BLOCK ||
4507 !pmap_every_pte_zero(old_l2 & ~ATTR_MASK))) {
4510 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx"
4511 " in pmap %p", va, pmap);
4512 return (KERN_FAILURE);
4515 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
4516 (void)pmap_remove_l2(pmap, l2, va,
4517 pmap_load(pmap_l1(pmap, va)), &free, lockp);
4519 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
4521 if (!ADDR_IS_KERNEL(va)) {
4522 vm_page_free_pages_toq(&free, true);
4523 KASSERT(pmap_load(l2) == 0,
4524 ("pmap_enter_l2: non-zero L2 entry %p", l2));
4526 KASSERT(SLIST_EMPTY(&free),
4527 ("pmap_enter_l2: freed kernel page table page"));
4530 * Both pmap_remove_l2() and pmap_remove_l3_range()
4531 * will leave the kernel page table page zero filled.
4532 * Nonetheless, the TLB could have an intermediate
4533 * entry for the kernel page table page, so request
4534 * an invalidation at all levels after clearing
4535 * the L2_TABLE entry.
4537 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
4538 if (pmap_insert_pt_page(pmap, mt, false))
4539 panic("pmap_enter_l2: trie insert failed");
4541 pmap_invalidate_page(pmap, va, false);
4545 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
4547 * Abort this mapping if its PV entry could not be created.
4549 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
4551 pmap_abort_ptp(pmap, va, l2pg);
4553 "pmap_enter_l2: failure for va %#lx in pmap %p",
4555 return (KERN_RESOURCE_SHORTAGE);
4557 if ((new_l2 & ATTR_SW_DBM) != 0)
4558 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4559 vm_page_aflag_set(mt, PGA_WRITEABLE);
4563 * Increment counters.
4565 if ((new_l2 & ATTR_SW_WIRED) != 0)
4566 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
4567 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
4570 * Conditionally sync the icache. See pmap_enter() for details.
4572 if ((new_l2 & ATTR_S1_XN) == 0 && ((new_l2 & ~ATTR_MASK) !=
4573 (old_l2 & ~ATTR_MASK) || (old_l2 & ATTR_S1_XN) != 0) &&
4574 pmap != kernel_pmap && m->md.pv_memattr == VM_MEMATTR_WRITE_BACK) {
4575 cpu_icache_sync_range(PHYS_TO_DMAP(new_l2 & ~ATTR_MASK),
4580 * Map the superpage.
4582 pmap_store(l2, new_l2);
4585 atomic_add_long(&pmap_l2_mappings, 1);
4586 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
4589 return (KERN_SUCCESS);
4593 * Maps a sequence of resident pages belonging to the same object.
4594 * The sequence begins with the given page m_start. This page is
4595 * mapped at the given virtual address start. Each subsequent page is
4596 * mapped at a virtual address that is offset from start by the same
4597 * amount as the page is offset from m_start within the object. The
4598 * last page in the sequence is the page with the largest offset from
4599 * m_start that can be mapped at a virtual address less than the given
4600 * virtual address end. Not every virtual page between start and end
4601 * is mapped; only those for which a resident page exists with the
4602 * corresponding offset from m_start are mapped.
4605 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4606 vm_page_t m_start, vm_prot_t prot)
4608 struct rwlock *lock;
4611 vm_pindex_t diff, psize;
4613 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4615 psize = atop(end - start);
4620 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4621 va = start + ptoa(diff);
4622 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
4623 m->psind == 1 && pmap_ps_enabled(pmap) &&
4624 pmap_enter_2mpage(pmap, va, m, prot, &lock))
4625 m = &m[L2_SIZE / PAGE_SIZE - 1];
4627 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
4629 m = TAILQ_NEXT(m, listq);
4637 * this code makes some *MAJOR* assumptions:
4638 * 1. Current pmap & pmap exists.
4641 * 4. No page table pages.
4642 * but is *MUCH* faster than pmap_enter...
4646 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4648 struct rwlock *lock;
4652 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4659 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4660 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4663 pt_entry_t *l2, *l3, l3_val;
4667 KASSERT(!VA_IS_CLEANMAP(va) ||
4668 (m->oflags & VPO_UNMANAGED) != 0,
4669 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4670 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4671 PMAP_ASSERT_STAGE1(pmap);
4672 KASSERT(ADDR_IS_CANONICAL(va),
4673 ("%s: Address not in canonical form: %lx", __func__, va));
4675 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
4677 * In the case that a page table page is not
4678 * resident, we are creating it here.
4680 if (!ADDR_IS_KERNEL(va)) {
4681 vm_pindex_t l2pindex;
4684 * Calculate pagetable page index
4686 l2pindex = pmap_l2_pindex(va);
4687 if (mpte && (mpte->pindex == l2pindex)) {
4693 pde = pmap_pde(pmap, va, &lvl);
4696 * If the page table page is mapped, we just increment
4697 * the hold count, and activate it. Otherwise, we
4698 * attempt to allocate a page table page. If this
4699 * attempt fails, we don't retry. Instead, we give up.
4702 l2 = pmap_l1_to_l2(pde, va);
4703 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
4707 if (lvl == 2 && pmap_load(pde) != 0) {
4709 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
4713 * Pass NULL instead of the PV list lock
4714 * pointer, because we don't intend to sleep.
4716 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
4721 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4722 l3 = &l3[pmap_l3_index(va)];
4725 pde = pmap_pde(kernel_pmap, va, &lvl);
4726 KASSERT(pde != NULL,
4727 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
4730 ("pmap_enter_quick_locked: Invalid level %d", lvl));
4731 l3 = pmap_l2_to_l3(pde, va);
4735 * Abort if a mapping already exists.
4737 if (pmap_load(l3) != 0) {
4744 * Enter on the PV list if part of our managed memory.
4746 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4747 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4749 pmap_abort_ptp(pmap, va, mpte);
4754 * Increment counters
4756 pmap_resident_count_inc(pmap, 1);
4758 pa = VM_PAGE_TO_PHYS(m);
4759 l3_val = pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
4760 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE;
4761 if ((prot & VM_PROT_EXECUTE) == 0 ||
4762 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4763 l3_val |= ATTR_S1_XN;
4764 if (!ADDR_IS_KERNEL(va))
4765 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4767 l3_val |= ATTR_S1_UXN;
4768 if (pmap != kernel_pmap)
4769 l3_val |= ATTR_S1_nG;
4772 * Now validate mapping with RO protection
4774 if ((m->oflags & VPO_UNMANAGED) == 0) {
4775 l3_val |= ATTR_SW_MANAGED;
4779 /* Sync icache before the mapping is stored to PTE */
4780 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4781 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
4782 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4784 pmap_store(l3, l3_val);
4791 * This code maps large physical mmap regions into the
4792 * processor address space. Note that some shortcuts
4793 * are taken, but the code works.
4796 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4797 vm_pindex_t pindex, vm_size_t size)
4800 VM_OBJECT_ASSERT_WLOCKED(object);
4801 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4802 ("pmap_object_init_pt: non-device object"));
4806 * Clear the wired attribute from the mappings for the specified range of
4807 * addresses in the given pmap. Every valid mapping within that range
4808 * must have the wired attribute set. In contrast, invalid mappings
4809 * cannot have the wired attribute set, so they are ignored.
4811 * The wired attribute of the page table entry is not a hardware feature,
4812 * so there is no need to invalidate any TLB entries.
4815 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4817 vm_offset_t va_next;
4818 pd_entry_t *l0, *l1, *l2;
4822 for (; sva < eva; sva = va_next) {
4823 l0 = pmap_l0(pmap, sva);
4824 if (pmap_load(l0) == 0) {
4825 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4831 l1 = pmap_l0_to_l1(l0, sva);
4832 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4835 if (pmap_load(l1) == 0)
4838 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
4839 KASSERT(va_next <= eva,
4840 ("partial update of non-transparent 1G page "
4841 "l1 %#lx sva %#lx eva %#lx va_next %#lx",
4842 pmap_load(l1), sva, eva, va_next));
4843 MPASS(pmap != kernel_pmap);
4844 MPASS((pmap_load(l1) & (ATTR_SW_MANAGED |
4845 ATTR_SW_WIRED)) == ATTR_SW_WIRED);
4846 pmap_clear_bits(l1, ATTR_SW_WIRED);
4847 pmap->pm_stats.wired_count -= L1_SIZE / PAGE_SIZE;
4851 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4855 l2 = pmap_l1_to_l2(l1, sva);
4856 if (pmap_load(l2) == 0)
4859 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
4860 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
4861 panic("pmap_unwire: l2 %#jx is missing "
4862 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
4865 * Are we unwiring the entire large page? If not,
4866 * demote the mapping and fall through.
4868 if (sva + L2_SIZE == va_next && eva >= va_next) {
4869 pmap_clear_bits(l2, ATTR_SW_WIRED);
4870 pmap->pm_stats.wired_count -= L2_SIZE /
4873 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
4874 panic("pmap_unwire: demotion failed");
4876 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4877 ("pmap_unwire: Invalid l2 entry after demotion"));
4881 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4883 if (pmap_load(l3) == 0)
4885 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
4886 panic("pmap_unwire: l3 %#jx is missing "
4887 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
4890 * ATTR_SW_WIRED must be cleared atomically. Although
4891 * the pmap lock synchronizes access to ATTR_SW_WIRED,
4892 * the System MMU may write to the entry concurrently.
4894 pmap_clear_bits(l3, ATTR_SW_WIRED);
4895 pmap->pm_stats.wired_count--;
4902 * Copy the range specified by src_addr/len
4903 * from the source map to the range dst_addr/len
4904 * in the destination map.
4906 * This routine is only advisory and need not do anything.
4908 * Because the executable mappings created by this routine are copied,
4909 * it should not have to flush the instruction cache.
4912 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4913 vm_offset_t src_addr)
4915 struct rwlock *lock;
4916 pd_entry_t *l0, *l1, *l2, srcptepaddr;
4917 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
4918 vm_offset_t addr, end_addr, va_next;
4919 vm_page_t dst_m, dstmpte, srcmpte;
4921 PMAP_ASSERT_STAGE1(dst_pmap);
4922 PMAP_ASSERT_STAGE1(src_pmap);
4924 if (dst_addr != src_addr)
4926 end_addr = src_addr + len;
4928 if (dst_pmap < src_pmap) {
4929 PMAP_LOCK(dst_pmap);
4930 PMAP_LOCK(src_pmap);
4932 PMAP_LOCK(src_pmap);
4933 PMAP_LOCK(dst_pmap);
4935 for (addr = src_addr; addr < end_addr; addr = va_next) {
4936 l0 = pmap_l0(src_pmap, addr);
4937 if (pmap_load(l0) == 0) {
4938 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
4944 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
4947 l1 = pmap_l0_to_l1(l0, addr);
4948 if (pmap_load(l1) == 0)
4950 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) {
4951 KASSERT(va_next <= end_addr,
4952 ("partial update of non-transparent 1G page "
4953 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
4954 pmap_load(l1), addr, end_addr, va_next));
4955 srcptepaddr = pmap_load(l1);
4956 l1 = pmap_l1(dst_pmap, addr);
4958 if (_pmap_alloc_l3(dst_pmap,
4959 pmap_l0_pindex(addr), NULL) == NULL)
4961 l1 = pmap_l1(dst_pmap, addr);
4963 l0 = pmap_l0(dst_pmap, addr);
4964 dst_m = PHYS_TO_VM_PAGE(pmap_load(l0) &
4968 KASSERT(pmap_load(l1) == 0,
4969 ("1G mapping present in dst pmap "
4970 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx",
4971 pmap_load(l1), addr, end_addr, va_next));
4972 pmap_store(l1, srcptepaddr & ~ATTR_SW_WIRED);
4973 pmap_resident_count_inc(dst_pmap, L1_SIZE / PAGE_SIZE);
4977 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
4980 l2 = pmap_l1_to_l2(l1, addr);
4981 srcptepaddr = pmap_load(l2);
4982 if (srcptepaddr == 0)
4984 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
4986 * We can only virtual copy whole superpages.
4988 if ((addr & L2_OFFSET) != 0 ||
4989 addr + L2_SIZE > end_addr)
4991 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_m, NULL);
4994 if (pmap_load(l2) == 0 &&
4995 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
4996 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
4997 PMAP_ENTER_NORECLAIM, &lock))) {
4999 * We leave the dirty bit unchanged because
5000 * managed read/write superpage mappings are
5001 * required to be dirty. However, managed
5002 * superpage mappings are not required to
5003 * have their accessed bit set, so we clear
5004 * it because we don't know if this mapping
5007 srcptepaddr &= ~ATTR_SW_WIRED;
5008 if ((srcptepaddr & ATTR_SW_MANAGED) != 0)
5009 srcptepaddr &= ~ATTR_AF;
5010 pmap_store(l2, srcptepaddr);
5011 pmap_resident_count_inc(dst_pmap, L2_SIZE /
5013 atomic_add_long(&pmap_l2_mappings, 1);
5015 pmap_abort_ptp(dst_pmap, addr, dst_m);
5018 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
5019 ("pmap_copy: invalid L2 entry"));
5020 srcptepaddr &= ~ATTR_MASK;
5021 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
5022 KASSERT(srcmpte->ref_count > 0,
5023 ("pmap_copy: source page table page is unused"));
5024 if (va_next > end_addr)
5026 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
5027 src_pte = &src_pte[pmap_l3_index(addr)];
5029 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
5030 ptetemp = pmap_load(src_pte);
5033 * We only virtual copy managed pages.
5035 if ((ptetemp & ATTR_SW_MANAGED) == 0)
5038 if (dstmpte != NULL) {
5039 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
5040 ("dstmpte pindex/addr mismatch"));
5041 dstmpte->ref_count++;
5042 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
5045 dst_pte = (pt_entry_t *)
5046 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
5047 dst_pte = &dst_pte[pmap_l3_index(addr)];
5048 if (pmap_load(dst_pte) == 0 &&
5049 pmap_try_insert_pv_entry(dst_pmap, addr,
5050 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
5052 * Clear the wired, modified, and accessed
5053 * (referenced) bits during the copy.
5055 mask = ATTR_AF | ATTR_SW_WIRED;
5057 if ((ptetemp & ATTR_SW_DBM) != 0)
5058 nbits |= ATTR_S1_AP_RW_BIT;
5059 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
5060 pmap_resident_count_inc(dst_pmap, 1);
5062 pmap_abort_ptp(dst_pmap, addr, dstmpte);
5065 /* Have we copied all of the valid mappings? */
5066 if (dstmpte->ref_count >= srcmpte->ref_count)
5072 * XXX This barrier may not be needed because the destination pmap is
5079 PMAP_UNLOCK(src_pmap);
5080 PMAP_UNLOCK(dst_pmap);
5084 * pmap_zero_page zeros the specified hardware page by mapping
5085 * the page into KVM and using bzero to clear its contents.
5088 pmap_zero_page(vm_page_t m)
5090 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5092 pagezero((void *)va);
5096 * pmap_zero_page_area zeros the specified hardware page by mapping
5097 * the page into KVM and using bzero to clear its contents.
5099 * off and size may not cover an area beyond a single hardware page.
5102 pmap_zero_page_area(vm_page_t m, int off, int size)
5104 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5106 if (off == 0 && size == PAGE_SIZE)
5107 pagezero((void *)va);
5109 bzero((char *)va + off, size);
5113 * pmap_copy_page copies the specified (machine independent)
5114 * page by mapping the page into virtual memory and using
5115 * bcopy to copy the page, one machine dependent page at a
5119 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5121 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5122 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5124 pagecopy((void *)src, (void *)dst);
5127 int unmapped_buf_allowed = 1;
5130 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5131 vm_offset_t b_offset, int xfersize)
5135 vm_paddr_t p_a, p_b;
5136 vm_offset_t a_pg_offset, b_pg_offset;
5139 while (xfersize > 0) {
5140 a_pg_offset = a_offset & PAGE_MASK;
5141 m_a = ma[a_offset >> PAGE_SHIFT];
5142 p_a = m_a->phys_addr;
5143 b_pg_offset = b_offset & PAGE_MASK;
5144 m_b = mb[b_offset >> PAGE_SHIFT];
5145 p_b = m_b->phys_addr;
5146 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5147 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5148 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
5149 panic("!DMAP a %lx", p_a);
5151 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
5153 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
5154 panic("!DMAP b %lx", p_b);
5156 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
5158 bcopy(a_cp, b_cp, cnt);
5166 pmap_quick_enter_page(vm_page_t m)
5169 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
5173 pmap_quick_remove_page(vm_offset_t addr)
5178 * Returns true if the pmap's pv is one of the first
5179 * 16 pvs linked to from this page. This count may
5180 * be changed upwards or downwards in the future; it
5181 * is only necessary that true be returned for a small
5182 * subset of pmaps for proper page aging.
5185 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5187 struct md_page *pvh;
5188 struct rwlock *lock;
5193 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5194 ("pmap_page_exists_quick: page %p is not managed", m));
5196 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5198 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5199 if (PV_PMAP(pv) == pmap) {
5207 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5208 pvh = page_to_pvh(m);
5209 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5210 if (PV_PMAP(pv) == pmap) {
5224 * pmap_page_wired_mappings:
5226 * Return the number of managed mappings to the given physical page
5230 pmap_page_wired_mappings(vm_page_t m)
5232 struct rwlock *lock;
5233 struct md_page *pvh;
5237 int count, lvl, md_gen, pvh_gen;
5239 if ((m->oflags & VPO_UNMANAGED) != 0)
5241 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5245 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5247 if (!PMAP_TRYLOCK(pmap)) {
5248 md_gen = m->md.pv_gen;
5252 if (md_gen != m->md.pv_gen) {
5257 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5258 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
5262 if ((m->flags & PG_FICTITIOUS) == 0) {
5263 pvh = page_to_pvh(m);
5264 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5266 if (!PMAP_TRYLOCK(pmap)) {
5267 md_gen = m->md.pv_gen;
5268 pvh_gen = pvh->pv_gen;
5272 if (md_gen != m->md.pv_gen ||
5273 pvh_gen != pvh->pv_gen) {
5278 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5280 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
5290 * Returns true if the given page is mapped individually or as part of
5291 * a 2mpage. Otherwise, returns false.
5294 pmap_page_is_mapped(vm_page_t m)
5296 struct rwlock *lock;
5299 if ((m->oflags & VPO_UNMANAGED) != 0)
5301 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5303 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5304 ((m->flags & PG_FICTITIOUS) == 0 &&
5305 !TAILQ_EMPTY(&page_to_pvh(m)->pv_list));
5311 * Destroy all managed, non-wired mappings in the given user-space
5312 * pmap. This pmap cannot be active on any processor besides the
5315 * This function cannot be applied to the kernel pmap. Moreover, it
5316 * is not intended for general use. It is only to be used during
5317 * process termination. Consequently, it can be implemented in ways
5318 * that make it faster than pmap_remove(). First, it can more quickly
5319 * destroy mappings by iterating over the pmap's collection of PV
5320 * entries, rather than searching the page table. Second, it doesn't
5321 * have to test and clear the page table entries atomically, because
5322 * no processor is currently accessing the user address space. In
5323 * particular, a page table entry's dirty bit won't change state once
5324 * this function starts.
5327 pmap_remove_pages(pmap_t pmap)
5330 pt_entry_t *pte, tpte;
5331 struct spglist free;
5332 vm_page_t m, ml3, mt;
5334 struct md_page *pvh;
5335 struct pv_chunk *pc, *npc;
5336 struct rwlock *lock;
5338 uint64_t inuse, bitmask;
5339 int allfree, field, freed, idx, lvl;
5346 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5349 for (field = 0; field < _NPCM; field++) {
5350 inuse = ~pc->pc_map[field] & pc_freemask[field];
5351 while (inuse != 0) {
5352 bit = ffsl(inuse) - 1;
5353 bitmask = 1UL << bit;
5354 idx = field * 64 + bit;
5355 pv = &pc->pc_pventry[idx];
5358 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5359 KASSERT(pde != NULL,
5360 ("Attempting to remove an unmapped page"));
5364 pte = pmap_l1_to_l2(pde, pv->pv_va);
5365 tpte = pmap_load(pte);
5366 KASSERT((tpte & ATTR_DESCR_MASK) ==
5368 ("Attempting to remove an invalid "
5369 "block: %lx", tpte));
5372 pte = pmap_l2_to_l3(pde, pv->pv_va);
5373 tpte = pmap_load(pte);
5374 KASSERT((tpte & ATTR_DESCR_MASK) ==
5376 ("Attempting to remove an invalid "
5377 "page: %lx", tpte));
5381 "Invalid page directory level: %d",
5386 * We cannot remove wired pages from a process' mapping at this time
5388 if (tpte & ATTR_SW_WIRED) {
5394 pc->pc_map[field] |= bitmask;
5397 * Because this pmap is not active on other
5398 * processors, the dirty bit cannot have
5399 * changed state since we last loaded pte.
5403 pa = tpte & ~ATTR_MASK;
5405 m = PHYS_TO_VM_PAGE(pa);
5406 KASSERT(m->phys_addr == pa,
5407 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5408 m, (uintmax_t)m->phys_addr,
5411 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5412 m < &vm_page_array[vm_page_array_size],
5413 ("pmap_remove_pages: bad pte %#jx",
5417 * Update the vm_page_t clean/reference bits.
5419 if (pmap_pte_dirty(pmap, tpte)) {
5422 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
5431 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5435 pmap_resident_count_dec(pmap,
5436 L2_SIZE / PAGE_SIZE);
5437 pvh = page_to_pvh(m);
5438 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
5440 if (TAILQ_EMPTY(&pvh->pv_list)) {
5441 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
5442 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
5443 TAILQ_EMPTY(&mt->md.pv_list))
5444 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5446 ml3 = pmap_remove_pt_page(pmap,
5449 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
5450 ("pmap_remove_pages: l3 page not promoted"));
5451 pmap_resident_count_dec(pmap,1);
5452 KASSERT(ml3->ref_count == NL3PG,
5453 ("pmap_remove_pages: l3 page ref count error"));
5455 pmap_add_delayed_free_list(ml3,
5460 pmap_resident_count_dec(pmap, 1);
5461 TAILQ_REMOVE(&m->md.pv_list, pv,
5464 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
5465 TAILQ_EMPTY(&m->md.pv_list) &&
5466 (m->flags & PG_FICTITIOUS) == 0) {
5467 pvh = page_to_pvh(m);
5468 if (TAILQ_EMPTY(&pvh->pv_list))
5469 vm_page_aflag_clear(m,
5474 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
5479 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5480 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5481 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5483 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5489 pmap_invalidate_all(pmap);
5491 vm_page_free_pages_toq(&free, true);
5495 * This is used to check if a page has been accessed or modified.
5498 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5500 struct rwlock *lock;
5502 struct md_page *pvh;
5503 pt_entry_t *pte, mask, value;
5505 int lvl, md_gen, pvh_gen;
5509 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5512 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5514 PMAP_ASSERT_STAGE1(pmap);
5515 if (!PMAP_TRYLOCK(pmap)) {
5516 md_gen = m->md.pv_gen;
5520 if (md_gen != m->md.pv_gen) {
5525 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5527 ("pmap_page_test_mappings: Invalid level %d", lvl));
5531 mask |= ATTR_S1_AP_RW_BIT;
5532 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5535 mask |= ATTR_AF | ATTR_DESCR_MASK;
5536 value |= ATTR_AF | L3_PAGE;
5538 rv = (pmap_load(pte) & mask) == value;
5543 if ((m->flags & PG_FICTITIOUS) == 0) {
5544 pvh = page_to_pvh(m);
5545 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5547 PMAP_ASSERT_STAGE1(pmap);
5548 if (!PMAP_TRYLOCK(pmap)) {
5549 md_gen = m->md.pv_gen;
5550 pvh_gen = pvh->pv_gen;
5554 if (md_gen != m->md.pv_gen ||
5555 pvh_gen != pvh->pv_gen) {
5560 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5562 ("pmap_page_test_mappings: Invalid level %d", lvl));
5566 mask |= ATTR_S1_AP_RW_BIT;
5567 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
5570 mask |= ATTR_AF | ATTR_DESCR_MASK;
5571 value |= ATTR_AF | L2_BLOCK;
5573 rv = (pmap_load(pte) & mask) == value;
5587 * Return whether or not the specified physical page was modified
5588 * in any physical maps.
5591 pmap_is_modified(vm_page_t m)
5594 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5595 ("pmap_is_modified: page %p is not managed", m));
5598 * If the page is not busied then this check is racy.
5600 if (!pmap_page_is_write_mapped(m))
5602 return (pmap_page_test_mappings(m, FALSE, TRUE));
5606 * pmap_is_prefaultable:
5608 * Return whether or not the specified virtual address is eligible
5612 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5620 pte = pmap_pte(pmap, addr, &lvl);
5621 if (pte != NULL && pmap_load(pte) != 0) {
5629 * pmap_is_referenced:
5631 * Return whether or not the specified physical page was referenced
5632 * in any physical maps.
5635 pmap_is_referenced(vm_page_t m)
5638 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5639 ("pmap_is_referenced: page %p is not managed", m));
5640 return (pmap_page_test_mappings(m, TRUE, FALSE));
5644 * Clear the write and modified bits in each of the given page's mappings.
5647 pmap_remove_write(vm_page_t m)
5649 struct md_page *pvh;
5651 struct rwlock *lock;
5652 pv_entry_t next_pv, pv;
5653 pt_entry_t oldpte, *pte;
5655 int lvl, md_gen, pvh_gen;
5657 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5658 ("pmap_remove_write: page %p is not managed", m));
5659 vm_page_assert_busied(m);
5661 if (!pmap_page_is_write_mapped(m))
5663 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5664 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5667 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5669 PMAP_ASSERT_STAGE1(pmap);
5670 if (!PMAP_TRYLOCK(pmap)) {
5671 pvh_gen = pvh->pv_gen;
5675 if (pvh_gen != pvh->pv_gen) {
5681 pte = pmap_pte(pmap, va, &lvl);
5682 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
5683 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
5684 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5685 ("inconsistent pv lock %p %p for page %p",
5686 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5689 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5691 PMAP_ASSERT_STAGE1(pmap);
5692 if (!PMAP_TRYLOCK(pmap)) {
5693 pvh_gen = pvh->pv_gen;
5694 md_gen = m->md.pv_gen;
5698 if (pvh_gen != pvh->pv_gen ||
5699 md_gen != m->md.pv_gen) {
5704 pte = pmap_pte(pmap, pv->pv_va, &lvl);
5705 oldpte = pmap_load(pte);
5706 if ((oldpte & ATTR_SW_DBM) != 0) {
5707 while (!atomic_fcmpset_64(pte, &oldpte,
5708 (oldpte | ATTR_S1_AP_RW_BIT) & ~ATTR_SW_DBM))
5710 if ((oldpte & ATTR_S1_AP_RW_BIT) ==
5711 ATTR_S1_AP(ATTR_S1_AP_RW))
5713 pmap_invalidate_page(pmap, pv->pv_va, true);
5718 vm_page_aflag_clear(m, PGA_WRITEABLE);
5722 * pmap_ts_referenced:
5724 * Return a count of reference bits for a page, clearing those bits.
5725 * It is not necessary for every reference bit to be cleared, but it
5726 * is necessary that 0 only be returned when there are truly no
5727 * reference bits set.
5729 * As an optimization, update the page's dirty field if a modified bit is
5730 * found while counting reference bits. This opportunistic update can be
5731 * performed at low cost and can eliminate the need for some future calls
5732 * to pmap_is_modified(). However, since this function stops after
5733 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5734 * dirty pages. Those dirty pages will only be detected by a future call
5735 * to pmap_is_modified().
5738 pmap_ts_referenced(vm_page_t m)
5740 struct md_page *pvh;
5743 struct rwlock *lock;
5744 pd_entry_t *pde, tpde;
5745 pt_entry_t *pte, tpte;
5748 int cleared, lvl, md_gen, not_cleared, pvh_gen;
5749 struct spglist free;
5751 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5752 ("pmap_ts_referenced: page %p is not managed", m));
5755 pa = VM_PAGE_TO_PHYS(m);
5756 lock = PHYS_TO_PV_LIST_LOCK(pa);
5757 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
5761 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5762 goto small_mappings;
5768 if (!PMAP_TRYLOCK(pmap)) {
5769 pvh_gen = pvh->pv_gen;
5773 if (pvh_gen != pvh->pv_gen) {
5779 pde = pmap_pde(pmap, va, &lvl);
5780 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
5782 ("pmap_ts_referenced: invalid pde level %d", lvl));
5783 tpde = pmap_load(pde);
5784 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
5785 ("pmap_ts_referenced: found an invalid l1 table"));
5786 pte = pmap_l1_to_l2(pde, va);
5787 tpte = pmap_load(pte);
5788 if (pmap_pte_dirty(pmap, tpte)) {
5790 * Although "tpte" is mapping a 2MB page, because
5791 * this function is called at a 4KB page granularity,
5792 * we only update the 4KB page under test.
5797 if ((tpte & ATTR_AF) != 0) {
5799 * Since this reference bit is shared by 512 4KB pages,
5800 * it should not be cleared every time it is tested.
5801 * Apply a simple "hash" function on the physical page
5802 * number, the virtual superpage number, and the pmap
5803 * address to select one 4KB page out of the 512 on
5804 * which testing the reference bit will result in
5805 * clearing that reference bit. This function is
5806 * designed to avoid the selection of the same 4KB page
5807 * for every 2MB page mapping.
5809 * On demotion, a mapping that hasn't been referenced
5810 * is simply destroyed. To avoid the possibility of a
5811 * subsequent page fault on a demoted wired mapping,
5812 * always leave its reference bit set. Moreover,
5813 * since the superpage is wired, the current state of
5814 * its reference bit won't affect page replacement.
5816 if ((((pa >> PAGE_SHIFT) ^ (va >> L2_SHIFT) ^
5817 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
5818 (tpte & ATTR_SW_WIRED) == 0) {
5819 pmap_clear_bits(pte, ATTR_AF);
5820 pmap_invalidate_page(pmap, va, true);
5826 /* Rotate the PV list if it has more than one entry. */
5827 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5828 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5829 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5832 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5834 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5836 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5843 if (!PMAP_TRYLOCK(pmap)) {
5844 pvh_gen = pvh->pv_gen;
5845 md_gen = m->md.pv_gen;
5849 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5854 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5855 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
5857 ("pmap_ts_referenced: invalid pde level %d", lvl));
5858 tpde = pmap_load(pde);
5859 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
5860 ("pmap_ts_referenced: found an invalid l2 table"));
5861 pte = pmap_l2_to_l3(pde, pv->pv_va);
5862 tpte = pmap_load(pte);
5863 if (pmap_pte_dirty(pmap, tpte))
5865 if ((tpte & ATTR_AF) != 0) {
5866 if ((tpte & ATTR_SW_WIRED) == 0) {
5867 pmap_clear_bits(pte, ATTR_AF);
5868 pmap_invalidate_page(pmap, pv->pv_va, true);
5874 /* Rotate the PV list if it has more than one entry. */
5875 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5876 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5877 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5880 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5881 not_cleared < PMAP_TS_REFERENCED_MAX);
5884 vm_page_free_pages_toq(&free, true);
5885 return (cleared + not_cleared);
5889 * Apply the given advice to the specified range of addresses within the
5890 * given pmap. Depending on the advice, clear the referenced and/or
5891 * modified flags in each mapping and set the mapped page's dirty field.
5894 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5896 struct rwlock *lock;
5897 vm_offset_t va, va_next;
5899 pd_entry_t *l0, *l1, *l2, oldl2;
5900 pt_entry_t *l3, oldl3;
5902 PMAP_ASSERT_STAGE1(pmap);
5904 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5908 for (; sva < eva; sva = va_next) {
5909 l0 = pmap_l0(pmap, sva);
5910 if (pmap_load(l0) == 0) {
5911 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
5917 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
5920 l1 = pmap_l0_to_l1(l0, sva);
5921 if (pmap_load(l1) == 0)
5923 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK)
5926 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
5929 l2 = pmap_l1_to_l2(l1, sva);
5930 oldl2 = pmap_load(l2);
5933 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
5934 if ((oldl2 & ATTR_SW_MANAGED) == 0)
5937 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
5942 * The 2MB page mapping was destroyed.
5948 * Unless the page mappings are wired, remove the
5949 * mapping to a single page so that a subsequent
5950 * access may repromote. Choosing the last page
5951 * within the address range [sva, min(va_next, eva))
5952 * generally results in more repromotions. Since the
5953 * underlying page table page is fully populated, this
5954 * removal never frees a page table page.
5956 if ((oldl2 & ATTR_SW_WIRED) == 0) {
5962 ("pmap_advise: no address gap"));
5963 l3 = pmap_l2_to_l3(l2, va);
5964 KASSERT(pmap_load(l3) != 0,
5965 ("pmap_advise: invalid PTE"));
5966 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
5972 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5973 ("pmap_advise: invalid L2 entry after demotion"));
5977 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5979 oldl3 = pmap_load(l3);
5980 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
5981 (ATTR_SW_MANAGED | L3_PAGE))
5983 else if (pmap_pte_dirty(pmap, oldl3)) {
5984 if (advice == MADV_DONTNEED) {
5986 * Future calls to pmap_is_modified()
5987 * can be avoided by making the page
5990 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
5993 while (!atomic_fcmpset_long(l3, &oldl3,
5994 (oldl3 & ~ATTR_AF) |
5995 ATTR_S1_AP(ATTR_S1_AP_RO)))
5997 } else if ((oldl3 & ATTR_AF) != 0)
5998 pmap_clear_bits(l3, ATTR_AF);
6005 if (va != va_next) {
6006 pmap_invalidate_range(pmap, va, sva, true);
6011 pmap_invalidate_range(pmap, va, sva, true);
6017 * Clear the modify bits on the specified physical page.
6020 pmap_clear_modify(vm_page_t m)
6022 struct md_page *pvh;
6023 struct rwlock *lock;
6025 pv_entry_t next_pv, pv;
6026 pd_entry_t *l2, oldl2;
6027 pt_entry_t *l3, oldl3;
6029 int md_gen, pvh_gen;
6031 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6032 ("pmap_clear_modify: page %p is not managed", m));
6033 vm_page_assert_busied(m);
6035 if (!pmap_page_is_write_mapped(m))
6037 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m);
6038 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6041 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6043 PMAP_ASSERT_STAGE1(pmap);
6044 if (!PMAP_TRYLOCK(pmap)) {
6045 pvh_gen = pvh->pv_gen;
6049 if (pvh_gen != pvh->pv_gen) {
6055 l2 = pmap_l2(pmap, va);
6056 oldl2 = pmap_load(l2);
6057 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
6058 if ((oldl2 & ATTR_SW_DBM) != 0 &&
6059 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
6060 (oldl2 & ATTR_SW_WIRED) == 0) {
6062 * Write protect the mapping to a single page so that
6063 * a subsequent write access may repromote.
6065 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
6066 l3 = pmap_l2_to_l3(l2, va);
6067 oldl3 = pmap_load(l3);
6068 while (!atomic_fcmpset_long(l3, &oldl3,
6069 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO)))
6072 pmap_invalidate_page(pmap, va, true);
6076 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6078 PMAP_ASSERT_STAGE1(pmap);
6079 if (!PMAP_TRYLOCK(pmap)) {
6080 md_gen = m->md.pv_gen;
6081 pvh_gen = pvh->pv_gen;
6085 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6090 l2 = pmap_l2(pmap, pv->pv_va);
6091 l3 = pmap_l2_to_l3(l2, pv->pv_va);
6092 oldl3 = pmap_load(l3);
6093 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){
6094 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO));
6095 pmap_invalidate_page(pmap, pv->pv_va, true);
6103 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6105 struct pmap_preinit_mapping *ppim;
6106 vm_offset_t va, offset;
6109 int i, lvl, l2_blocks, free_l2_count, start_idx;
6111 if (!vm_initialized) {
6113 * No L3 ptables so map entire L2 blocks where start VA is:
6114 * preinit_map_va + start_idx * L2_SIZE
6115 * There may be duplicate mappings (multiple VA -> same PA) but
6116 * ARM64 dcache is always PIPT so that's acceptable.
6121 /* Calculate how many L2 blocks are needed for the mapping */
6122 l2_blocks = (roundup2(pa + size, L2_SIZE) -
6123 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
6125 offset = pa & L2_OFFSET;
6127 if (preinit_map_va == 0)
6130 /* Map 2MiB L2 blocks from reserved VA space */
6134 /* Find enough free contiguous VA space */
6135 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6136 ppim = pmap_preinit_mapping + i;
6137 if (free_l2_count > 0 && ppim->pa != 0) {
6138 /* Not enough space here */
6144 if (ppim->pa == 0) {
6146 if (start_idx == -1)
6149 if (free_l2_count == l2_blocks)
6153 if (free_l2_count != l2_blocks)
6154 panic("%s: too many preinit mappings", __func__);
6156 va = preinit_map_va + (start_idx * L2_SIZE);
6157 for (i = start_idx; i < start_idx + l2_blocks; i++) {
6158 /* Mark entries as allocated */
6159 ppim = pmap_preinit_mapping + i;
6161 ppim->va = va + offset;
6166 pa = rounddown2(pa, L2_SIZE);
6167 for (i = 0; i < l2_blocks; i++) {
6168 pde = pmap_pde(kernel_pmap, va, &lvl);
6169 KASSERT(pde != NULL,
6170 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
6173 ("pmap_mapbios: Invalid level %d", lvl));
6175 /* Insert L2_BLOCK */
6176 l2 = pmap_l1_to_l2(pde, va);
6178 pa | ATTR_DEFAULT | ATTR_S1_XN |
6179 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
6184 pmap_invalidate_all(kernel_pmap);
6186 va = preinit_map_va + (start_idx * L2_SIZE);
6189 /* kva_alloc may be used to map the pages */
6190 offset = pa & PAGE_MASK;
6191 size = round_page(offset + size);
6193 va = kva_alloc(size);
6195 panic("%s: Couldn't allocate KVA", __func__);
6197 pde = pmap_pde(kernel_pmap, va, &lvl);
6198 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
6200 /* L3 table is linked */
6201 va = trunc_page(va);
6202 pa = trunc_page(pa);
6203 pmap_kenter(va, size, pa, memory_mapping_mode(pa));
6206 return ((void *)(va + offset));
6210 pmap_unmapbios(vm_offset_t va, vm_size_t size)
6212 struct pmap_preinit_mapping *ppim;
6213 vm_offset_t offset, tmpsize, va_trunc;
6216 int i, lvl, l2_blocks, block;
6220 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
6221 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
6223 /* Remove preinit mapping */
6224 preinit_map = false;
6226 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6227 ppim = pmap_preinit_mapping + i;
6228 if (ppim->va == va) {
6229 KASSERT(ppim->size == size,
6230 ("pmap_unmapbios: size mismatch"));
6235 offset = block * L2_SIZE;
6236 va_trunc = rounddown2(va, L2_SIZE) + offset;
6238 /* Remove L2_BLOCK */
6239 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
6240 KASSERT(pde != NULL,
6241 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
6243 l2 = pmap_l1_to_l2(pde, va_trunc);
6246 if (block == (l2_blocks - 1))
6252 pmap_invalidate_all(kernel_pmap);
6256 /* Unmap the pages reserved with kva_alloc. */
6257 if (vm_initialized) {
6258 offset = va & PAGE_MASK;
6259 size = round_page(offset + size);
6260 va = trunc_page(va);
6262 pde = pmap_pde(kernel_pmap, va, &lvl);
6263 KASSERT(pde != NULL,
6264 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
6265 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
6267 /* Unmap and invalidate the pages */
6268 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6269 pmap_kremove(va + tmpsize);
6276 * Sets the memory attribute for the specified page.
6279 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6282 m->md.pv_memattr = ma;
6285 * If "m" is a normal page, update its direct mapping. This update
6286 * can be relied upon to perform any cache operations that are
6287 * required for data coherence.
6289 if ((m->flags & PG_FICTITIOUS) == 0 &&
6290 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6291 m->md.pv_memattr) != 0)
6292 panic("memory attribute change on the direct map failed");
6296 * Changes the specified virtual address range's memory type to that given by
6297 * the parameter "mode". The specified virtual address range must be
6298 * completely contained within either the direct map or the kernel map. If
6299 * the virtual address range is contained within the kernel map, then the
6300 * memory type for each of the corresponding ranges of the direct map is also
6301 * changed. (The corresponding ranges of the direct map are those ranges that
6302 * map the same physical pages as the specified virtual address range.) These
6303 * changes to the direct map are necessary because Intel describes the
6304 * behavior of their processors as "undefined" if two or more mappings to the
6305 * same physical page have different memory types.
6307 * Returns zero if the change completed successfully, and either EINVAL or
6308 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6309 * of the virtual address range was not mapped, and ENOMEM is returned if
6310 * there was insufficient memory available to complete the change. In the
6311 * latter case, the memory type may have been changed on some part of the
6312 * virtual address range or the direct map.
6315 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6319 PMAP_LOCK(kernel_pmap);
6320 error = pmap_change_props_locked(va, size, PROT_NONE, mode, false);
6321 PMAP_UNLOCK(kernel_pmap);
6326 * Changes the specified virtual address range's protections to those
6327 * specified by "prot". Like pmap_change_attr(), protections for aliases
6328 * in the direct map are updated as well. Protections on aliasing mappings may
6329 * be a subset of the requested protections; for example, mappings in the direct
6330 * map are never executable.
6333 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
6337 /* Only supported within the kernel map. */
6338 if (va < VM_MIN_KERNEL_ADDRESS)
6341 PMAP_LOCK(kernel_pmap);
6342 error = pmap_change_props_locked(va, size, prot, -1, false);
6343 PMAP_UNLOCK(kernel_pmap);
6348 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
6349 int mode, bool skip_unmapped)
6351 vm_offset_t base, offset, tmpva;
6354 pt_entry_t pte, *ptep, *newpte;
6355 pt_entry_t bits, mask;
6358 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6359 base = trunc_page(va);
6360 offset = va & PAGE_MASK;
6361 size = round_page(offset + size);
6363 if (!VIRT_IN_DMAP(base) &&
6364 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
6370 bits = ATTR_S1_IDX(mode);
6371 mask = ATTR_S1_IDX_MASK;
6372 if (mode == VM_MEMATTR_DEVICE) {
6377 if (prot != VM_PROT_NONE) {
6378 /* Don't mark the DMAP as executable. It never is on arm64. */
6379 if (VIRT_IN_DMAP(base)) {
6380 prot &= ~VM_PROT_EXECUTE;
6382 * XXX Mark the DMAP as writable for now. We rely
6383 * on this in ddb & dtrace to insert breakpoint
6386 prot |= VM_PROT_WRITE;
6389 if ((prot & VM_PROT_WRITE) == 0) {
6390 bits |= ATTR_S1_AP(ATTR_S1_AP_RO);
6392 if ((prot & VM_PROT_EXECUTE) == 0) {
6393 bits |= ATTR_S1_PXN;
6395 bits |= ATTR_S1_UXN;
6396 mask |= ATTR_S1_AP_MASK | ATTR_S1_XN;
6399 for (tmpva = base; tmpva < base + size; ) {
6400 ptep = pmap_pte(kernel_pmap, tmpva, &lvl);
6401 if (ptep == NULL && !skip_unmapped) {
6403 } else if ((ptep == NULL && skip_unmapped) ||
6404 (pmap_load(ptep) & mask) == bits) {
6406 * We already have the correct attribute or there
6407 * is no memory mapped at this address and we are
6408 * skipping unmapped memory.
6412 panic("Invalid DMAP table level: %d\n", lvl);
6414 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
6417 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
6424 /* We can't demote/promote this entry */
6425 MPASS((pmap_load(ptep) & ATTR_SW_NO_PROMOTE) == 0);
6428 * Split the entry to an level 3 table, then
6429 * set the new attribute.
6433 panic("Invalid DMAP table level: %d\n", lvl);
6435 if ((tmpva & L1_OFFSET) == 0 &&
6436 (base + size - tmpva) >= L1_SIZE) {
6440 newpte = pmap_demote_l1(kernel_pmap, ptep,
6441 tmpva & ~L1_OFFSET);
6444 ptep = pmap_l1_to_l2(ptep, tmpva);
6447 if ((tmpva & L2_OFFSET) == 0 &&
6448 (base + size - tmpva) >= L2_SIZE) {
6452 newpte = pmap_demote_l2(kernel_pmap, ptep,
6456 ptep = pmap_l2_to_l3(ptep, tmpva);
6459 pte_size = PAGE_SIZE;
6463 /* Update the entry */
6464 pte = pmap_load(ptep);
6468 pmap_update_entry(kernel_pmap, ptep, pte, tmpva,
6471 pa = pte & ~ATTR_MASK;
6472 if (!VIRT_IN_DMAP(tmpva) && PHYS_IN_DMAP(pa)) {
6474 * Keep the DMAP memory in sync.
6476 rv = pmap_change_props_locked(
6477 PHYS_TO_DMAP(pa), pte_size,
6484 * If moving to a non-cacheable entry flush
6487 if (mode == VM_MEMATTR_UNCACHEABLE)
6488 cpu_dcache_wbinv_range(tmpva, pte_size);
6497 * Create an L2 table to map all addresses within an L1 mapping.
6500 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
6502 pt_entry_t *l2, newl2, oldl1;
6504 vm_paddr_t l2phys, phys;
6508 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6509 oldl1 = pmap_load(l1);
6510 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
6511 ("pmap_demote_l1: Demoting a non-block entry"));
6512 KASSERT((va & L1_OFFSET) == 0,
6513 ("pmap_demote_l1: Invalid virtual address %#lx", va));
6514 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
6515 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
6516 KASSERT((oldl1 & ATTR_SW_NO_PROMOTE) == 0,
6517 ("pmap_demote_l1: Demoting entry with no-demote flag set"));
6520 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
6521 tmpl1 = kva_alloc(PAGE_SIZE);
6526 if ((ml2 = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED)) ==
6528 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
6529 " in pmap %p", va, pmap);
6534 l2phys = VM_PAGE_TO_PHYS(ml2);
6535 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
6537 /* Address the range points at */
6538 phys = oldl1 & ~ATTR_MASK;
6539 /* The attributed from the old l1 table to be copied */
6540 newl2 = oldl1 & ATTR_MASK;
6542 /* Create the new entries */
6543 for (i = 0; i < Ln_ENTRIES; i++) {
6544 l2[i] = newl2 | phys;
6547 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
6548 ("Invalid l2 page (%lx != %lx)", l2[0],
6549 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
6552 pmap_kenter(tmpl1, PAGE_SIZE,
6553 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
6554 VM_MEMATTR_WRITE_BACK);
6555 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
6558 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
6562 pmap_kremove(tmpl1);
6563 kva_free(tmpl1, PAGE_SIZE);
6570 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
6574 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
6581 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
6582 struct rwlock **lockp)
6584 struct spglist free;
6587 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
6589 vm_page_free_pages_toq(&free, true);
6593 * Create an L3 table to map all addresses within an L2 mapping.
6596 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
6597 struct rwlock **lockp)
6599 pt_entry_t *l3, newl3, oldl2;
6604 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6605 PMAP_ASSERT_STAGE1(pmap);
6606 KASSERT(ADDR_IS_CANONICAL(va),
6607 ("%s: Address not in canonical form: %lx", __func__, va));
6610 oldl2 = pmap_load(l2);
6611 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
6612 ("pmap_demote_l2: Demoting a non-block entry"));
6613 KASSERT((oldl2 & ATTR_SW_NO_PROMOTE) == 0,
6614 ("pmap_demote_l2: Demoting entry with no-demote flag set"));
6618 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
6619 tmpl2 = kva_alloc(PAGE_SIZE);
6625 * Invalidate the 2MB page mapping and return "failure" if the
6626 * mapping was never accessed.
6628 if ((oldl2 & ATTR_AF) == 0) {
6629 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
6630 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
6631 pmap_demote_l2_abort(pmap, va, l2, lockp);
6632 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
6637 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
6638 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
6639 ("pmap_demote_l2: page table page for a wired mapping"
6643 * If the page table page is missing and the mapping
6644 * is for a kernel address, the mapping must belong to
6645 * either the direct map or the early kernel memory.
6646 * Page table pages are preallocated for every other
6647 * part of the kernel address space, so the direct map
6648 * region and early kernel memory are the only parts of the
6649 * kernel address space that must be handled here.
6651 KASSERT(!ADDR_IS_KERNEL(va) || VIRT_IN_DMAP(va) ||
6652 (va >= VM_MIN_KERNEL_ADDRESS && va < kernel_vm_end),
6653 ("pmap_demote_l2: No saved mpte for va %#lx", va));
6656 * If the 2MB page mapping belongs to the direct map
6657 * region of the kernel's address space, then the page
6658 * allocation request specifies the highest possible
6659 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
6660 * priority is normal.
6662 ml3 = vm_page_alloc_noobj(
6663 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : 0) |
6667 * If the allocation of the new page table page fails,
6668 * invalidate the 2MB page mapping and return "failure".
6671 pmap_demote_l2_abort(pmap, va, l2, lockp);
6672 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
6673 " in pmap %p", va, pmap);
6676 ml3->pindex = pmap_l2_pindex(va);
6678 if (!ADDR_IS_KERNEL(va)) {
6679 ml3->ref_count = NL3PG;
6680 pmap_resident_count_inc(pmap, 1);
6683 l3phys = VM_PAGE_TO_PHYS(ml3);
6684 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
6685 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
6686 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) !=
6687 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM),
6688 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
6691 * If the page table page is not leftover from an earlier promotion,
6692 * or the mapping attributes have changed, (re)initialize the L3 table.
6694 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
6695 * performs a dsb(). That dsb() ensures that the stores for filling
6696 * "l3" are visible before "l3" is added to the page table.
6698 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
6699 pmap_fill_l3(l3, newl3);
6702 * Map the temporary page so we don't lose access to the l2 table.
6705 pmap_kenter(tmpl2, PAGE_SIZE,
6706 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
6707 VM_MEMATTR_WRITE_BACK);
6708 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
6712 * The spare PV entries must be reserved prior to demoting the
6713 * mapping, that is, prior to changing the PDE. Otherwise, the state
6714 * of the L2 and the PV lists will be inconsistent, which can result
6715 * in reclaim_pv_chunk() attempting to remove a PV entry from the
6716 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
6717 * PV entry for the 2MB page mapping that is being demoted.
6719 if ((oldl2 & ATTR_SW_MANAGED) != 0)
6720 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
6723 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
6724 * the 2MB page mapping.
6726 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
6729 * Demote the PV entry.
6731 if ((oldl2 & ATTR_SW_MANAGED) != 0)
6732 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
6734 atomic_add_long(&pmap_l2_demotions, 1);
6735 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
6736 " in pmap %p %lx", va, pmap, l3[0]);
6740 pmap_kremove(tmpl2);
6741 kva_free(tmpl2, PAGE_SIZE);
6749 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
6751 struct rwlock *lock;
6755 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
6762 * Perform the pmap work for mincore(2). If the page is not both referenced and
6763 * modified by this pmap, returns its physical address so that the caller can
6764 * find other mappings.
6767 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
6769 pt_entry_t *pte, tpte;
6770 vm_paddr_t mask, pa;
6774 PMAP_ASSERT_STAGE1(pmap);
6776 pte = pmap_pte(pmap, addr, &lvl);
6778 tpte = pmap_load(pte);
6791 panic("pmap_mincore: invalid level %d", lvl);
6794 managed = (tpte & ATTR_SW_MANAGED) != 0;
6795 val = MINCORE_INCORE;
6797 val |= MINCORE_PSIND(3 - lvl);
6798 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed &&
6799 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)))
6800 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6801 if ((tpte & ATTR_AF) == ATTR_AF)
6802 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6804 pa = (tpte & ~ATTR_MASK) | (addr & mask);
6810 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6811 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6819 * Garbage collect every ASID that is neither active on a processor nor
6823 pmap_reset_asid_set(pmap_t pmap)
6826 int asid, cpuid, epoch;
6827 struct asid_set *set;
6828 enum pmap_stage stage;
6830 set = pmap->pm_asid_set;
6831 stage = pmap->pm_stage;
6833 set = pmap->pm_asid_set;
6834 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6835 mtx_assert(&set->asid_set_mutex, MA_OWNED);
6838 * Ensure that the store to asid_epoch is globally visible before the
6839 * loads from pc_curpmap are performed.
6841 epoch = set->asid_epoch + 1;
6842 if (epoch == INT_MAX)
6844 set->asid_epoch = epoch;
6846 if (stage == PM_STAGE1) {
6847 __asm __volatile("tlbi vmalle1is");
6849 KASSERT(pmap_clean_stage2_tlbi != NULL,
6850 ("%s: Unset stage 2 tlb invalidation callback\n",
6852 pmap_clean_stage2_tlbi();
6855 bit_nclear(set->asid_set, ASID_FIRST_AVAILABLE,
6856 set->asid_set_size - 1);
6857 CPU_FOREACH(cpuid) {
6858 if (cpuid == curcpu)
6860 if (stage == PM_STAGE1) {
6861 curpmap = pcpu_find(cpuid)->pc_curpmap;
6862 PMAP_ASSERT_STAGE1(pmap);
6864 curpmap = pcpu_find(cpuid)->pc_curvmpmap;
6865 if (curpmap == NULL)
6867 PMAP_ASSERT_STAGE2(pmap);
6869 KASSERT(curpmap->pm_asid_set == set, ("Incorrect set"));
6870 asid = COOKIE_TO_ASID(curpmap->pm_cookie);
6873 bit_set(set->asid_set, asid);
6874 curpmap->pm_cookie = COOKIE_FROM(asid, epoch);
6879 * Allocate a new ASID for the specified pmap.
6882 pmap_alloc_asid(pmap_t pmap)
6884 struct asid_set *set;
6887 set = pmap->pm_asid_set;
6888 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6890 mtx_lock_spin(&set->asid_set_mutex);
6893 * While this processor was waiting to acquire the asid set mutex,
6894 * pmap_reset_asid_set() running on another processor might have
6895 * updated this pmap's cookie to the current epoch. In which case, we
6896 * don't need to allocate a new ASID.
6898 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch)
6901 bit_ffc_at(set->asid_set, set->asid_next, set->asid_set_size,
6903 if (new_asid == -1) {
6904 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6905 set->asid_next, &new_asid);
6906 if (new_asid == -1) {
6907 pmap_reset_asid_set(pmap);
6908 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6909 set->asid_set_size, &new_asid);
6910 KASSERT(new_asid != -1, ("ASID allocation failure"));
6913 bit_set(set->asid_set, new_asid);
6914 set->asid_next = new_asid + 1;
6915 pmap->pm_cookie = COOKIE_FROM(new_asid, set->asid_epoch);
6917 mtx_unlock_spin(&set->asid_set_mutex);
6920 static uint64_t __read_mostly ttbr_flags;
6923 * Compute the value that should be stored in ttbr0 to activate the specified
6924 * pmap. This value may change from time to time.
6927 pmap_to_ttbr0(pmap_t pmap)
6931 ttbr = pmap->pm_ttbr;
6932 ttbr |= ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
6939 pmap_set_cnp(void *arg)
6941 uint64_t ttbr0, ttbr1;
6944 cpuid = *(u_int *)arg;
6945 if (cpuid == curcpu) {
6947 * Set the flags while all CPUs are handling the
6948 * smp_rendezvous so will not call pmap_to_ttbr0. Any calls
6949 * to pmap_to_ttbr0 after this will have the CnP flag set.
6950 * The dsb after invalidating the TLB will act as a barrier
6951 * to ensure all CPUs can observe this change.
6953 ttbr_flags |= TTBR_CnP;
6956 ttbr0 = READ_SPECIALREG(ttbr0_el1);
6959 ttbr1 = READ_SPECIALREG(ttbr1_el1);
6962 /* Update ttbr{0,1}_el1 with the CnP flag */
6963 WRITE_SPECIALREG(ttbr0_el1, ttbr0);
6964 WRITE_SPECIALREG(ttbr1_el1, ttbr1);
6966 __asm __volatile("tlbi vmalle1is");
6972 * Defer enabling CnP until we have read the ID registers to know if it's
6973 * supported on all CPUs.
6976 pmap_init_cnp(void *dummy __unused)
6981 if (!get_kernel_reg(ID_AA64MMFR2_EL1, ®))
6984 if (ID_AA64MMFR2_CnP_VAL(reg) != ID_AA64MMFR2_CnP_NONE) {
6986 printf("Enabling CnP\n");
6988 smp_rendezvous(NULL, pmap_set_cnp, NULL, &cpuid);
6992 SYSINIT(pmap_init_cnp, SI_SUB_SMP, SI_ORDER_ANY, pmap_init_cnp, NULL);
6995 pmap_activate_int(pmap_t pmap)
6997 struct asid_set *set;
7000 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
7001 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
7003 if ((pmap->pm_stage == PM_STAGE1 && pmap == PCPU_GET(curpmap)) ||
7004 (pmap->pm_stage == PM_STAGE2 && pmap == PCPU_GET(curvmpmap))) {
7006 * Handle the possibility that the old thread was preempted
7007 * after an "ic" or "tlbi" instruction but before it performed
7008 * a "dsb" instruction. If the old thread migrates to a new
7009 * processor, its completion of a "dsb" instruction on that
7010 * new processor does not guarantee that the "ic" or "tlbi"
7011 * instructions performed on the old processor have completed.
7017 set = pmap->pm_asid_set;
7018 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
7021 * Ensure that the store to curpmap is globally visible before the
7022 * load from asid_epoch is performed.
7024 if (pmap->pm_stage == PM_STAGE1)
7025 PCPU_SET(curpmap, pmap);
7027 PCPU_SET(curvmpmap, pmap);
7029 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
7030 if (epoch >= 0 && epoch != set->asid_epoch)
7031 pmap_alloc_asid(pmap);
7033 if (pmap->pm_stage == PM_STAGE1) {
7034 set_ttbr0(pmap_to_ttbr0(pmap));
7035 if (PCPU_GET(bcast_tlbi_workaround) != 0)
7036 invalidate_local_icache();
7042 pmap_activate_vm(pmap_t pmap)
7045 PMAP_ASSERT_STAGE2(pmap);
7047 (void)pmap_activate_int(pmap);
7051 pmap_activate(struct thread *td)
7055 pmap = vmspace_pmap(td->td_proc->p_vmspace);
7056 PMAP_ASSERT_STAGE1(pmap);
7058 (void)pmap_activate_int(pmap);
7063 * To eliminate the unused parameter "old", we would have to add an instruction
7067 pmap_switch(struct thread *old __unused, struct thread *new)
7069 pcpu_bp_harden bp_harden;
7072 /* Store the new curthread */
7073 PCPU_SET(curthread, new);
7074 #if defined(PERTHREAD_SSP)
7075 /* Set the new threads SSP canary */
7076 __asm("msr sp_el0, %0" :: "r"(&new->td_md.md_canary));
7079 /* And the new pcb */
7081 PCPU_SET(curpcb, pcb);
7084 * TODO: We may need to flush the cache here if switching
7085 * to a user process.
7088 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
7090 * Stop userspace from training the branch predictor against
7091 * other processes. This will call into a CPU specific
7092 * function that clears the branch predictor state.
7094 bp_harden = PCPU_GET(bp_harden);
7095 if (bp_harden != NULL)
7103 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
7106 PMAP_ASSERT_STAGE1(pmap);
7107 KASSERT(ADDR_IS_CANONICAL(va),
7108 ("%s: Address not in canonical form: %lx", __func__, va));
7110 if (ADDR_IS_KERNEL(va)) {
7111 cpu_icache_sync_range(va, sz);
7116 /* Find the length of data in this page to flush */
7117 offset = va & PAGE_MASK;
7118 len = imin(PAGE_SIZE - offset, sz);
7121 /* Extract the physical address & find it in the DMAP */
7122 pa = pmap_extract(pmap, va);
7124 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
7126 /* Move to the next page */
7129 /* Set the length for the next iteration */
7130 len = imin(PAGE_SIZE, sz);
7136 pmap_stage2_fault(pmap_t pmap, uint64_t esr, uint64_t far)
7139 pt_entry_t *ptep, pte;
7142 PMAP_ASSERT_STAGE2(pmap);
7145 /* Data and insn aborts use same encoding for FSC field. */
7146 dfsc = esr & ISS_DATA_DFSC_MASK;
7148 case ISS_DATA_DFSC_TF_L0:
7149 case ISS_DATA_DFSC_TF_L1:
7150 case ISS_DATA_DFSC_TF_L2:
7151 case ISS_DATA_DFSC_TF_L3:
7153 pdep = pmap_pde(pmap, far, &lvl);
7154 if (pdep == NULL || lvl != (dfsc - ISS_DATA_DFSC_TF_L1)) {
7161 ptep = pmap_l0_to_l1(pdep, far);
7164 ptep = pmap_l1_to_l2(pdep, far);
7167 ptep = pmap_l2_to_l3(pdep, far);
7170 panic("%s: Invalid pde level %d", __func__,lvl);
7174 case ISS_DATA_DFSC_AFF_L1:
7175 case ISS_DATA_DFSC_AFF_L2:
7176 case ISS_DATA_DFSC_AFF_L3:
7178 ptep = pmap_pte(pmap, far, &lvl);
7180 if (ptep != NULL && (pte = pmap_load(ptep)) != 0) {
7182 pmap_invalidate_vpipt_icache();
7185 * If accessing an executable page invalidate
7186 * the I-cache so it will be valid when we
7187 * continue execution in the guest. The D-cache
7188 * is assumed to already be clean to the Point
7191 if ((pte & ATTR_S2_XN_MASK) !=
7192 ATTR_S2_XN(ATTR_S2_XN_NONE)) {
7193 invalidate_icache();
7196 pmap_set_bits(ptep, ATTR_AF | ATTR_DESCR_VALID);
7207 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
7209 pt_entry_t pte, *ptep;
7216 ec = ESR_ELx_EXCEPTION(esr);
7218 case EXCP_INSN_ABORT_L:
7219 case EXCP_INSN_ABORT:
7220 case EXCP_DATA_ABORT_L:
7221 case EXCP_DATA_ABORT:
7227 if (pmap->pm_stage == PM_STAGE2)
7228 return (pmap_stage2_fault(pmap, esr, far));
7230 /* Data and insn aborts use same encoding for FSC field. */
7231 switch (esr & ISS_DATA_DFSC_MASK) {
7232 case ISS_DATA_DFSC_AFF_L1:
7233 case ISS_DATA_DFSC_AFF_L2:
7234 case ISS_DATA_DFSC_AFF_L3:
7236 ptep = pmap_pte(pmap, far, &lvl);
7238 pmap_set_bits(ptep, ATTR_AF);
7241 * XXXMJ as an optimization we could mark the entry
7242 * dirty if this is a write fault.
7247 case ISS_DATA_DFSC_PF_L1:
7248 case ISS_DATA_DFSC_PF_L2:
7249 case ISS_DATA_DFSC_PF_L3:
7250 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
7251 (esr & ISS_DATA_WnR) == 0)
7254 ptep = pmap_pte(pmap, far, &lvl);
7256 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
7257 if ((pte & ATTR_S1_AP_RW_BIT) ==
7258 ATTR_S1_AP(ATTR_S1_AP_RO)) {
7259 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT);
7260 pmap_invalidate_page(pmap, far, true);
7266 case ISS_DATA_DFSC_TF_L0:
7267 case ISS_DATA_DFSC_TF_L1:
7268 case ISS_DATA_DFSC_TF_L2:
7269 case ISS_DATA_DFSC_TF_L3:
7271 * Retry the translation. A break-before-make sequence can
7272 * produce a transient fault.
7274 if (pmap == kernel_pmap) {
7276 * The translation fault may have occurred within a
7277 * critical section. Therefore, we must check the
7278 * address without acquiring the kernel pmap's lock.
7280 if (pmap_klookup(far, NULL))
7284 /* Ask the MMU to check the address. */
7285 intr = intr_disable();
7286 par = arm64_address_translate_s1e0r(far);
7291 * If the translation was successful, then we can
7292 * return success to the trap handler.
7294 if (PAR_SUCCESS(par))
7304 * Increase the starting virtual address of the given mapping if a
7305 * different alignment might result in more superpage mappings.
7308 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
7309 vm_offset_t *addr, vm_size_t size)
7311 vm_offset_t superpage_offset;
7315 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
7316 offset += ptoa(object->pg_color);
7317 superpage_offset = offset & L2_OFFSET;
7318 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
7319 (*addr & L2_OFFSET) == superpage_offset)
7321 if ((*addr & L2_OFFSET) < superpage_offset)
7322 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
7324 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
7328 * Get the kernel virtual address of a set of physical pages. If there are
7329 * physical addresses not covered by the DMAP perform a transient mapping
7330 * that will be removed when calling pmap_unmap_io_transient.
7332 * \param page The pages the caller wishes to obtain the virtual
7333 * address on the kernel memory map.
7334 * \param vaddr On return contains the kernel virtual memory address
7335 * of the pages passed in the page parameter.
7336 * \param count Number of pages passed in.
7337 * \param can_fault TRUE if the thread using the mapped pages can take
7338 * page faults, FALSE otherwise.
7340 * \returns TRUE if the caller must call pmap_unmap_io_transient when
7341 * finished or FALSE otherwise.
7345 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7346 boolean_t can_fault)
7349 boolean_t needs_mapping;
7353 * Allocate any KVA space that we need, this is done in a separate
7354 * loop to prevent calling vmem_alloc while pinned.
7356 needs_mapping = FALSE;
7357 for (i = 0; i < count; i++) {
7358 paddr = VM_PAGE_TO_PHYS(page[i]);
7359 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
7360 error = vmem_alloc(kernel_arena, PAGE_SIZE,
7361 M_BESTFIT | M_WAITOK, &vaddr[i]);
7362 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
7363 needs_mapping = TRUE;
7365 vaddr[i] = PHYS_TO_DMAP(paddr);
7369 /* Exit early if everything is covered by the DMAP */
7375 for (i = 0; i < count; i++) {
7376 paddr = VM_PAGE_TO_PHYS(page[i]);
7377 if (!PHYS_IN_DMAP(paddr)) {
7379 "pmap_map_io_transient: TODO: Map out of DMAP data");
7383 return (needs_mapping);
7387 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7388 boolean_t can_fault)
7395 for (i = 0; i < count; i++) {
7396 paddr = VM_PAGE_TO_PHYS(page[i]);
7397 if (!PHYS_IN_DMAP(paddr)) {
7398 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
7404 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
7407 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
7411 * Track a range of the kernel's virtual address space that is contiguous
7412 * in various mapping attributes.
7414 struct pmap_kernel_map_range {
7424 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
7430 if (eva <= range->sva)
7433 index = range->attrs & ATTR_S1_IDX_MASK;
7435 case ATTR_S1_IDX(VM_MEMATTR_DEVICE):
7438 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE):
7441 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK):
7444 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH):
7449 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
7450 __func__, index, range->sva, eva);
7455 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %3s %d %d %d %d\n",
7457 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-',
7458 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x',
7459 (range->attrs & ATTR_S1_UXN) != 0 ? '-' : 'X',
7460 (range->attrs & ATTR_S1_AP(ATTR_S1_AP_USER)) != 0 ? 'u' : 's',
7461 mode, range->l1blocks, range->l2blocks, range->l3contig,
7464 /* Reset to sentinel value. */
7465 range->sva = 0xfffffffffffffffful;
7469 * Determine whether the attributes specified by a page table entry match those
7470 * being tracked by the current range.
7473 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
7476 return (range->attrs == attrs);
7480 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
7484 memset(range, 0, sizeof(*range));
7486 range->attrs = attrs;
7489 /* Get the block/page attributes that correspond to the table attributes */
7491 sysctl_kmaps_table_attrs(pd_entry_t table)
7496 if ((table & TATTR_UXN_TABLE) != 0)
7497 attrs |= ATTR_S1_UXN;
7498 if ((table & TATTR_PXN_TABLE) != 0)
7499 attrs |= ATTR_S1_PXN;
7500 if ((table & TATTR_AP_TABLE_RO) != 0)
7501 attrs |= ATTR_S1_AP(ATTR_S1_AP_RO);
7506 /* Read the block/page attributes we care about */
7508 sysctl_kmaps_block_attrs(pt_entry_t block)
7510 return (block & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK));
7514 * Given a leaf PTE, derive the mapping's attributes. If they do not match
7515 * those of the current run, dump the address range and its attributes, and
7519 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
7520 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
7525 attrs = sysctl_kmaps_table_attrs(l0e);
7527 if ((l1e & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
7528 attrs |= sysctl_kmaps_block_attrs(l1e);
7531 attrs |= sysctl_kmaps_table_attrs(l1e);
7533 if ((l2e & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) {
7534 attrs |= sysctl_kmaps_block_attrs(l2e);
7537 attrs |= sysctl_kmaps_table_attrs(l2e);
7538 attrs |= sysctl_kmaps_block_attrs(l3e);
7541 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
7542 sysctl_kmaps_dump(sb, range, va);
7543 sysctl_kmaps_reinit(range, va, attrs);
7548 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
7550 struct pmap_kernel_map_range range;
7551 struct sbuf sbuf, *sb;
7552 pd_entry_t l0e, *l1, l1e, *l2, l2e;
7553 pt_entry_t *l3, l3e;
7556 int error, i, j, k, l;
7558 error = sysctl_wire_old_buffer(req, 0);
7562 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
7564 /* Sentinel value. */
7565 range.sva = 0xfffffffffffffffful;
7568 * Iterate over the kernel page tables without holding the kernel pmap
7569 * lock. Kernel page table pages are never freed, so at worst we will
7570 * observe inconsistencies in the output.
7572 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
7574 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
7575 sbuf_printf(sb, "\nDirect map:\n");
7576 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
7577 sbuf_printf(sb, "\nKernel map:\n");
7579 l0e = kernel_pmap->pm_l0[i];
7580 if ((l0e & ATTR_DESCR_VALID) == 0) {
7581 sysctl_kmaps_dump(sb, &range, sva);
7585 pa = l0e & ~ATTR_MASK;
7586 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
7588 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
7590 if ((l1e & ATTR_DESCR_VALID) == 0) {
7591 sysctl_kmaps_dump(sb, &range, sva);
7595 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
7596 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
7602 pa = l1e & ~ATTR_MASK;
7603 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
7605 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
7607 if ((l2e & ATTR_DESCR_VALID) == 0) {
7608 sysctl_kmaps_dump(sb, &range, sva);
7612 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
7613 sysctl_kmaps_check(sb, &range, sva,
7619 pa = l2e & ~ATTR_MASK;
7620 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
7622 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
7623 l++, sva += L3_SIZE) {
7625 if ((l3e & ATTR_DESCR_VALID) == 0) {
7626 sysctl_kmaps_dump(sb, &range,
7630 sysctl_kmaps_check(sb, &range, sva,
7631 l0e, l1e, l2e, l3e);
7632 if ((l3e & ATTR_CONTIGUOUS) != 0)
7633 range.l3contig += l % 16 == 0 ?
7642 error = sbuf_finish(sb);
7646 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
7647 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
7648 NULL, 0, sysctl_kmaps, "A",
7649 "Dump kernel address layout");