2 * Copyright (c) 2017 Andrew Turner
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
37 #include <sys/queue.h>
38 #include <sys/signal.h>
39 #include <sys/signalvar.h>
40 #include <sys/sysctl.h>
41 #include <sys/sysent.h>
43 #include <machine/atomic.h>
44 #include <machine/frame.h>
45 #define _MD_WANT_SWAPWORD
46 #include <machine/md_var.h>
47 #include <machine/pcb.h>
48 #include <machine/undefined.h>
49 #include <machine/vmparam.h>
52 #include <vm/vm_extern.h>
54 /* Low bit masked off */
55 #define INSN_COND(insn) ((insn >> 28) & ~0x1)
56 #define INSN_COND_INVERTED(insn) ((insn >> 28) & 0x1)
57 #define INSN_COND_EQ 0x00 /* NE */
58 #define INSN_COND_CS 0x02 /* CC */
59 #define INSN_COND_MI 0x04 /* PL */
60 #define INSN_COND_VS 0x06 /* VC */
61 #define INSN_COND_HI 0x08 /* LS */
62 #define INSN_COND_GE 0x0a /* LT */
63 #define INSN_COND_GT 0x0c /* LE */
64 #define INSN_COND_AL 0x0e /* Always */
66 MALLOC_DEFINE(M_UNDEF, "undefhandler", "Undefined instruction handler data");
68 #ifdef COMPAT_FREEBSD32
73 SYSCTL_DECL(_compat_arm);
75 static bool compat32_emul_swp = EMUL_SWP;
76 SYSCTL_BOOL(_compat_arm, OID_AUTO, emul_swp,
77 CTLFLAG_RWTUN | CTLFLAG_MPSAFE, &compat32_emul_swp, 0,
78 "Enable SWP/SWPB emulation");
81 struct undef_handler {
82 LIST_ENTRY(undef_handler) uh_link;
83 undef_handler_t uh_handler;
87 * Create two undefined instruction handler lists, one for userspace, one for
88 * the kernel. This allows us to handle instructions that will trap
90 LIST_HEAD(, undef_handler) undef_handlers[2];
93 * Work around a bug in QEMU prior to 2.5.1 where reading unknown ID
94 * registers would raise an exception when they should return 0.
97 id_aa64mmfr2_handler(vm_offset_t va, uint32_t insn, struct trapframe *frame,
102 #define MRS_ID_AA64MMFR2_EL0_MASK (MRS_MASK | 0x000fffe0)
103 #define MRS_ID_AA64MMFR2_EL0_VALUE (MRS_VALUE | 0x00080740)
105 /* mrs xn, id_aa64mfr2_el1 */
106 if ((insn & MRS_ID_AA64MMFR2_EL0_MASK) == MRS_ID_AA64MMFR2_EL0_VALUE) {
107 reg = MRS_REGISTER(insn);
109 frame->tf_elr += INSN_SIZE;
110 if (reg < nitems(frame->tf_x)) {
111 frame->tf_x[reg] = 0;
112 } else if (reg == 30) {
115 /* If reg is 32 then write to xzr, i.e. do nothing */
123 arm_cond_match(uint32_t insn, struct trapframe *frame)
131 * Generally based on the function of the same name in NetBSD, though
132 * condition bits left in their original position rather than shifting
133 * over the low bit that indicates inversion for quicker sanity checking
136 spsr = frame->tf_spsr;
137 cond = INSN_COND(insn);
138 invert = INSN_COND_INVERTED(insn);
142 match = (spsr & PSR_Z) != 0;
145 match = (spsr & PSR_C) != 0;
148 match = (spsr & PSR_N) != 0;
151 match = (spsr & PSR_V) != 0;
154 match = (spsr & (PSR_C | PSR_Z)) == PSR_C;
157 match = (!(spsr & PSR_N) == !(spsr & PSR_V));
160 match = !(spsr & PSR_Z) && (!(spsr & PSR_N) == !(spsr & PSR_V));
166 __assert_unreachable();
169 return (match != invert);
172 #ifdef COMPAT_FREEBSD32
173 /* arm32 GDB breakpoints */
174 #define GDB_BREAKPOINT 0xe6000011
175 #define GDB5_BREAKPOINT 0xe7ffdefe
177 gdb_trapper(vm_offset_t va, uint32_t insn, struct trapframe *frame,
180 struct thread *td = curthread;
182 if (insn == GDB_BREAKPOINT || insn == GDB5_BREAKPOINT) {
183 if (SV_PROC_FLAG(td->td_proc, SV_ILP32) &&
184 va < VM_MAXUSER_ADDRESS) {
187 ksiginfo_init_trap(&ksi);
188 ksi.ksi_signo = SIGTRAP;
189 ksi.ksi_code = TRAP_BRKPT;
190 ksi.ksi_addr = (void *)va;
191 trapsignal(td, &ksi);
199 swp_emulate(vm_offset_t va, uint32_t insn, struct trapframe *frame,
207 int attempts, error, Rn, Rd, Rm;
213 * swp, swpb only; there are no Thumb swp/swpb instructions so we can
214 * safely bail out if we're in Thumb mode.
216 if (!compat32_emul_swp || !SV_PROC_FLAG(td->td_proc, SV_ILP32) ||
217 (frame->tf_spsr & PSR_T) != 0)
219 else if ((insn & 0x0fb00ff0) != 0x01000090)
221 else if (!arm_cond_match(insn, frame))
222 goto next; /* Handled, but does nothing */
224 Rn = (insn & 0xf0000) >> 16;
225 Rd = (insn & 0xf000) >> 12;
229 vaddr = regs[Rn] & 0xffffffff;
232 /* Enforce alignment for swp. */
233 is_swpb = (insn & 0x00400000) != 0;
234 if (!is_swpb && (vaddr & 3) != 0)
244 error = swapueword8((void *)vaddr, &bval);
247 error = swapueword32((void *)vaddr, &val);
254 * Avoid potential DoS, e.g., on CPUs that don't implement
257 if (error != 0 && (++attempts % 5) == 0)
259 } while (error != 0);
264 /* No thumb SWP/SWPB */
265 frame->tf_elr += 4; //INSN_SIZE;
269 ksiginfo_init_trap(&ksi);
270 ksi.ksi_signo = SIGSEGV;
271 ksi.ksi_code = SEGV_MAPERR;
272 ksi.ksi_addr = (void *)va;
273 trapsignal(td, &ksi);
283 LIST_INIT(&undef_handlers[0]);
284 LIST_INIT(&undef_handlers[1]);
286 install_undef_handler(false, id_aa64mmfr2_handler);
287 #ifdef COMPAT_FREEBSD32
288 install_undef_handler(true, gdb_trapper);
289 install_undef_handler(true, swp_emulate);
294 install_undef_handler(bool user, undef_handler_t func)
296 struct undef_handler *uh;
298 uh = malloc(sizeof(*uh), M_UNDEF, M_WAITOK);
299 uh->uh_handler = func;
300 LIST_INSERT_HEAD(&undef_handlers[user ? 0 : 1], uh, uh_link);
306 remove_undef_handler(void *handle)
308 struct undef_handler *uh;
311 LIST_REMOVE(uh, uh_link);
312 free(handle, M_UNDEF);
316 undef_insn(u_int el, struct trapframe *frame)
318 struct undef_handler *uh;
322 KASSERT(el < 2, ("Invalid exception level %u", el));
325 ret = fueword32((uint32_t *)frame->tf_elr, &insn);
327 panic("Unable to read userspace faulting instruction");
329 insn = *(uint32_t *)frame->tf_elr;
332 LIST_FOREACH(uh, &undef_handlers[el], uh_link) {
333 ret = uh->uh_handler(frame->tf_elr, insn, frame, frame->tf_esr);