2 * Copyright (c) 2019 Juniper Networks, Inc.
3 * Copyright (c) 2019 Semihalf.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
36 #include <sys/systm.h>
38 #include <dev/fdt/simplebus.h>
39 #include <dev/ofw/ofw_bus_subr.h>
40 #include <dev/ofw/ofw_bus.h>
42 #include <machine/bus.h>
43 #include <machine/resource.h>
47 #define BLK_ADDR_REG_OFFSET 0x1f
48 #define PLL_AFE1_100MHZ_BLK 0x2100
49 #define PLL_CLK_AMP_OFFSET 0x03
50 #define PLL_CLK_AMP_2P05V 0x2b18
52 struct ns2_pcie_phy_softc {
56 static device_probe_t ns2_pcie_phy_fdt_probe;
57 static device_attach_t ns2_pcie_phy_fdt_attach;
59 static int ns2_pci_phy_init(device_t dev);
61 static device_method_t ns2_pcie_phy_fdt_methods[] = {
62 /* Device interface */
63 DEVMETHOD(device_probe, ns2_pcie_phy_fdt_probe),
64 DEVMETHOD(device_attach, ns2_pcie_phy_fdt_attach),
69 DEFINE_CLASS_0(ns2_pcie_phy, ns2_pcie_phy_fdt_driver, ns2_pcie_phy_fdt_methods,
70 sizeof(struct ns2_pcie_phy_softc));
72 static devclass_t ns2_pcie_phy_fdt_devclass;
74 static driver_t ns2_pcie_phy_driver = {
76 ns2_pcie_phy_fdt_methods,
77 sizeof(struct ns2_pcie_phy_softc)
79 EARLY_DRIVER_MODULE(ns2_pcie_phy, brcm_mdionexus, ns2_pcie_phy_driver,
80 ns2_pcie_phy_fdt_devclass, NULL, NULL, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
83 ns2_pci_phy_init(device_t dev)
85 struct ns2_pcie_phy_softc *sc;
88 sc = device_get_softc(dev);
90 /* select the AFE 100MHz block page */
91 err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id,
92 BLK_ADDR_REG_OFFSET, PLL_AFE1_100MHZ_BLK);
96 /* set the 100 MHz reference clock amplitude to 2.05 v */
97 err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id,
98 PLL_CLK_AMP_OFFSET, PLL_CLK_AMP_2P05V);
105 device_printf(dev, "Error %d writing to phy\n", err);
110 get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells)
114 /* Find address cells if present */
115 OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells));
118 /* Find size cells if present */
119 OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells));
123 ns2_pcie_phy_fdt_probe(device_t dev)
126 if (!ofw_bus_status_okay(dev))
129 if (!ofw_bus_is_compatible(dev, "brcm,ns2-pcie-phy"))
132 device_set_desc(dev, "Broadcom NS2 PCIe PHY");
133 return (BUS_PROBE_SPECIFIC);
137 ns2_pcie_phy_fdt_attach(device_t dev)
139 struct ns2_pcie_phy_softc *sc;
140 pcell_t addr_cells, size_cells, buf[2];
143 sc = device_get_softc(dev);
145 node = ofw_bus_get_node(dev);
146 get_addr_size_cells(OF_parent(node), &addr_cells, &size_cells);
147 if ((addr_cells != 1) || (size_cells != 0)) {
149 "Only addr_cells=1 and size_cells=0 are supported\n");
153 if (OF_getencprop(node, "reg", buf, sizeof(pcell_t)) < 0)
158 if (ns2_pci_phy_init(dev) < 0)
161 return (bus_generic_attach(dev));