2 * Copyright (c) 2015 The FreeBSD Foundation
5 * This software was developed by Semihalf under
6 * the sponsorship of the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 /* PCIe root complex driver for Cavium Thunder SOC */
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
40 #include <sys/module.h>
42 #include <sys/endian.h>
43 #include <sys/cpuset.h>
44 #include <dev/ofw/openfirm.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pcib_private.h>
50 #include <machine/cpu.h>
51 #include <machine/bus.h>
52 #include <machine/intr.h>
54 #include "thunder_pcie_common.h"
58 /* Assembling ECAM Configuration Address */
59 #define PCIE_BUS_SHIFT 20
60 #define PCIE_SLOT_SHIFT 15
61 #define PCIE_FUNC_SHIFT 12
62 #define PCIE_BUS_MASK 0xFF
63 #define PCIE_SLOT_MASK 0x1F
64 #define PCIE_FUNC_MASK 0x07
65 #define PCIE_REG_MASK 0xFFF
67 #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
68 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
69 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
70 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
71 ((reg) & PCIE_REG_MASK))
73 #define THUNDER_ECAM0_CFG_BASE 0x848000000000UL
74 #define THUNDER_ECAM1_CFG_BASE 0x849000000000UL
75 #define THUNDER_ECAM2_CFG_BASE 0x84a000000000UL
76 #define THUNDER_ECAM3_CFG_BASE 0x84b000000000UL
77 #define THUNDER_ECAM4_CFG_BASE 0x948000000000UL
78 #define THUNDER_ECAM5_CFG_BASE 0x949000000000UL
79 #define THUNDER_ECAM6_CFG_BASE 0x94a000000000UL
80 #define THUNDER_ECAM7_CFG_BASE 0x94b000000000UL
82 #define OFW_CELL_TO_UINT64(cell) \
83 (((uint64_t)(*(cell)) << 32) | (uint64_t)(*((cell) + 1)))
85 #define SPACE_CODE_SHIFT 24
86 #define SPACE_CODE_MASK 0x3
87 #define SPACE_CODE_IO_SPACE 0x1
88 #define PROPS_CELL_SIZE 1
89 #define PCI_ADDR_CELL_SIZE 2
91 struct thunder_pcie_softc {
92 struct pcie_range ranges[MAX_RANGES_TUPLES];
99 /* Forward prototypes */
100 static struct resource *thunder_pcie_alloc_resource(device_t,
101 device_t, int, int *, u_long, u_long, u_long, u_int);
102 static int thunder_pcie_attach(device_t);
103 static int thunder_pcie_identify_pcib(device_t);
104 static int thunder_pcie_maxslots(device_t);
105 static int parse_pci_mem_ranges(struct thunder_pcie_softc *);
106 static int thunder_pcie_probe(device_t);
107 static uint32_t thunder_pcie_read_config(device_t, u_int, u_int, u_int, u_int,
109 static int thunder_pcie_read_ivar(device_t, device_t, int, uintptr_t *);
110 static int thunder_pcie_release_resource(device_t, device_t, int, int,
112 static void thunder_pcie_write_config(device_t, u_int, u_int,
113 u_int, u_int, uint32_t, int);
114 static int thunder_pcie_write_ivar(device_t, device_t, int, uintptr_t);
117 thunder_pcie_probe(device_t dev)
120 if (!ofw_bus_status_okay(dev))
123 if (ofw_bus_is_compatible(dev, "cavium,thunder-pcie")) {
124 device_set_desc(dev, "Cavium Integrated PCI/PCI-E Controller");
125 return (BUS_PROBE_DEFAULT);
132 thunder_pcie_attach(device_t dev)
135 struct thunder_pcie_softc *sc;
140 sc = device_get_softc(dev);
143 /* Identify pcib domain */
144 if (thunder_pcie_identify_pcib(dev))
148 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
149 if (sc->res == NULL) {
150 device_printf(dev, "could not map memory.\n");
154 sc->mem_rman.rm_type = RMAN_ARRAY;
155 sc->mem_rman.rm_descr = "PCIe Memory";
157 /* Retrieve 'ranges' property from FDT */
159 device_printf(dev, "parsing FDT for ECAM%d:\n",
161 if (parse_pci_mem_ranges(sc))
164 /* Initialize rman and allocate memory regions */
165 error = rman_init(&sc->mem_rman);
167 device_printf(dev, "rman_init() failed. error = %d\n", error);
171 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
172 base = sc->ranges[tuple].phys_base;
173 size = sc->ranges[tuple].size;
174 if ((base == 0) || (size == 0))
175 continue; /* empty range element */
177 error = rman_manage_region(&sc->mem_rman, base, base + size - 1);
179 device_printf(dev, "rman_manage_region() failed. error = %d\n", error);
180 rman_fini(&sc->mem_rman);
184 device_add_child(dev, "pci", -1);
186 return (bus_generic_attach(dev));
190 parse_pci_mem_ranges(struct thunder_pcie_softc *sc)
193 pcell_t pci_addr_cells, parent_addr_cells, size_cells;
195 pcell_t *ranges_buf, *cell_ptr;
196 int cells_count, tuples_count;
200 node = ofw_bus_get_node(sc->dev);
202 /* Find address cells if present */
203 if (OF_getencprop(node, "#address-cells", &pci_addr_cells,
204 sizeof(pci_addr_cells)) < sizeof(pci_addr_cells))
207 /* Find size cells if present */
208 if (OF_getencprop(node, "#size-cells", &size_cells,
209 sizeof(size_cells)) < sizeof(size_cells))
212 /* Find parent address cells if present */
213 if (OF_getencprop(OF_parent(node), "#address-cells",
214 &parent_addr_cells, sizeof(parent_addr_cells)) < sizeof(parent_addr_cells))
215 parent_addr_cells = 2;
217 /* Check if FDT format matches driver requirements */
218 if ((parent_addr_cells != 2) || (pci_addr_cells != 3) ||
220 device_printf(sc->dev,
221 "Unexpected number of address or size cells in FDT "
223 parent_addr_cells, pci_addr_cells, size_cells);
227 cells_count = OF_getencprop_alloc(node, "ranges",
228 sizeof(pcell_t), (void **)&ranges_buf);
229 if (cells_count == -1) {
230 device_printf(sc->dev, "Error parsing FDT 'ranges' property\n");
234 tuples_count = cells_count /
235 (pci_addr_cells + parent_addr_cells + size_cells);
236 if ((tuples_count > MAX_RANGES_TUPLES) ||
237 (tuples_count < MIN_RANGES_TUPLES)) {
238 device_printf(sc->dev,
239 "Unexpected number of 'ranges' tuples in FDT\n");
244 cell_ptr = ranges_buf;
246 for (tuple = 0; tuple < tuples_count; tuple++) {
249 * attributes - 32-bit attributes field
250 * PCI address - bus address combined of two cells in
251 * a following format:
252 * <ADDR MSB> <ADDR LSB>
253 * PA address - physical address combined of two cells in
254 * a following format:
255 * <ADDR MSB> <ADDR LSB>
256 * size - range size combined of two cells in
257 * a following format:
258 * <ADDR MSB> <ADDR LSB>
260 attributes = *cell_ptr;
261 attributes = (attributes >> SPACE_CODE_SHIFT) & SPACE_CODE_MASK;
262 if (attributes == SPACE_CODE_IO_SPACE) {
263 /* Internal PCIe does not support IO space, ignore. */
264 sc->ranges[tuple].phys_base = 0;
265 sc->ranges[tuple].size = 0;
267 (pci_addr_cells + parent_addr_cells + size_cells);
270 cell_ptr += PROPS_CELL_SIZE;
271 sc->ranges[tuple].pci_base = OFW_CELL_TO_UINT64(cell_ptr);
272 cell_ptr += PCI_ADDR_CELL_SIZE;
273 sc->ranges[tuple].phys_base = OFW_CELL_TO_UINT64(cell_ptr);
274 cell_ptr += parent_addr_cells;
275 sc->ranges[tuple].size = OFW_CELL_TO_UINT64(cell_ptr);
276 cell_ptr += size_cells;
279 device_printf(sc->dev,
280 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n",
281 sc->ranges[tuple].pci_base,
282 sc->ranges[tuple].phys_base,
283 sc->ranges[tuple].size);
287 for (; tuple < MAX_RANGES_TUPLES; tuple++) {
288 /* zero-fill remaining tuples to mark empty elements in array */
289 sc->ranges[tuple].phys_base = 0;
290 sc->ranges[tuple].size = 0;
295 free(ranges_buf, M_OFWPROP);
300 thunder_pcie_read_config(device_t dev, u_int bus, u_int slot,
301 u_int func, u_int reg, int bytes)
305 struct thunder_pcie_softc *sc;
307 bus_space_handle_t h;
309 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
310 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
313 sc = device_get_softc(dev);
315 offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
316 t = rman_get_bustag(sc->res);
317 h = rman_get_bushandle(sc->res);
321 data = bus_space_read_1(t, h, offset);
324 data = le16toh(bus_space_read_2(t, h, offset));
327 data = le32toh(bus_space_read_4(t, h, offset));
337 thunder_pcie_write_config(device_t dev, u_int bus, u_int slot,
338 u_int func, u_int reg, uint32_t val, int bytes)
341 struct thunder_pcie_softc *sc;
343 bus_space_handle_t h;
345 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
346 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
349 sc = device_get_softc(dev);
351 offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
352 t = rman_get_bustag(sc->res);
353 h = rman_get_bushandle(sc->res);
357 bus_space_write_1(t, h, offset, val);
360 bus_space_write_2(t, h, offset, htole16(val));
363 bus_space_write_4(t, h, offset, htole32(val));
372 thunder_pcie_maxslots(device_t dev)
375 /* max slots per bus acc. to standard */
376 return (PCI_SLOTMAX);
380 thunder_pcie_read_ivar(device_t dev, device_t child, int index,
383 struct thunder_pcie_softc *sc;
385 sc = device_get_softc(dev);
387 if (index == PCIB_IVAR_BUS) {
388 /* this pcib is always on bus 0 */
392 if (index == PCIB_IVAR_DOMAIN) {
401 thunder_pcie_write_ivar(device_t dev, device_t child, int index,
409 thunder_pcie_release_resource(device_t dev, device_t child, int type, int rid,
410 struct resource *res)
413 if (type != SYS_RES_MEMORY)
414 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
417 return (rman_release_resource(res));
420 static struct resource *
421 thunder_pcie_alloc_resource(device_t dev, device_t child, int type, int *rid,
422 u_long start, u_long end, u_long count, u_int flags)
424 struct thunder_pcie_softc *sc = device_get_softc(dev);
425 struct rman *rm = NULL;
426 struct resource *res;
436 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
437 type, rid, start, end, count, flags));
440 if ((start == 0UL) && (end == ~0UL)) {
442 "Cannot allocate resource with unspecified range\n");
446 /* Convert input BUS address to required PHYS */
447 if (range_addr_is_pci(sc->ranges, start, count) == 0)
449 start = range_addr_pci_to_phys(sc->ranges, start);
450 end = start + count - 1;
454 "rman_reserve_resource: start=%#lx, end=%#lx, count=%#lx\n",
458 res = rman_reserve_resource(rm, start, end, count, flags, child);
462 rman_set_rid(res, *rid);
464 if ((flags & RF_ACTIVE) != 0)
465 if (bus_activate_resource(child, type, *rid, res)) {
466 rman_release_resource(res);
474 device_printf(dev, "%s FAIL: type=%d, rid=%d, "
475 "start=%016lx, end=%016lx, count=%016lx, flags=%x\n",
476 __func__, type, *rid, start, end, count, flags);
483 thunder_pcie_identify_pcib(device_t dev)
485 struct thunder_pcie_softc *sc;
488 sc = device_get_softc(dev);
489 start = bus_get_resource_start(dev, SYS_RES_MEMORY, 0);
492 case THUNDER_ECAM0_CFG_BASE:
495 case THUNDER_ECAM1_CFG_BASE:
498 case THUNDER_ECAM2_CFG_BASE:
501 case THUNDER_ECAM3_CFG_BASE:
504 case THUNDER_ECAM4_CFG_BASE:
507 case THUNDER_ECAM5_CFG_BASE:
510 case THUNDER_ECAM6_CFG_BASE:
513 case THUNDER_ECAM7_CFG_BASE:
518 "error: incorrect resource address=%#lx.\n", start);
524 static device_method_t thunder_pcie_methods[] = {
525 DEVMETHOD(device_probe, thunder_pcie_probe),
526 DEVMETHOD(device_attach, thunder_pcie_attach),
527 DEVMETHOD(pcib_maxslots, thunder_pcie_maxslots),
528 DEVMETHOD(pcib_read_config, thunder_pcie_read_config),
529 DEVMETHOD(pcib_write_config, thunder_pcie_write_config),
530 DEVMETHOD(bus_read_ivar, thunder_pcie_read_ivar),
531 DEVMETHOD(bus_write_ivar, thunder_pcie_write_ivar),
532 DEVMETHOD(bus_alloc_resource, thunder_pcie_alloc_resource),
533 DEVMETHOD(bus_release_resource, thunder_pcie_release_resource),
534 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
535 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
536 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
537 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
538 DEVMETHOD(pcib_map_msi, thunder_common_map_msi),
539 DEVMETHOD(pcib_alloc_msix, thunder_common_alloc_msix),
540 DEVMETHOD(pcib_release_msix, thunder_common_release_msix),
541 DEVMETHOD(pcib_alloc_msi, thunder_common_alloc_msi),
542 DEVMETHOD(pcib_release_msi, thunder_common_release_msi),
547 static driver_t thunder_pcie_driver = {
549 thunder_pcie_methods,
550 sizeof(struct thunder_pcie_softc),
553 static devclass_t thunder_pcie_devclass;
555 DRIVER_MODULE(thunder_pcib, simplebus, thunder_pcie_driver,
556 thunder_pcie_devclass, 0, 0);
557 DRIVER_MODULE(thunder_pcib, ofwbus, thunder_pcie_driver,
558 thunder_pcie_devclass, 0, 0);