2 * Copyright (c) 2015 The FreeBSD Foundation
5 * This software was developed by Semihalf under
6 * the sponsorship of the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 /* Common PCIe functions for Cavium Thunder SOC */
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include "opt_platform.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
44 #include <machine/bus.h>
45 #include <machine/cpu.h>
46 #include <machine/intr.h>
49 #include <dev/ofw/openfirm.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dev/ofw/ofw_pci.h>
55 #include <sys/pciio.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/pci_private.h>
59 #include <dev/pci/pcib_private.h>
60 #include <dev/pci/pci_host_generic.h>
62 #include <dev/pci/pci_host_generic_fdt.h>
65 #include "thunder_pcie_common.h"
67 MALLOC_DEFINE(M_THUNDER_PCIE, "Thunder PCIe driver", "Thunder PCIe driver memory");
69 #define THUNDER_CFG_BASE_TO_ECAM(x) ((((x) >> 36UL) & 0x3) | (((x) >> 42UL) & 0x4))
72 range_addr_is_pci(struct pcie_range *ranges, uint64_t addr, uint64_t size)
77 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
79 if (addr >= r->pci_base &&
80 addr < (r->pci_base + r->size) &&
82 /* Address is within PCI range */
87 /* Address is outside PCI range */
92 range_addr_is_phys(struct pcie_range *ranges, uint64_t addr, uint64_t size)
97 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
99 if (addr >= r->phys_base &&
100 addr < (r->phys_base + r->size) &&
102 /* Address is within Physical range */
107 /* Address is outside Physical range */
112 range_addr_phys_to_pci(struct pcie_range *ranges, uint64_t phys_addr)
114 struct pcie_range *r;
118 /* Find physical address corresponding to given bus address */
119 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
121 if (phys_addr >= r->phys_base &&
122 phys_addr < (r->phys_base + r->size)) {
123 /* Given phys addr is in this range.
124 * Translate phys addr to bus addr.
126 offset = phys_addr - r->phys_base;
127 return (r->pci_base + offset);
134 range_addr_pci_to_phys(struct pcie_range *ranges, uint64_t pci_addr)
136 struct pcie_range *r;
140 /* Find physical address corresponding to given bus address */
141 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
143 if (pci_addr >= r->pci_base &&
144 pci_addr < (r->pci_base + r->size)) {
145 /* Given pci addr is in this range.
146 * Translate bus addr to phys addr.
148 offset = pci_addr - r->pci_base;
149 return (r->phys_base + offset);
156 thunder_pcie_identify_ecam(device_t dev, int *ecam)
160 /* Check if we're running on Cavium ThunderX */
161 if (!CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
162 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, 0))
165 start = bus_get_resource_start(dev, SYS_RES_MEMORY, 0);
166 *ecam = THUNDER_CFG_BASE_TO_ECAM(start);
168 device_printf(dev, "ThunderX quirk, setting ECAM to %d\n", *ecam);
173 #ifdef THUNDERX_PASS_1_1_ERRATA
175 thunder_pcie_alloc_resource(device_t dev, device_t child, int type, int *rid,
176 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
178 pci_addr_t map, testval;
181 * If Enhanced Allocation is not used, we can't allocate any random
182 * range. All internal devices have hardcoded place where they can
183 * be located within PCI address space. Fortunately, we can read
184 * this value from BAR.
186 if (((type == SYS_RES_IOPORT) || (type == SYS_RES_MEMORY)) &&
187 RMAN_IS_DEFAULT_RANGE(start, end)) {
189 /* Read BAR manually to get resource address and size */
190 pci_read_bar(child, *rid, &map, &testval, NULL);
192 /* Mask the information bits */
193 if (PCI_BAR_MEM(map))
194 map &= PCIM_BAR_MEM_BASE;
196 map &= PCIM_BAR_IO_BASE;
198 if (PCI_BAR_MEM(testval))
199 testval &= PCIM_BAR_MEM_BASE;
201 testval &= PCIM_BAR_IO_BASE;
204 end = start + count - 1;
207 return (pci_host_generic_core_alloc_resource(dev, child, type, rid,
208 start, end, count, flags));