2 * Copyright (c) 2015 The FreeBSD Foundation
4 * This software was developed by Semihalf under
5 * the sponsorship of the FreeBSD Foundation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 /* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */
31 #include <sys/cdefs.h>
32 #include "opt_platform.h"
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
41 #include <sys/endian.h>
46 #include <dev/ofw/openfirm.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49 #include <dev/ofw/ofw_pci.h>
52 #include <dev/pci/pcivar.h>
53 #include <dev/pci/pcireg.h>
54 #include <dev/pci/pci_host_generic.h>
55 #include <dev/pci/pcib_private.h>
57 #include <machine/bus.h>
58 #include <machine/resource.h>
59 #include <machine/smp.h>
60 #include <machine/intr.h>
62 #include <arm64/cavium/thunder_pcie_common.h>
63 #include <arm64/cavium/thunder_pcie_pem.h>
66 #define THUNDER_PEM_DEVICE_ID 0xa020
67 #define THUNDER_PEM_VENDOR_ID 0x177d
69 /* ThunderX specific defines */
70 #define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24))
71 #define PCIERC_CFG002 0x08
72 #define PCIERC_CFG006 0x18
73 #define PCIERC_CFG032 0x80
74 #define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF)
75 #define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3)
76 #define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF)
77 #define PEM_CFG_RD 0x30
78 #define PEM_CFG_LINK_MASK 0x3
79 #define PEM_CFG_LINK_RDY 0x3
80 #define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4)
81 #define SBNUM_OFFSET 0x8
82 #define SBNUM_MASK 0xFF
83 #define PEM_ON_REG 0x420
84 #define PEM_CTL_STATUS 0x0
85 #define PEM_LINK_ENABLE (1 << 4)
86 #define PEM_LINK_DLLA (1 << 29)
87 #define PEM_LINK_LT (1 << 27)
88 #define PEM_BUS_SHIFT (24)
89 #define PEM_SLOT_SHIFT (19)
90 #define PEM_FUNC_SHIFT (16)
91 #define SLIX_S2M_REGX_ACC 0x874001000000UL
92 #define SLIX_S2M_REGX_ACC_SIZE 0x1000
93 #define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL
94 #define SLI_BASE 0x880000000000UL
95 #define SLI_WINDOW_SPACING 0x004000000000UL
96 #define SLI_PCI_OFFSET 0x001000000000UL
97 #define SLI_NODE_SHIFT (44)
98 #define SLI_NODE_MASK (3)
99 #define SLI_GROUP_SHIFT (40)
100 #define SLI_ID_SHIFT (24)
101 #define SLI_ID_MASK (7)
102 #define SLI_PEMS_PER_GROUP (3)
103 #define SLI_GROUPS_PER_NODE (2)
104 #define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE)
105 #define SLI_ACC_REG_CNT (256)
108 * Each PEM device creates its own bus with
109 * own address translation, so we can adjust bus addresses
110 * as we want. To support 32-bit cards let's assume
111 * PCI window assignment looks as following:
113 * 0x00000000 - 0x000FFFFF IO
114 * 0x00100000 - 0xFFFFFFFF Memory
116 #define PCI_IO_BASE 0x00000000UL
117 #define PCI_IO_SIZE 0x00100000UL
118 #define PCI_MEMORY_BASE PCI_IO_SIZE
119 #define PCI_MEMORY_SIZE 0xFFF00000UL
121 #define RID_PEM_SPACE 1
123 static int thunder_pem_activate_resource(device_t, device_t, int, int,
125 static int thunder_pem_adjust_resource(device_t, device_t, int,
126 struct resource *, rman_res_t, rman_res_t);
127 static struct resource * thunder_pem_alloc_resource(device_t, device_t, int,
128 int *, rman_res_t, rman_res_t, rman_res_t, u_int);
129 static int thunder_pem_alloc_msi(device_t, device_t, int, int, int *);
130 static int thunder_pem_release_msi(device_t, device_t, int, int *);
131 static int thunder_pem_alloc_msix(device_t, device_t, int *);
132 static int thunder_pem_release_msix(device_t, device_t, int);
133 static int thunder_pem_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
134 static int thunder_pem_get_id(device_t, device_t, enum pci_id_type,
136 static int thunder_pem_attach(device_t);
137 static int thunder_pem_deactivate_resource(device_t, device_t, int, int,
139 static int thunder_pem_map_resource(device_t, device_t, int, struct resource *,
140 struct resource_map_request *, struct resource_map *);
141 static int thunder_pem_unmap_resource(device_t, device_t, int,
142 struct resource *, struct resource_map *);
143 static bus_dma_tag_t thunder_pem_get_dma_tag(device_t, device_t);
144 static int thunder_pem_detach(device_t);
145 static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int);
146 static int thunder_pem_link_init(struct thunder_pem_softc *);
147 static int thunder_pem_maxslots(device_t);
148 static int thunder_pem_probe(device_t);
149 static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int,
151 static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *);
152 static void thunder_pem_release_all(device_t);
153 static int thunder_pem_release_resource(device_t, device_t, int, int,
155 static struct rman * thunder_pem_get_rman(device_t, int, u_int);
156 static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *,
158 static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int,
160 static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t);
162 /* Global handlers for SLI interface */
163 static bus_space_handle_t sli0_s2m_regx_base = 0;
164 static bus_space_handle_t sli1_s2m_regx_base = 0;
166 static device_method_t thunder_pem_methods[] = {
167 /* Device interface */
168 DEVMETHOD(device_probe, thunder_pem_probe),
169 DEVMETHOD(device_attach, thunder_pem_attach),
170 DEVMETHOD(device_detach, thunder_pem_detach),
173 DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar),
174 DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar),
175 DEVMETHOD(bus_get_rman, thunder_pem_get_rman),
176 DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource),
177 DEVMETHOD(bus_release_resource, thunder_pem_release_resource),
178 DEVMETHOD(bus_adjust_resource, thunder_pem_adjust_resource),
179 DEVMETHOD(bus_activate_resource, thunder_pem_activate_resource),
180 DEVMETHOD(bus_deactivate_resource, thunder_pem_deactivate_resource),
181 DEVMETHOD(bus_map_resource, thunder_pem_map_resource),
182 DEVMETHOD(bus_unmap_resource, thunder_pem_unmap_resource),
183 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
184 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
186 DEVMETHOD(bus_get_dma_tag, thunder_pem_get_dma_tag),
189 DEVMETHOD(pcib_maxslots, thunder_pem_maxslots),
190 DEVMETHOD(pcib_read_config, thunder_pem_read_config),
191 DEVMETHOD(pcib_write_config, thunder_pem_write_config),
192 DEVMETHOD(pcib_alloc_msix, thunder_pem_alloc_msix),
193 DEVMETHOD(pcib_release_msix, thunder_pem_release_msix),
194 DEVMETHOD(pcib_alloc_msi, thunder_pem_alloc_msi),
195 DEVMETHOD(pcib_release_msi, thunder_pem_release_msi),
196 DEVMETHOD(pcib_map_msi, thunder_pem_map_msi),
197 DEVMETHOD(pcib_get_id, thunder_pem_get_id),
202 DEFINE_CLASS_0(pcib, thunder_pem_driver, thunder_pem_methods,
203 sizeof(struct thunder_pem_softc));
205 extern struct bus_space memmap_bus;
207 DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, 0, 0);
208 MODULE_DEPEND(thunder_pem, pci, 1, 1, 1);
211 thunder_pem_maxslots(device_t dev)
215 /* max slots per bus acc. to standard */
216 return (PCI_SLOTMAX);
219 * ARM64TODO Workaround - otherwise an em(4) interface appears to be
220 * present on every PCI function on the bus to which it is connected
227 thunder_pem_read_ivar(device_t dev, device_t child, int index,
230 struct thunder_pem_softc *sc;
231 int secondary_bus = 0;
233 sc = device_get_softc(dev);
235 if (index == PCIB_IVAR_BUS) {
236 secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006);
237 *result = PCIERC_CFG006_SEC_BUS(secondary_bus);
240 if (index == PCIB_IVAR_DOMAIN) {
249 thunder_pem_write_ivar(device_t dev, device_t child, int index,
257 thunder_pem_activate_resource(device_t dev, device_t child, int type, int rid,
260 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
261 struct thunder_pem_softc *sc;
263 sc = device_get_softc(dev);
266 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
268 return (pci_domain_activate_bus(sc->id, child, rid, r));
272 return (bus_generic_rman_activate_resource(dev, child, type,
275 return (bus_generic_activate_resource(dev, child, type, rid,
281 thunder_pem_deactivate_resource(device_t dev, device_t child, int type, int rid,
284 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
285 struct thunder_pem_softc *sc;
287 sc = device_get_softc(dev);
290 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
292 return (pci_domain_deactivate_bus(sc->id, child, rid, r));
296 return (bus_generic_rman_deactivate_resource(dev, child, type,
299 return (bus_generic_deactivate_resource(dev, child, type, rid,
305 thunder_pem_map_resource(device_t dev, device_t child, int type,
306 struct resource *r, struct resource_map_request *argsp,
307 struct resource_map *map)
309 struct resource_map_request args;
310 struct thunder_pem_softc *sc;
311 rman_res_t length, start;
314 /* Resources must be active to be mapped. */
315 if (!(rman_get_flags(r) & RF_ACTIVE))
326 resource_init_map_request(&args);
327 error = resource_validate_map_request(r, argsp, &args, &start, &length);
331 sc = device_get_softc(dev);
332 start = range_addr_pci_to_phys(sc->ranges, start);
333 error = bus_space_map(&memmap_bus, start, length, 0, &map->r_bushandle);
336 map->r_bustag = &memmap_bus;
337 map->r_vaddr = (void *)map->r_bushandle;
338 map->r_size = length;
343 thunder_pem_unmap_resource(device_t dev, device_t child, int type,
344 struct resource *r, struct resource_map *map)
350 bus_space_unmap(map->r_bustag, map->r_bushandle, map->r_size);
358 thunder_pem_adjust_resource(device_t dev, device_t child, int type,
359 struct resource *res, rman_res_t start, rman_res_t end)
361 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
362 struct thunder_pem_softc *sc;
364 sc = device_get_softc(dev);
367 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
369 return (pci_domain_adjust_bus(sc->id, child, res, start, end));
373 return (bus_generic_rman_adjust_resource(dev, child, type, res,
376 return (bus_generic_adjust_resource(dev, child, type, res,
382 thunder_pem_get_dma_tag(device_t dev, device_t child)
384 struct thunder_pem_softc *sc;
386 sc = device_get_softc(dev);
391 thunder_pem_alloc_msi(device_t pci, device_t child, int count, int maxcount,
396 bus = device_get_parent(pci);
397 return (PCIB_ALLOC_MSI(device_get_parent(bus), child, count, maxcount,
402 thunder_pem_release_msi(device_t pci, device_t child, int count, int *irqs)
406 bus = device_get_parent(pci);
407 return (PCIB_RELEASE_MSI(device_get_parent(bus), child, count, irqs));
411 thunder_pem_alloc_msix(device_t pci, device_t child, int *irq)
415 bus = device_get_parent(pci);
416 return (PCIB_ALLOC_MSIX(device_get_parent(bus), child, irq));
420 thunder_pem_release_msix(device_t pci, device_t child, int irq)
424 bus = device_get_parent(pci);
425 return (PCIB_RELEASE_MSIX(device_get_parent(bus), child, irq));
429 thunder_pem_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
434 bus = device_get_parent(pci);
435 return (PCIB_MAP_MSI(device_get_parent(bus), child, irq, addr, data));
439 thunder_pem_get_id(device_t pci, device_t child, enum pci_id_type type,
445 if (type != PCI_ID_MSI)
446 return (pcib_get_id(pci, child, type, id));
448 bsf = pci_get_rid(child);
450 /* PEM (PCIe MAC/root complex) number is equal to domain */
451 pem = pci_get_domain(child);
454 * Set appropriate device ID (passed by the HW along with
455 * the transaction to memory) for different root complex
456 * numbers using hard-coded domain portion for each group.
459 *id = (0x1 << PCI_RID_DOMAIN_SHIFT) | bsf;
461 *id = (0x3 << PCI_RID_DOMAIN_SHIFT) | bsf;
463 *id = (0x9 << PCI_RID_DOMAIN_SHIFT) | bsf;
465 *id = (0xB << PCI_RID_DOMAIN_SHIFT) | bsf;
473 thunder_pem_identify(device_t dev)
475 struct thunder_pem_softc *sc;
478 sc = device_get_softc(dev);
479 start = rman_get_start(sc->reg);
481 /* Calculate PEM designations from its address */
482 sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK;
483 sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) +
484 (SLI_PEMS_PER_NODE * sc->node);
485 sc->sli = sc->id % SLI_PEMS_PER_GROUP;
486 sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE;
487 sc->sli_window_base = SLI_BASE |
488 (((uint64_t)sc->node) << SLI_NODE_SHIFT) |
489 ((uint64_t)sc->sli_group << SLI_GROUP_SHIFT);
490 sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli;
496 thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc,
497 int sli_group, int slix)
500 bus_space_handle_t handle = 0;
502 KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index"));
505 handle = sli0_s2m_regx_base;
506 else if (sli_group == 1)
507 handle = sli1_s2m_regx_base;
509 device_printf(sc->dev, "SLI group is not correct\n");
512 /* Clear lower 32-bits of the SLIx register */
513 regval = bus_space_read_8(sc->reg_bst, handle,
514 PEM_CFG_SLIX_TO_REG(slix));
515 regval &= ~(0xFFFFFFFFUL);
516 bus_space_write_8(sc->reg_bst, handle,
517 PEM_CFG_SLIX_TO_REG(slix), regval);
522 thunder_pem_link_init(struct thunder_pem_softc *sc)
526 /* check whether PEM is safe to access. */
527 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG);
528 if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) {
529 device_printf(sc->dev, "PEM%d is not ON\n", sc->id);
533 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS);
534 regval |= PEM_LINK_ENABLE;
535 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval);
537 /* Wait 1ms as per Cavium specification */
540 regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032);
542 if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) {
543 device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n",
552 thunder_pem_init(struct thunder_pem_softc *sc)
556 retval = thunder_pem_link_init(sc);
558 device_printf(sc->dev, "%s failed\n", __func__);
562 /* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */
563 for (i = 0; i < SLI_ACC_REG_CNT; i++) {
564 thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i);
571 thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg)
575 /* Write to ADDR register */
576 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD,
577 PEM_CFG_RD_REG_ALIGN(reg));
578 bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8,
579 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
580 /* Read from DATA register */
581 data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh,
588 thunder_pem_read_config(device_t dev, u_int bus, u_int slot,
589 u_int func, u_int reg, int bytes)
593 struct thunder_pem_softc *sc;
595 bus_space_handle_t h;
597 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
598 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
601 sc = device_get_softc(dev);
603 /* Calculate offset */
604 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) |
605 (func << PEM_FUNC_SHIFT);
607 h = sc->pem_sli_base;
609 bus_space_map(sc->reg_bst, sc->sli_window_base + offset,
614 data = bus_space_read_1(t, h, reg);
617 data = le16toh(bus_space_read_2(t, h, reg));
620 data = le32toh(bus_space_read_4(t, h, reg));
627 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX);
633 thunder_pem_write_config(device_t dev, u_int bus, u_int slot,
634 u_int func, u_int reg, uint32_t val, int bytes)
637 struct thunder_pem_softc *sc;
639 bus_space_handle_t h;
641 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
642 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
645 sc = device_get_softc(dev);
647 /* Calculate offset */
648 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) |
649 (func << PEM_FUNC_SHIFT);
651 h = sc->pem_sli_base;
653 bus_space_map(sc->reg_bst, sc->sli_window_base + offset,
658 bus_space_write_1(t, h, reg, val);
661 bus_space_write_2(t, h, reg, htole16(val));
664 bus_space_write_4(t, h, reg, htole32(val));
670 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX);
673 static struct resource *
674 thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid,
675 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
677 struct thunder_pem_softc *sc = device_get_softc(dev);
678 struct resource *res;
682 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
684 return (pci_domain_alloc_bus(sc->id, child, rid, start, end,
691 /* Find parent device. On ThunderX we know an exact path. */
692 parent_dev = device_get_parent(device_get_parent(dev));
693 return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start,
697 if (!RMAN_IS_DEFAULT_RANGE(start, end)) {
699 * We might get PHYS addresses here inherited from EFI.
700 * Convert to PCI if necessary.
702 if (range_addr_is_phys(sc->ranges, start, count)) {
703 start = range_addr_phys_to_pci(sc->ranges, start);
704 end = start + count - 1;
710 "thunder_pem_alloc_resource: start=%#lx, end=%#lx, count=%#lx\n",
714 res = bus_generic_rman_alloc_resource(dev, child, type, rid, start,
716 if (res == NULL && bootverbose) {
717 device_printf(dev, "%s FAIL: type=%d, rid=%d, "
718 "start=%016lx, end=%016lx, count=%016lx, flags=%x\n",
719 __func__, type, *rid, start, end, count, flags);
726 thunder_pem_release_resource(device_t dev, device_t child, int type, int rid,
727 struct resource *res)
730 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
731 struct thunder_pem_softc *sc = device_get_softc(dev);
735 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
737 return (pci_domain_release_bus(sc->id, child, rid, res));
741 return (bus_generic_rman_release_resource(dev, child, type,
744 /* Find parent device. On ThunderX we know an exact path. */
745 parent_dev = device_get_parent(device_get_parent(dev));
746 return (BUS_RELEASE_RESOURCE(parent_dev, child,
752 thunder_pem_get_rman(device_t bus, int type, u_int flags)
754 struct thunder_pem_softc *sc;
756 sc = device_get_softc(bus);
759 return (&sc->io_rman);
761 return (&sc->mem_rman);
770 thunder_pem_probe(device_t dev)
772 uint16_t pci_vendor_id;
773 uint16_t pci_device_id;
775 pci_vendor_id = pci_get_vendor(dev);
776 pci_device_id = pci_get_device(dev);
778 if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) &&
779 (pci_device_id == THUNDER_PEM_DEVICE_ID)) {
780 device_set_desc_copy(dev, THUNDER_PEM_DESC);
788 thunder_pem_attach(device_t dev)
790 struct resource_map_request req;
791 struct resource_map map;
792 devclass_t pci_class;
794 struct thunder_pem_softc *sc;
801 sc = device_get_softc(dev);
804 /* Allocate memory for resource */
805 pci_class = devclass_find("pci");
806 parent = device_get_parent(dev);
807 if (device_get_devclass(parent) == pci_class)
812 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
813 &rid, RF_ACTIVE | RF_UNMAPPED);
814 if (sc->reg == NULL) {
815 device_printf(dev, "Failed to allocate resource\n");
818 resource_init_map_request(&req);
819 req.memattr = VM_MEMATTR_DEVICE_NP;
820 error = bus_map_resource(dev, SYS_RES_MEMORY, sc->reg, &req, &map);
822 device_printf(dev, "could not map memory.\n");
825 rman_set_mapping(sc->reg, &map);
827 sc->reg_bst = rman_get_bustag(sc->reg);
828 sc->reg_bsh = rman_get_bushandle(sc->reg);
830 /* Create the parent DMA tag to pass down the coherent flag */
831 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
832 1, 0, /* alignment, bounds */
833 BUS_SPACE_MAXADDR, /* lowaddr */
834 BUS_SPACE_MAXADDR, /* highaddr */
835 NULL, NULL, /* filter, filterarg */
836 BUS_SPACE_MAXSIZE, /* maxsize */
837 BUS_SPACE_UNRESTRICTED, /* nsegments */
838 BUS_SPACE_MAXSIZE, /* maxsegsize */
839 BUS_DMA_COHERENT, /* flags */
840 NULL, NULL, /* lockfunc, lockarg */
845 /* Map SLI, do it only once */
846 if (!sli0_s2m_regx_base) {
847 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC,
848 SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base);
850 if (!sli1_s2m_regx_base) {
851 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC +
852 SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0,
853 &sli1_s2m_regx_base);
856 if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) {
858 "bus_space_map failed to map slix_s2m_regx_base\n");
863 if (thunder_pem_identify(dev) != 0)
866 /* Initialize rman and allocate regions */
867 sc->mem_rman.rm_type = RMAN_ARRAY;
868 sc->mem_rman.rm_descr = "PEM PCIe Memory";
869 error = rman_init(&sc->mem_rman);
871 device_printf(dev, "memory rman_init() failed. error = %d\n",
875 sc->io_rman.rm_type = RMAN_ARRAY;
876 sc->io_rman.rm_descr = "PEM PCIe IO";
877 error = rman_init(&sc->io_rman);
879 device_printf(dev, "IO rman_init() failed. error = %d\n",
885 * We ignore the values that may have been provided in FDT
886 * and configure ranges according to the below formula
887 * for all types of devices. This is because some DTBs provided
888 * by EFI do not have proper ranges property or don't have them
891 /* Fill memory window */
892 sc->ranges[0].pci_base = PCI_MEMORY_BASE;
893 sc->ranges[0].size = PCI_MEMORY_SIZE;
894 sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET +
895 sc->ranges[0].pci_base;
896 sc->ranges[0].flags = SYS_RES_MEMORY;
899 sc->ranges[1].pci_base = PCI_IO_BASE;
900 sc->ranges[1].size = PCI_IO_SIZE;
901 sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET +
902 sc->ranges[1].pci_base;
903 sc->ranges[1].flags = SYS_RES_IOPORT;
905 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
906 base = sc->ranges[tuple].pci_base;
907 size = sc->ranges[tuple].size;
909 continue; /* empty range element */
911 rman = thunder_pem_get_rman(dev, sc->ranges[tuple].flags, 0);
913 error = rman_manage_region(rman, base,
919 "rman_manage_region() failed. error = %d\n", error);
920 rman_fini(&sc->mem_rman);
925 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx, Flags:0x%jx\n",
926 sc->ranges[tuple].pci_base,
927 sc->ranges[tuple].phys_base,
928 sc->ranges[tuple].size,
929 sc->ranges[tuple].flags);
933 if (thunder_pem_init(sc)) {
934 device_printf(dev, "Failure during PEM init\n");
938 device_add_child(dev, "pci", -1);
940 return (bus_generic_attach(dev));
943 rman_fini(&sc->io_rman);
945 rman_fini(&sc->mem_rman);
947 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg);
952 thunder_pem_release_all(device_t dev)
954 struct thunder_pem_softc *sc;
956 sc = device_get_softc(dev);
958 rman_fini(&sc->io_rman);
959 rman_fini(&sc->mem_rman);
962 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg);
966 thunder_pem_detach(device_t dev)
969 thunder_pem_release_all(dev);