2 * Copyright (c) 2015 The FreeBSD Foundation
4 * This software was developed by Semihalf under
5 * the sponsorship of the FreeBSD Foundation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 /* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include "opt_platform.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
43 #include <sys/endian.h>
46 #include <dev/ofw/openfirm.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49 #include <dev/ofw/ofw_pci.h>
52 #include <dev/pci/pcivar.h>
53 #include <dev/pci/pcireg.h>
54 #include <dev/pci/pci_host_generic.h>
55 #include <dev/pci/pcib_private.h>
57 #include <machine/bus.h>
58 #include <machine/resource.h>
59 #include <machine/smp.h>
60 #include <machine/intr.h>
62 #include <arm64/cavium/thunder_pcie_common.h>
63 #include <arm64/cavium/thunder_pcie_pem.h>
66 #define THUNDER_PEM_DEVICE_ID 0xa020
67 #define THUNDER_PEM_VENDOR_ID 0x177d
69 /* ThunderX specific defines */
70 #define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24))
71 #define PCIERC_CFG002 0x08
72 #define PCIERC_CFG006 0x18
73 #define PCIERC_CFG032 0x80
74 #define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF)
75 #define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3)
76 #define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF)
77 #define PEM_CFG_RD 0x30
78 #define PEM_CFG_LINK_MASK 0x3
79 #define PEM_CFG_LINK_RDY 0x3
80 #define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4)
81 #define SBNUM_OFFSET 0x8
82 #define SBNUM_MASK 0xFF
83 #define PEM_ON_REG 0x420
84 #define PEM_CTL_STATUS 0x0
85 #define PEM_LINK_ENABLE (1 << 4)
86 #define PEM_LINK_DLLA (1 << 29)
87 #define PEM_LINK_LT (1 << 27)
88 #define PEM_BUS_SHIFT (24)
89 #define PEM_SLOT_SHIFT (19)
90 #define PEM_FUNC_SHIFT (16)
91 #define SLIX_S2M_REGX_ACC 0x874001000000UL
92 #define SLIX_S2M_REGX_ACC_SIZE 0x1000
93 #define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL
94 #define SLI_BASE 0x880000000000UL
95 #define SLI_WINDOW_SPACING 0x004000000000UL
96 #define SLI_PCI_OFFSET 0x001000000000UL
97 #define SLI_NODE_SHIFT (44)
98 #define SLI_NODE_MASK (3)
99 #define SLI_GROUP_SHIFT (40)
100 #define SLI_ID_SHIFT (24)
101 #define SLI_ID_MASK (7)
102 #define SLI_PEMS_PER_GROUP (3)
103 #define SLI_GROUPS_PER_NODE (2)
104 #define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE)
105 #define SLI_ACC_REG_CNT (256)
108 * Each PEM device creates its own bus with
109 * own address translation, so we can adjust bus addresses
110 * as we want. To support 32-bit cards let's assume
111 * PCI window assignment looks as following:
113 * 0x00000000 - 0x000FFFFF IO
114 * 0x00100000 - 0xFFFFFFFF Memory
116 #define PCI_IO_BASE 0x00000000UL
117 #define PCI_IO_SIZE 0x00100000UL
118 #define PCI_MEMORY_BASE PCI_IO_SIZE
119 #define PCI_MEMORY_SIZE 0xFFF00000UL
121 #define RID_PEM_SPACE 1
123 static int thunder_pem_activate_resource(device_t, device_t, int, int,
125 static int thunder_pem_adjust_resource(device_t, device_t, int,
126 struct resource *, rman_res_t, rman_res_t);
127 static struct resource * thunder_pem_alloc_resource(device_t, device_t, int,
128 int *, rman_res_t, rman_res_t, rman_res_t, u_int);
129 static int thunder_pem_alloc_msi(device_t, device_t, int, int, int *);
130 static int thunder_pem_release_msi(device_t, device_t, int, int *);
131 static int thunder_pem_alloc_msix(device_t, device_t, int *);
132 static int thunder_pem_release_msix(device_t, device_t, int);
133 static int thunder_pem_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
134 static int thunder_pem_get_id(device_t, device_t, enum pci_id_type,
136 static int thunder_pem_attach(device_t);
137 static int thunder_pem_deactivate_resource(device_t, device_t, int, int,
139 static bus_dma_tag_t thunder_pem_get_dma_tag(device_t, device_t);
140 static int thunder_pem_detach(device_t);
141 static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int);
142 static int thunder_pem_link_init(struct thunder_pem_softc *);
143 static int thunder_pem_maxslots(device_t);
144 static int thunder_pem_probe(device_t);
145 static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int,
147 static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *);
148 static void thunder_pem_release_all(device_t);
149 static int thunder_pem_release_resource(device_t, device_t, int, int,
151 static struct rman * thunder_pem_rman(struct thunder_pem_softc *, int);
152 static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *,
154 static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int,
156 static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t);
158 /* Global handlers for SLI interface */
159 static bus_space_handle_t sli0_s2m_regx_base = 0;
160 static bus_space_handle_t sli1_s2m_regx_base = 0;
162 static device_method_t thunder_pem_methods[] = {
163 /* Device interface */
164 DEVMETHOD(device_probe, thunder_pem_probe),
165 DEVMETHOD(device_attach, thunder_pem_attach),
166 DEVMETHOD(device_detach, thunder_pem_detach),
169 DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar),
170 DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar),
171 DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource),
172 DEVMETHOD(bus_release_resource, thunder_pem_release_resource),
173 DEVMETHOD(bus_adjust_resource, thunder_pem_adjust_resource),
174 DEVMETHOD(bus_activate_resource, thunder_pem_activate_resource),
175 DEVMETHOD(bus_deactivate_resource, thunder_pem_deactivate_resource),
176 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
177 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
179 DEVMETHOD(bus_get_dma_tag, thunder_pem_get_dma_tag),
182 DEVMETHOD(pcib_maxslots, thunder_pem_maxslots),
183 DEVMETHOD(pcib_read_config, thunder_pem_read_config),
184 DEVMETHOD(pcib_write_config, thunder_pem_write_config),
185 DEVMETHOD(pcib_alloc_msix, thunder_pem_alloc_msix),
186 DEVMETHOD(pcib_release_msix, thunder_pem_release_msix),
187 DEVMETHOD(pcib_alloc_msi, thunder_pem_alloc_msi),
188 DEVMETHOD(pcib_release_msi, thunder_pem_release_msi),
189 DEVMETHOD(pcib_map_msi, thunder_pem_map_msi),
190 DEVMETHOD(pcib_get_id, thunder_pem_get_id),
195 DEFINE_CLASS_0(pcib, thunder_pem_driver, thunder_pem_methods,
196 sizeof(struct thunder_pem_softc));
198 static devclass_t thunder_pem_devclass;
199 extern struct bus_space memmap_bus;
201 DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, thunder_pem_devclass, 0, 0);
202 MODULE_DEPEND(thunder_pem, pci, 1, 1, 1);
205 thunder_pem_maxslots(device_t dev)
209 /* max slots per bus acc. to standard */
210 return (PCI_SLOTMAX);
213 * ARM64TODO Workaround - otherwise an em(4) interface appears to be
214 * present on every PCI function on the bus to which it is connected
221 thunder_pem_read_ivar(device_t dev, device_t child, int index,
224 struct thunder_pem_softc *sc;
225 int secondary_bus = 0;
227 sc = device_get_softc(dev);
229 if (index == PCIB_IVAR_BUS) {
230 secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006);
231 *result = PCIERC_CFG006_SEC_BUS(secondary_bus);
234 if (index == PCIB_IVAR_DOMAIN) {
243 thunder_pem_write_ivar(device_t dev, device_t child, int index,
251 thunder_pem_activate_resource(device_t dev, device_t child, int type, int rid,
257 bus_space_handle_t vaddr;
258 struct thunder_pem_softc *sc;
260 if ((err = rman_activate_resource(r)) != 0)
263 sc = device_get_softc(dev);
266 * If this is a memory resource, map it into the kernel.
268 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
269 paddr = (bus_addr_t)rman_get_start(r);
270 psize = (bus_size_t)rman_get_size(r);
272 paddr = range_addr_pci_to_phys(sc->ranges, paddr);
274 err = bus_space_map(&memmap_bus, paddr, psize, 0, &vaddr);
276 rman_deactivate_resource(r);
279 rman_set_bustag(r, &memmap_bus);
280 rman_set_virtual(r, (void *)vaddr);
281 rman_set_bushandle(r, vaddr);
287 * This function is an exact copy of nexus_deactivate_resource()
288 * Keep it up-to-date with all changes in nexus. To be removed
289 * once bus-mapping interface is developed.
292 thunder_pem_deactivate_resource(device_t bus, device_t child, int type, int rid,
296 bus_space_handle_t vaddr;
298 psize = (bus_size_t)rman_get_size(r);
299 vaddr = rman_get_bushandle(r);
302 bus_space_unmap(&memmap_bus, vaddr, psize);
303 rman_set_virtual(r, NULL);
304 rman_set_bushandle(r, 0);
307 return (rman_deactivate_resource(r));
311 thunder_pem_adjust_resource(device_t dev, device_t child, int type,
312 struct resource *res, rman_res_t start, rman_res_t end)
314 struct thunder_pem_softc *sc;
317 sc = device_get_softc(dev);
318 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
319 if (type == PCI_RES_BUS)
320 return (pci_domain_adjust_bus(sc->id, child, res, start, end));
323 rm = thunder_pem_rman(sc, type);
325 return (bus_generic_adjust_resource(dev, child, type, res,
327 if (!rman_is_region_manager(res, rm))
329 * This means a child device has a memory or I/O
330 * resource not from you which shouldn't happen.
333 return (rman_adjust_resource(res, start, end));
337 thunder_pem_get_dma_tag(device_t dev, device_t child)
339 struct thunder_pem_softc *sc;
341 sc = device_get_softc(dev);
346 thunder_pem_alloc_msi(device_t pci, device_t child, int count, int maxcount,
351 bus = device_get_parent(pci);
352 return (PCIB_ALLOC_MSI(device_get_parent(bus), child, count, maxcount,
357 thunder_pem_release_msi(device_t pci, device_t child, int count, int *irqs)
361 bus = device_get_parent(pci);
362 return (PCIB_RELEASE_MSI(device_get_parent(bus), child, count, irqs));
366 thunder_pem_alloc_msix(device_t pci, device_t child, int *irq)
370 bus = device_get_parent(pci);
371 return (PCIB_ALLOC_MSIX(device_get_parent(bus), child, irq));
375 thunder_pem_release_msix(device_t pci, device_t child, int irq)
379 bus = device_get_parent(pci);
380 return (PCIB_RELEASE_MSIX(device_get_parent(bus), child, irq));
384 thunder_pem_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
389 bus = device_get_parent(pci);
390 return (PCIB_MAP_MSI(device_get_parent(bus), child, irq, addr, data));
394 thunder_pem_get_id(device_t pci, device_t child, enum pci_id_type type,
400 if (type != PCI_ID_MSI)
401 return (pcib_get_id(pci, child, type, id));
403 bsf = pci_get_rid(child);
405 /* PEM (PCIe MAC/root complex) number is equal to domain */
406 pem = pci_get_domain(child);
409 * Set appropriate device ID (passed by the HW along with
410 * the transaction to memory) for different root complex
411 * numbers using hard-coded domain portion for each group.
414 *id = (0x1 << PCI_RID_DOMAIN_SHIFT) | bsf;
416 *id = (0x3 << PCI_RID_DOMAIN_SHIFT) | bsf;
418 *id = (0x9 << PCI_RID_DOMAIN_SHIFT) | bsf;
420 *id = (0xB << PCI_RID_DOMAIN_SHIFT) | bsf;
428 thunder_pem_identify(device_t dev)
430 struct thunder_pem_softc *sc;
433 sc = device_get_softc(dev);
434 start = rman_get_start(sc->reg);
436 /* Calculate PEM designations from its address */
437 sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK;
438 sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) +
439 (SLI_PEMS_PER_NODE * sc->node);
440 sc->sli = sc->id % SLI_PEMS_PER_GROUP;
441 sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE;
442 sc->sli_window_base = SLI_BASE |
443 (((uint64_t)sc->node) << SLI_NODE_SHIFT) |
444 ((uint64_t)sc->sli_group << SLI_GROUP_SHIFT);
445 sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli;
451 thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc,
452 int sli_group, int slix)
455 bus_space_handle_t handle = 0;
457 KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index"));
460 handle = sli0_s2m_regx_base;
461 else if (sli_group == 1)
462 handle = sli1_s2m_regx_base;
464 device_printf(sc->dev, "SLI group is not correct\n");
467 /* Clear lower 32-bits of the SLIx register */
468 regval = bus_space_read_8(sc->reg_bst, handle,
469 PEM_CFG_SLIX_TO_REG(slix));
470 regval &= ~(0xFFFFFFFFUL);
471 bus_space_write_8(sc->reg_bst, handle,
472 PEM_CFG_SLIX_TO_REG(slix), regval);
477 thunder_pem_link_init(struct thunder_pem_softc *sc)
481 /* check whether PEM is safe to access. */
482 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG);
483 if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) {
484 device_printf(sc->dev, "PEM%d is not ON\n", sc->id);
488 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS);
489 regval |= PEM_LINK_ENABLE;
490 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval);
492 /* Wait 1ms as per Cavium specification */
495 regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032);
497 if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) {
498 device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n",
507 thunder_pem_init(struct thunder_pem_softc *sc)
511 retval = thunder_pem_link_init(sc);
513 device_printf(sc->dev, "%s failed\n", __func__);
517 /* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */
518 for (i = 0; i < SLI_ACC_REG_CNT; i++) {
519 thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i);
526 thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg)
530 /* Write to ADDR register */
531 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD,
532 PEM_CFG_RD_REG_ALIGN(reg));
533 bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8,
534 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
535 /* Read from DATA register */
536 data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh,
543 thunder_pem_read_config(device_t dev, u_int bus, u_int slot,
544 u_int func, u_int reg, int bytes)
548 struct thunder_pem_softc *sc;
550 bus_space_handle_t h;
552 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
553 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
556 sc = device_get_softc(dev);
558 /* Calculate offset */
559 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) |
560 (func << PEM_FUNC_SHIFT);
562 h = sc->pem_sli_base;
564 bus_space_map(sc->reg_bst, sc->sli_window_base + offset,
569 data = bus_space_read_1(t, h, reg);
572 data = le16toh(bus_space_read_2(t, h, reg));
575 data = le32toh(bus_space_read_4(t, h, reg));
582 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX);
588 thunder_pem_write_config(device_t dev, u_int bus, u_int slot,
589 u_int func, u_int reg, uint32_t val, int bytes)
592 struct thunder_pem_softc *sc;
594 bus_space_handle_t h;
596 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
597 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
600 sc = device_get_softc(dev);
602 /* Calculate offset */
603 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) |
604 (func << PEM_FUNC_SHIFT);
606 h = sc->pem_sli_base;
608 bus_space_map(sc->reg_bst, sc->sli_window_base + offset,
613 bus_space_write_1(t, h, reg, val);
616 bus_space_write_2(t, h, reg, htole16(val));
619 bus_space_write_4(t, h, reg, htole32(val));
625 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX);
628 static struct resource *
629 thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid,
630 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
632 struct thunder_pem_softc *sc = device_get_softc(dev);
633 struct rman *rm = NULL;
634 struct resource *res;
637 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
638 if (type == PCI_RES_BUS)
639 return (pci_domain_alloc_bus(sc->id, child, rid, start, end,
642 rm = thunder_pem_rman(sc, type);
644 /* Find parent device. On ThunderX we know an exact path. */
645 parent_dev = device_get_parent(device_get_parent(dev));
646 return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start,
650 if (!RMAN_IS_DEFAULT_RANGE(start, end)) {
652 * We might get PHYS addresses here inherited from EFI.
653 * Convert to PCI if necessary.
655 if (range_addr_is_phys(sc->ranges, start, count)) {
656 start = range_addr_phys_to_pci(sc->ranges, start);
657 end = start + count - 1;
663 "thunder_pem_alloc_resource: start=%#lx, end=%#lx, count=%#lx\n",
667 res = rman_reserve_resource(rm, start, end, count, flags, child);
671 rman_set_rid(res, *rid);
673 if (flags & RF_ACTIVE)
674 if (bus_activate_resource(child, type, *rid, res)) {
675 rman_release_resource(res);
683 device_printf(dev, "%s FAIL: type=%d, rid=%d, "
684 "start=%016lx, end=%016lx, count=%016lx, flags=%x\n",
685 __func__, type, *rid, start, end, count, flags);
692 thunder_pem_release_resource(device_t dev, device_t child, int type, int rid,
693 struct resource *res)
696 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
697 struct thunder_pem_softc *sc = device_get_softc(dev);
699 if (type == PCI_RES_BUS)
700 return (pci_domain_release_bus(sc->id, child, rid, res));
702 /* Find parent device. On ThunderX we know an exact path. */
703 parent_dev = device_get_parent(device_get_parent(dev));
705 if ((type != SYS_RES_MEMORY) && (type != SYS_RES_IOPORT))
706 return (BUS_RELEASE_RESOURCE(parent_dev, child,
709 return (rman_release_resource(res));
713 thunder_pem_rman(struct thunder_pem_softc *sc, int type)
718 return (&sc->io_rman);
720 return (&sc->mem_rman);
729 thunder_pem_probe(device_t dev)
731 uint16_t pci_vendor_id;
732 uint16_t pci_device_id;
734 pci_vendor_id = pci_get_vendor(dev);
735 pci_device_id = pci_get_device(dev);
737 if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) &&
738 (pci_device_id == THUNDER_PEM_DEVICE_ID)) {
739 device_set_desc_copy(dev, THUNDER_PEM_DESC);
747 thunder_pem_attach(device_t dev)
749 devclass_t pci_class;
751 struct thunder_pem_softc *sc;
758 sc = device_get_softc(dev);
761 /* Allocate memory for resource */
762 pci_class = devclass_find("pci");
763 parent = device_get_parent(dev);
764 if (device_get_devclass(parent) == pci_class)
769 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
771 if (sc->reg == NULL) {
772 device_printf(dev, "Failed to allocate resource\n");
775 sc->reg_bst = rman_get_bustag(sc->reg);
776 sc->reg_bsh = rman_get_bushandle(sc->reg);
778 /* Create the parent DMA tag to pass down the coherent flag */
779 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
780 1, 0, /* alignment, bounds */
781 BUS_SPACE_MAXADDR, /* lowaddr */
782 BUS_SPACE_MAXADDR, /* highaddr */
783 NULL, NULL, /* filter, filterarg */
784 BUS_SPACE_MAXSIZE, /* maxsize */
785 BUS_SPACE_UNRESTRICTED, /* nsegments */
786 BUS_SPACE_MAXSIZE, /* maxsegsize */
787 BUS_DMA_COHERENT, /* flags */
788 NULL, NULL, /* lockfunc, lockarg */
793 /* Map SLI, do it only once */
794 if (!sli0_s2m_regx_base) {
795 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC,
796 SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base);
798 if (!sli1_s2m_regx_base) {
799 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC +
800 SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0,
801 &sli1_s2m_regx_base);
804 if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) {
806 "bus_space_map failed to map slix_s2m_regx_base\n");
811 if (thunder_pem_identify(dev) != 0)
814 /* Initialize rman and allocate regions */
815 sc->mem_rman.rm_type = RMAN_ARRAY;
816 sc->mem_rman.rm_descr = "PEM PCIe Memory";
817 error = rman_init(&sc->mem_rman);
819 device_printf(dev, "memory rman_init() failed. error = %d\n",
823 sc->io_rman.rm_type = RMAN_ARRAY;
824 sc->io_rman.rm_descr = "PEM PCIe IO";
825 error = rman_init(&sc->io_rman);
827 device_printf(dev, "IO rman_init() failed. error = %d\n",
833 * We ignore the values that may have been provided in FDT
834 * and configure ranges according to the below formula
835 * for all types of devices. This is because some DTBs provided
836 * by EFI do not have proper ranges property or don't have them
839 /* Fill memory window */
840 sc->ranges[0].pci_base = PCI_MEMORY_BASE;
841 sc->ranges[0].size = PCI_MEMORY_SIZE;
842 sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET +
843 sc->ranges[0].pci_base;
844 sc->ranges[0].flags = SYS_RES_MEMORY;
847 sc->ranges[1].pci_base = PCI_IO_BASE;
848 sc->ranges[1].size = PCI_IO_SIZE;
849 sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET +
850 sc->ranges[1].pci_base;
851 sc->ranges[1].flags = SYS_RES_IOPORT;
853 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
854 base = sc->ranges[tuple].pci_base;
855 size = sc->ranges[tuple].size;
857 continue; /* empty range element */
859 rman = thunder_pem_rman(sc, sc->ranges[tuple].flags);
861 error = rman_manage_region(rman, base,
867 "rman_manage_region() failed. error = %d\n", error);
868 rman_fini(&sc->mem_rman);
873 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx, Flags:0x%jx\n",
874 sc->ranges[tuple].pci_base,
875 sc->ranges[tuple].phys_base,
876 sc->ranges[tuple].size,
877 sc->ranges[tuple].flags);
881 if (thunder_pem_init(sc)) {
882 device_printf(dev, "Failure during PEM init\n");
886 device_add_child(dev, "pci", -1);
888 return (bus_generic_attach(dev));
891 rman_fini(&sc->io_rman);
893 rman_fini(&sc->mem_rman);
895 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg);
900 thunder_pem_release_all(device_t dev)
902 struct thunder_pem_softc *sc;
904 sc = device_get_softc(dev);
906 rman_fini(&sc->io_rman);
907 rman_fini(&sc->mem_rman);
910 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg);
914 thunder_pem_detach(device_t dev)
917 thunder_pem_release_all(dev);