2 * Copyright (c) 2015 The FreeBSD Foundation
5 * This software was developed by Semihalf under
6 * the sponsorship of the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 /* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include "opt_platform.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
44 #include <sys/endian.h>
47 #include <dev/ofw/openfirm.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
50 #include <dev/ofw/ofw_pci.h>
53 #include <dev/pci/pcivar.h>
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pci_host_generic.h>
56 #include <dev/pci/pcib_private.h>
58 #include <machine/bus.h>
59 #include <machine/resource.h>
60 #include <machine/smp.h>
61 #include <machine/intr.h>
63 #include <arm64/cavium/thunder_pcie_common.h>
64 #include <arm64/cavium/thunder_pcie_pem.h>
67 #define THUNDER_PEM_DEVICE_ID 0xa020
68 #define THUNDER_PEM_VENDOR_ID 0x177d
70 /* ThunderX specific defines */
71 #define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24))
72 #define PCIERC_CFG002 0x08
73 #define PCIERC_CFG006 0x18
74 #define PCIERC_CFG032 0x80
75 #define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF)
76 #define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3)
77 #define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF)
78 #define PEM_CFG_RD 0x30
79 #define PEM_CFG_LINK_MASK 0x3
80 #define PEM_CFG_LINK_RDY 0x3
81 #define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4)
82 #define SBNUM_OFFSET 0x8
83 #define SBNUM_MASK 0xFF
84 #define PEM_ON_REG 0x420
85 #define PEM_CTL_STATUS 0x0
86 #define PEM_LINK_ENABLE (1 << 4)
87 #define PEM_LINK_DLLA (1 << 29)
88 #define PEM_LINK_LT (1 << 27)
89 #define PEM_BUS_SHIFT (24)
90 #define PEM_SLOT_SHIFT (19)
91 #define PEM_FUNC_SHIFT (16)
92 #define SLIX_S2M_REGX_ACC 0x874001000000UL
93 #define SLIX_S2M_REGX_ACC_SIZE 0x1000
94 #define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL
95 #define SLI_BASE 0x880000000000UL
96 #define SLI_WINDOW_SPACING 0x004000000000UL
97 #define SLI_PCI_OFFSET 0x001000000000UL
98 #define SLI_NODE_SHIFT (44)
99 #define SLI_NODE_MASK (3)
100 #define SLI_GROUP_SHIFT (40)
101 #define SLI_ID_SHIFT (24)
102 #define SLI_ID_MASK (7)
103 #define SLI_PEMS_PER_GROUP (3)
104 #define SLI_GROUPS_PER_NODE (2)
105 #define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE)
106 #define SLI_ACC_REG_CNT (256)
109 * Each PEM device creates its own bus with
110 * own address translation, so we can adjust bus addresses
111 * as we want. To support 32-bit cards let's assume
112 * PCI window assignment looks as following:
114 * 0x00000000 - 0x000FFFFF IO
115 * 0x00100000 - 0xFFFFFFFF Memory
117 #define PCI_IO_BASE 0x00000000UL
118 #define PCI_IO_SIZE 0x00100000UL
119 #define PCI_MEMORY_BASE PCI_IO_SIZE
120 #define PCI_MEMORY_SIZE 0xFFF00000UL
122 #define RID_PEM_SPACE 1
124 static int thunder_pem_activate_resource(device_t, device_t, int, int,
126 static int thunder_pem_adjust_resource(device_t, device_t, int,
127 struct resource *, rman_res_t, rman_res_t);
128 static struct resource * thunder_pem_alloc_resource(device_t, device_t, int,
129 int *, rman_res_t, rman_res_t, rman_res_t, u_int);
130 static int thunder_pem_alloc_msi(device_t, device_t, int, int, int *);
131 static int thunder_pem_release_msi(device_t, device_t, int, int *);
132 static int thunder_pem_alloc_msix(device_t, device_t, int *);
133 static int thunder_pem_release_msix(device_t, device_t, int);
134 static int thunder_pem_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
135 static int thunder_pem_get_id(device_t, device_t, enum pci_id_type,
137 static int thunder_pem_attach(device_t);
138 static int thunder_pem_deactivate_resource(device_t, device_t, int, int,
140 static bus_dma_tag_t thunder_pem_get_dma_tag(device_t, device_t);
141 static int thunder_pem_detach(device_t);
142 static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int);
143 static int thunder_pem_link_init(struct thunder_pem_softc *);
144 static int thunder_pem_maxslots(device_t);
145 static int thunder_pem_probe(device_t);
146 static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int,
148 static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *);
149 static void thunder_pem_release_all(device_t);
150 static int thunder_pem_release_resource(device_t, device_t, int, int,
152 static struct rman * thunder_pem_rman(struct thunder_pem_softc *, int);
153 static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *,
155 static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int,
157 static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t);
159 /* Global handlers for SLI interface */
160 static bus_space_handle_t sli0_s2m_regx_base = 0;
161 static bus_space_handle_t sli1_s2m_regx_base = 0;
163 static device_method_t thunder_pem_methods[] = {
164 /* Device interface */
165 DEVMETHOD(device_probe, thunder_pem_probe),
166 DEVMETHOD(device_attach, thunder_pem_attach),
167 DEVMETHOD(device_detach, thunder_pem_detach),
170 DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar),
171 DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar),
172 DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource),
173 DEVMETHOD(bus_release_resource, thunder_pem_release_resource),
174 DEVMETHOD(bus_adjust_resource, thunder_pem_adjust_resource),
175 DEVMETHOD(bus_activate_resource, thunder_pem_activate_resource),
176 DEVMETHOD(bus_deactivate_resource, thunder_pem_deactivate_resource),
177 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
178 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
180 DEVMETHOD(bus_get_dma_tag, thunder_pem_get_dma_tag),
183 DEVMETHOD(pcib_maxslots, thunder_pem_maxslots),
184 DEVMETHOD(pcib_read_config, thunder_pem_read_config),
185 DEVMETHOD(pcib_write_config, thunder_pem_write_config),
186 DEVMETHOD(pcib_alloc_msix, thunder_pem_alloc_msix),
187 DEVMETHOD(pcib_release_msix, thunder_pem_release_msix),
188 DEVMETHOD(pcib_alloc_msi, thunder_pem_alloc_msi),
189 DEVMETHOD(pcib_release_msi, thunder_pem_release_msi),
190 DEVMETHOD(pcib_map_msi, thunder_pem_map_msi),
191 DEVMETHOD(pcib_get_id, thunder_pem_get_id),
196 DEFINE_CLASS_0(pcib, thunder_pem_driver, thunder_pem_methods,
197 sizeof(struct thunder_pem_softc));
199 static devclass_t thunder_pem_devclass;
200 extern struct bus_space memmap_bus;
202 DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, thunder_pem_devclass, 0, 0);
203 MODULE_DEPEND(thunder_pem, pci, 1, 1, 1);
206 thunder_pem_maxslots(device_t dev)
210 /* max slots per bus acc. to standard */
211 return (PCI_SLOTMAX);
214 * ARM64TODO Workaround - otherwise an em(4) interface appears to be
215 * present on every PCI function on the bus to which it is connected
222 thunder_pem_read_ivar(device_t dev, device_t child, int index,
225 struct thunder_pem_softc *sc;
226 int secondary_bus = 0;
228 sc = device_get_softc(dev);
230 if (index == PCIB_IVAR_BUS) {
231 secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006);
232 *result = PCIERC_CFG006_SEC_BUS(secondary_bus);
235 if (index == PCIB_IVAR_DOMAIN) {
244 thunder_pem_write_ivar(device_t dev, device_t child, int index,
252 thunder_pem_activate_resource(device_t dev, device_t child, int type, int rid,
258 bus_space_handle_t vaddr;
259 struct thunder_pem_softc *sc;
261 if ((err = rman_activate_resource(r)) != 0)
264 sc = device_get_softc(dev);
267 * If this is a memory resource, map it into the kernel.
269 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
270 paddr = (bus_addr_t)rman_get_start(r);
271 psize = (bus_size_t)rman_get_size(r);
273 paddr = range_addr_pci_to_phys(sc->ranges, paddr);
275 err = bus_space_map(&memmap_bus, paddr, psize, 0, &vaddr);
277 rman_deactivate_resource(r);
280 rman_set_bustag(r, &memmap_bus);
281 rman_set_virtual(r, (void *)vaddr);
282 rman_set_bushandle(r, vaddr);
288 * This function is an exact copy of nexus_deactivate_resource()
289 * Keep it up-to-date with all changes in nexus. To be removed
290 * once bus-mapping interface is developed.
293 thunder_pem_deactivate_resource(device_t bus, device_t child, int type, int rid,
297 bus_space_handle_t vaddr;
299 psize = (bus_size_t)rman_get_size(r);
300 vaddr = rman_get_bushandle(r);
303 bus_space_unmap(&memmap_bus, vaddr, psize);
304 rman_set_virtual(r, NULL);
305 rman_set_bushandle(r, 0);
308 return (rman_deactivate_resource(r));
312 thunder_pem_adjust_resource(device_t dev, device_t child, int type,
313 struct resource *res, rman_res_t start, rman_res_t end)
315 struct thunder_pem_softc *sc;
318 sc = device_get_softc(dev);
319 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
320 if (type == PCI_RES_BUS)
321 return (pci_domain_adjust_bus(sc->id, child, res, start, end));
324 rm = thunder_pem_rman(sc, type);
326 return (bus_generic_adjust_resource(dev, child, type, res,
328 if (!rman_is_region_manager(res, rm))
330 * This means a child device has a memory or I/O
331 * resource not from you which shouldn't happen.
334 return (rman_adjust_resource(res, start, end));
338 thunder_pem_get_dma_tag(device_t dev, device_t child)
340 struct thunder_pem_softc *sc;
342 sc = device_get_softc(dev);
347 thunder_pem_alloc_msi(device_t pci, device_t child, int count, int maxcount,
352 bus = device_get_parent(pci);
353 return (PCIB_ALLOC_MSI(device_get_parent(bus), child, count, maxcount,
358 thunder_pem_release_msi(device_t pci, device_t child, int count, int *irqs)
362 bus = device_get_parent(pci);
363 return (PCIB_RELEASE_MSI(device_get_parent(bus), child, count, irqs));
367 thunder_pem_alloc_msix(device_t pci, device_t child, int *irq)
371 bus = device_get_parent(pci);
372 return (PCIB_ALLOC_MSIX(device_get_parent(bus), child, irq));
376 thunder_pem_release_msix(device_t pci, device_t child, int irq)
380 bus = device_get_parent(pci);
381 return (PCIB_RELEASE_MSIX(device_get_parent(bus), child, irq));
385 thunder_pem_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
390 bus = device_get_parent(pci);
391 return (PCIB_MAP_MSI(device_get_parent(bus), child, irq, addr, data));
395 thunder_pem_get_id(device_t pci, device_t child, enum pci_id_type type,
401 if (type != PCI_ID_MSI)
402 return (pcib_get_id(pci, child, type, id));
404 bsf = pci_get_rid(child);
406 /* PEM (PCIe MAC/root complex) number is equal to domain */
407 pem = pci_get_domain(child);
410 * Set appropriate device ID (passed by the HW along with
411 * the transaction to memory) for different root complex
412 * numbers using hard-coded domain portion for each group.
415 *id = (0x1 << PCI_RID_DOMAIN_SHIFT) | bsf;
417 *id = (0x3 << PCI_RID_DOMAIN_SHIFT) | bsf;
419 *id = (0x9 << PCI_RID_DOMAIN_SHIFT) | bsf;
421 *id = (0xB << PCI_RID_DOMAIN_SHIFT) | bsf;
429 thunder_pem_identify(device_t dev)
431 struct thunder_pem_softc *sc;
434 sc = device_get_softc(dev);
435 start = rman_get_start(sc->reg);
437 /* Calculate PEM designations from its address */
438 sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK;
439 sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) +
440 (SLI_PEMS_PER_NODE * sc->node);
441 sc->sli = sc->id % SLI_PEMS_PER_GROUP;
442 sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE;
443 sc->sli_window_base = SLI_BASE |
444 (((uint64_t)sc->node) << SLI_NODE_SHIFT) |
445 ((uint64_t)sc->sli_group << SLI_GROUP_SHIFT);
446 sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli;
452 thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc,
453 int sli_group, int slix)
456 bus_space_handle_t handle = 0;
458 KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index"));
461 handle = sli0_s2m_regx_base;
462 else if (sli_group == 1)
463 handle = sli1_s2m_regx_base;
465 device_printf(sc->dev, "SLI group is not correct\n");
468 /* Clear lower 32-bits of the SLIx register */
469 regval = bus_space_read_8(sc->reg_bst, handle,
470 PEM_CFG_SLIX_TO_REG(slix));
471 regval &= ~(0xFFFFFFFFUL);
472 bus_space_write_8(sc->reg_bst, handle,
473 PEM_CFG_SLIX_TO_REG(slix), regval);
478 thunder_pem_link_init(struct thunder_pem_softc *sc)
482 /* check whether PEM is safe to access. */
483 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG);
484 if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) {
485 device_printf(sc->dev, "PEM%d is not ON\n", sc->id);
489 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS);
490 regval |= PEM_LINK_ENABLE;
491 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval);
493 /* Wait 1ms as per Cavium specification */
496 regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032);
498 if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) {
499 device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n",
508 thunder_pem_init(struct thunder_pem_softc *sc)
512 retval = thunder_pem_link_init(sc);
514 device_printf(sc->dev, "%s failed\n", __func__);
518 /* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */
519 for (i = 0; i < SLI_ACC_REG_CNT; i++) {
520 thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i);
527 thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg)
531 /* Write to ADDR register */
532 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD,
533 PEM_CFG_RD_REG_ALIGN(reg));
534 bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8,
535 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
536 /* Read from DATA register */
537 data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh,
544 thunder_pem_read_config(device_t dev, u_int bus, u_int slot,
545 u_int func, u_int reg, int bytes)
549 struct thunder_pem_softc *sc;
551 bus_space_handle_t h;
553 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
554 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
557 sc = device_get_softc(dev);
559 /* Calculate offset */
560 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) |
561 (func << PEM_FUNC_SHIFT);
563 h = sc->pem_sli_base;
565 bus_space_map(sc->reg_bst, sc->sli_window_base + offset,
570 data = bus_space_read_1(t, h, reg);
573 data = le16toh(bus_space_read_2(t, h, reg));
576 data = le32toh(bus_space_read_4(t, h, reg));
583 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX);
589 thunder_pem_write_config(device_t dev, u_int bus, u_int slot,
590 u_int func, u_int reg, uint32_t val, int bytes)
593 struct thunder_pem_softc *sc;
595 bus_space_handle_t h;
597 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
598 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
601 sc = device_get_softc(dev);
603 /* Calculate offset */
604 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) |
605 (func << PEM_FUNC_SHIFT);
607 h = sc->pem_sli_base;
609 bus_space_map(sc->reg_bst, sc->sli_window_base + offset,
614 bus_space_write_1(t, h, reg, val);
617 bus_space_write_2(t, h, reg, htole16(val));
620 bus_space_write_4(t, h, reg, htole32(val));
626 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX);
629 static struct resource *
630 thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid,
631 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
633 struct thunder_pem_softc *sc = device_get_softc(dev);
634 struct rman *rm = NULL;
635 struct resource *res;
638 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
639 if (type == PCI_RES_BUS)
640 return (pci_domain_alloc_bus(sc->id, child, rid, start, end,
643 rm = thunder_pem_rman(sc, type);
645 /* Find parent device. On ThunderX we know an exact path. */
646 parent_dev = device_get_parent(device_get_parent(dev));
647 return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start,
652 if (!RMAN_IS_DEFAULT_RANGE(start, end)) {
654 * We might get PHYS addresses here inherited from EFI.
655 * Convert to PCI if necessary.
657 if (range_addr_is_phys(sc->ranges, start, count)) {
658 start = range_addr_phys_to_pci(sc->ranges, start);
659 end = start + count - 1;
666 "thunder_pem_alloc_resource: start=%#lx, end=%#lx, count=%#lx\n",
670 res = rman_reserve_resource(rm, start, end, count, flags, child);
674 rman_set_rid(res, *rid);
676 if (flags & RF_ACTIVE)
677 if (bus_activate_resource(child, type, *rid, res)) {
678 rman_release_resource(res);
686 device_printf(dev, "%s FAIL: type=%d, rid=%d, "
687 "start=%016lx, end=%016lx, count=%016lx, flags=%x\n",
688 __func__, type, *rid, start, end, count, flags);
695 thunder_pem_release_resource(device_t dev, device_t child, int type, int rid,
696 struct resource *res)
699 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
700 struct thunder_pem_softc *sc = device_get_softc(dev);
702 if (type == PCI_RES_BUS)
703 return (pci_domain_release_bus(sc->id, child, rid, res));
705 /* Find parent device. On ThunderX we know an exact path. */
706 parent_dev = device_get_parent(device_get_parent(dev));
708 if ((type != SYS_RES_MEMORY) && (type != SYS_RES_IOPORT))
709 return (BUS_RELEASE_RESOURCE(parent_dev, child,
712 return (rman_release_resource(res));
716 thunder_pem_rman(struct thunder_pem_softc *sc, int type)
721 return (&sc->io_rman);
723 return (&sc->mem_rman);
732 thunder_pem_probe(device_t dev)
734 uint16_t pci_vendor_id;
735 uint16_t pci_device_id;
737 pci_vendor_id = pci_get_vendor(dev);
738 pci_device_id = pci_get_device(dev);
740 if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) &&
741 (pci_device_id == THUNDER_PEM_DEVICE_ID)) {
742 device_set_desc_copy(dev, THUNDER_PEM_DESC);
750 thunder_pem_attach(device_t dev)
752 devclass_t pci_class;
754 struct thunder_pem_softc *sc;
761 sc = device_get_softc(dev);
764 /* Allocate memory for resource */
765 pci_class = devclass_find("pci");
766 parent = device_get_parent(dev);
767 if (device_get_devclass(parent) == pci_class)
772 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
774 if (sc->reg == NULL) {
775 device_printf(dev, "Failed to allocate resource\n");
778 sc->reg_bst = rman_get_bustag(sc->reg);
779 sc->reg_bsh = rman_get_bushandle(sc->reg);
781 /* Create the parent DMA tag to pass down the coherent flag */
782 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
783 1, 0, /* alignment, bounds */
784 BUS_SPACE_MAXADDR, /* lowaddr */
785 BUS_SPACE_MAXADDR, /* highaddr */
786 NULL, NULL, /* filter, filterarg */
787 BUS_SPACE_MAXSIZE, /* maxsize */
788 BUS_SPACE_UNRESTRICTED, /* nsegments */
789 BUS_SPACE_MAXSIZE, /* maxsegsize */
790 BUS_DMA_COHERENT, /* flags */
791 NULL, NULL, /* lockfunc, lockarg */
796 /* Map SLI, do it only once */
797 if (!sli0_s2m_regx_base) {
798 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC,
799 SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base);
801 if (!sli1_s2m_regx_base) {
802 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC +
803 SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0,
804 &sli1_s2m_regx_base);
807 if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) {
809 "bus_space_map failed to map slix_s2m_regx_base\n");
814 if (thunder_pem_identify(dev) != 0)
817 /* Initialize rman and allocate regions */
818 sc->mem_rman.rm_type = RMAN_ARRAY;
819 sc->mem_rman.rm_descr = "PEM PCIe Memory";
820 error = rman_init(&sc->mem_rman);
822 device_printf(dev, "memory rman_init() failed. error = %d\n",
826 sc->io_rman.rm_type = RMAN_ARRAY;
827 sc->io_rman.rm_descr = "PEM PCIe IO";
828 error = rman_init(&sc->io_rman);
830 device_printf(dev, "IO rman_init() failed. error = %d\n",
836 * We ignore the values that may have been provided in FDT
837 * and configure ranges according to the below formula
838 * for all types of devices. This is because some DTBs provided
839 * by EFI do not have proper ranges property or don't have them
842 /* Fill memory window */
843 sc->ranges[0].pci_base = PCI_MEMORY_BASE;
844 sc->ranges[0].size = PCI_MEMORY_SIZE;
845 sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET +
846 sc->ranges[0].pci_base;
847 sc->ranges[0].flags = SYS_RES_MEMORY;
850 sc->ranges[1].pci_base = PCI_IO_BASE;
851 sc->ranges[1].size = PCI_IO_SIZE;
852 sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET +
853 sc->ranges[1].pci_base;
854 sc->ranges[1].flags = SYS_RES_IOPORT;
856 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
857 base = sc->ranges[tuple].pci_base;
858 size = sc->ranges[tuple].size;
860 continue; /* empty range element */
862 rman = thunder_pem_rman(sc, sc->ranges[tuple].flags);
864 error = rman_manage_region(rman, base,
870 "rman_manage_region() failed. error = %d\n", error);
871 rman_fini(&sc->mem_rman);
876 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx, Flags:0x%jx\n",
877 sc->ranges[tuple].pci_base,
878 sc->ranges[tuple].phys_base,
879 sc->ranges[tuple].size,
880 sc->ranges[tuple].flags);
884 if (thunder_pem_init(sc)) {
885 device_printf(dev, "Failure during PEM init\n");
889 device_add_child(dev, "pci", -1);
891 return (bus_generic_attach(dev));
894 rman_fini(&sc->io_rman);
896 rman_fini(&sc->mem_rman);
898 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg);
903 thunder_pem_release_all(device_t dev)
905 struct thunder_pem_softc *sc;
907 sc = device_get_softc(dev);
909 rman_fini(&sc->io_rman);
910 rman_fini(&sc->mem_rman);
913 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg);
917 thunder_pem_detach(device_t dev)
920 thunder_pem_release_all(dev);