2 * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by BAE Systems, the University of Cambridge
6 * Computer Laboratory, and Memorial University under DARPA/AFRL contract
7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
8 * (TC) research program.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <machine/bus.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
46 #include <arm64/coresight/coresight.h>
47 #include <arm64/coresight/coresight-etm4x.h>
49 #include "coresight_if.h"
55 #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
57 #define dprintf(fmt, ...)
63 * CPU0 -> ETM0 -> funnel1 -> funnel0 -> ETF -> replicator -> ETR -> DRAM
64 * CPU1 -> ETM1 -> funnel1 -^
65 * CPU2 -> ETM2 -> funnel1 -^
66 * CPU3 -> ETM3 -> funnel1 -^
69 static struct ofw_compat_data compat_data[] = {
70 { "arm,coresight-etm4x", 1 },
76 struct coresight_platform_data *pdata;
79 static struct resource_spec etm_spec[] = {
80 { SYS_RES_MEMORY, 0, RF_ACTIVE },
85 etm_prepare(device_t dev, struct coresight_event *event)
91 sc = device_get_softc(dev);
96 * Enable the return stack, global timestamping,
97 * Context ID, and Virtual context identifier tracing.
99 reg = TRCCONFIGR_RS | TRCCONFIGR_TS;
100 reg |= TRCCONFIGR_CID | TRCCONFIGR_VMID;
101 reg |= TRCCONFIGR_INSTP0_LDRSTR;
102 reg |= TRCCONFIGR_COND_ALL;
103 bus_write_4(sc->res, TRCCONFIGR, reg);
105 /* Disable all event tracing. */
106 bus_write_4(sc->res, TRCEVENTCTL0R, 0);
107 bus_write_4(sc->res, TRCEVENTCTL1R, 0);
109 /* Disable stalling, if implemented. */
110 bus_write_4(sc->res, TRCSTALLCTLR, 0);
112 /* Enable trace synchronization every 4096 bytes of trace. */
113 bus_write_4(sc->res, TRCSYNCPR, TRCSYNCPR_4K);
115 /* Set a value for the trace ID */
116 bus_write_4(sc->res, TRCTRACEIDR, event->etm.trace_id);
119 * Disable the timestamp event. The trace unit still generates
120 * timestamps due to other reasons such as trace synchronization.
122 bus_write_4(sc->res, TRCTSCTLR, 0);
125 * Enable ViewInst to trace everything, with the start/stop
128 reg = TRCVICTLR_SSSTATUS;
130 /* The number of the single resource used to activate the event. */
131 reg |= (1 << EVENT_SEL_S);
133 if (event->excp_level > 2)
136 reg |= TRCVICTLR_EXLEVEL_NS_M;
137 reg &= ~TRCVICTLR_EXLEVEL_NS(event->excp_level);
138 reg |= TRCVICTLR_EXLEVEL_S_M;
139 reg &= ~TRCVICTLR_EXLEVEL_S(event->excp_level);
140 bus_write_4(sc->res, TRCVICTLR, reg);
142 for (i = 0; i < event->naddr * 2; i++) {
143 dprintf("configure range %d, address %lx\n",
145 bus_write_8(sc->res, TRCACVR(i), event->addr[i]);
149 reg |= TRCACATR_EXLEVEL_S_M;
150 reg &= ~TRCACATR_EXLEVEL_S(event->excp_level);
151 /* Non-secure state */
152 reg |= TRCACATR_EXLEVEL_NS_M;
153 reg &= ~TRCACATR_EXLEVEL_NS(event->excp_level);
154 bus_write_4(sc->res, TRCACATR(i), reg);
156 /* Address range is included */
157 reg = bus_read_4(sc->res, TRCVIIECTLR);
158 reg |= (1 << (TRCVIIECTLR_INCLUDE_S + i / 2));
159 bus_write_4(sc->res, TRCVIIECTLR, reg);
162 /* No address filtering for ViewData. */
163 bus_write_4(sc->res, TRCVDARCCTLR, 0);
165 /* Clear the STATUS bit to zero */
166 bus_write_4(sc->res, TRCSSCSR(0), 0);
168 if (event->naddr == 0) {
169 /* No address range filtering for ViewInst. */
170 bus_write_4(sc->res, TRCVIIECTLR, 0);
173 /* No start or stop points for ViewInst. */
174 bus_write_4(sc->res, TRCVISSCTLR, 0);
176 /* Disable ViewData */
177 bus_write_4(sc->res, TRCVDCTLR, 0);
179 /* No address filtering for ViewData. */
180 bus_write_4(sc->res, TRCVDSACCTLR, 0);
186 etm_init(device_t dev)
188 struct etm_softc *sc;
191 sc = device_get_softc(dev);
193 /* Unlocking Coresight */
194 bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK);
197 bus_write_4(sc->res, TRCOSLAR, 0);
199 reg = bus_read_4(sc->res, TRCIDR(1));
200 dprintf("ETM Version: %d.%d\n",
201 (reg & TRCIDR1_TRCARCHMAJ_M) >> TRCIDR1_TRCARCHMAJ_S,
202 (reg & TRCIDR1_TRCARCHMIN_M) >> TRCIDR1_TRCARCHMIN_S);
208 etm_enable(device_t dev, struct endpoint *endp,
209 struct coresight_event *event)
211 struct etm_softc *sc;
214 sc = device_get_softc(dev);
216 etm_prepare(dev, event);
218 /* Enable the trace unit */
219 bus_write_4(sc->res, TRCPRGCTLR, TRCPRGCTLR_EN);
221 /* Wait for an IDLE bit to be LOW */
223 reg = bus_read_4(sc->res, TRCSTATR);
224 } while ((reg & TRCSTATR_IDLE) == 1);
226 if ((bus_read_4(sc->res, TRCPRGCTLR) & TRCPRGCTLR_EN) == 0)
227 panic("etm is not enabled\n");
233 etm_disable(device_t dev, struct endpoint *endp,
234 struct coresight_event *event)
236 struct etm_softc *sc;
239 sc = device_get_softc(dev);
241 /* Disable the trace unit */
242 bus_write_4(sc->res, TRCPRGCTLR, 0);
244 /* Wait for an IDLE bit */
246 reg = bus_read_4(sc->res, TRCSTATR);
247 } while ((reg & TRCSTATR_IDLE) == 0);
251 etm_probe(device_t dev)
253 if (!ofw_bus_status_okay(dev))
256 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
259 device_set_desc(dev, "AArch64 Embedded Trace Macrocell");
261 return (BUS_PROBE_DEFAULT);
265 etm_attach(device_t dev)
267 struct coresight_desc desc;
268 struct etm_softc *sc;
270 sc = device_get_softc(dev);
272 if (bus_alloc_resources(dev, etm_spec, &sc->res) != 0) {
273 device_printf(dev, "cannot allocate resources for device\n");
277 sc->pdata = coresight_get_platform_data(dev);
278 desc.pdata = sc->pdata;
280 desc.dev_type = CORESIGHT_ETMV4;
281 coresight_register(&desc);
286 static device_method_t etm_methods[] = {
287 /* Device interface */
288 DEVMETHOD(device_probe, etm_probe),
289 DEVMETHOD(device_attach, etm_attach),
291 /* Coresight interface */
292 DEVMETHOD(coresight_init, etm_init),
293 DEVMETHOD(coresight_enable, etm_enable),
294 DEVMETHOD(coresight_disable, etm_disable),
298 static driver_t etm_driver = {
301 sizeof(struct etm_softc),
304 static devclass_t etm_devclass;
306 DRIVER_MODULE(etm, simplebus, etm_driver, etm_devclass, 0, 0);
307 MODULE_VERSION(etm, 1);