2 * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <machine/bus.h>
42 #include <arm64/coresight/coresight.h>
43 #include <arm64/coresight/coresight-tmc.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
48 #include "coresight_if.h"
54 #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
56 #define dprintf(fmt, ...)
59 static struct ofw_compat_data compat_data[] = {
60 { "arm,coresight-tmc", 1 },
68 struct coresight_platform_data *pdata;
70 #define CORESIGHT_UNKNOWN 0
71 #define CORESIGHT_ETR 1
72 #define CORESIGHT_ETF 2
74 struct coresight_event *event;
75 boolean_t etf_configured;
78 static struct resource_spec tmc_spec[] = {
79 { SYS_RES_MEMORY, 0, RF_ACTIVE },
84 tmc_start(device_t dev)
89 sc = device_get_softc(dev);
91 if (bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN)
95 bus_write_4(sc->res, TMC_CTL, CTL_TRACECAPTEN);
96 if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0)
97 panic("Not enabled\n");
100 reg = bus_read_4(sc->res, TMC_STS);
101 } while ((reg & STS_TMCREADY) == 1);
103 if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0)
104 panic("Not enabled\n");
110 tmc_stop(device_t dev)
112 struct tmc_softc *sc;
115 sc = device_get_softc(dev);
117 reg = bus_read_4(sc->res, TMC_CTL);
118 reg &= ~CTL_TRACECAPTEN;
119 bus_write_4(sc->res, TMC_CTL, reg);
122 reg = bus_read_4(sc->res, TMC_STS);
123 } while ((reg & STS_TMCREADY) == 1);
129 tmc_configure_etf(device_t dev)
131 struct tmc_softc *sc;
134 sc = device_get_softc(dev);
137 reg = bus_read_4(sc->res, TMC_STS);
138 } while ((reg & STS_TMCREADY) == 0);
140 bus_write_4(sc->res, TMC_MODE, MODE_HW_FIFO);
141 bus_write_4(sc->res, TMC_FFCR, FFCR_EN_FMT | FFCR_EN_TI);
145 dprintf("%s: STS %x, CTL %x, RSZ %x, RRP %x, RWP %x, "
146 "LBUFLEVEL %x, CBUFLEVEL %x\n", __func__,
147 bus_read_4(sc->res, TMC_STS),
148 bus_read_4(sc->res, TMC_CTL),
149 bus_read_4(sc->res, TMC_RSZ),
150 bus_read_4(sc->res, TMC_RRP),
151 bus_read_4(sc->res, TMC_RWP),
152 bus_read_4(sc->res, TMC_CBUFLEVEL),
153 bus_read_4(sc->res, TMC_LBUFLEVEL));
159 tmc_configure_etr(device_t dev, struct endpoint *endp,
160 struct coresight_event *event)
162 struct tmc_softc *sc;
165 sc = device_get_softc(dev);
170 reg = bus_read_4(sc->res, TMC_STS);
171 } while ((reg & STS_TMCREADY) == 0);
174 bus_write_4(sc->res, TMC_MODE, MODE_CIRCULAR_BUFFER);
176 reg = AXICTL_PROT_CTRL_BIT1;
177 reg |= AXICTL_WRBURSTLEN_16;
180 * SG operation is broken on DragonBoard 410c
181 * reg |= AXICTL_SG_MODE;
184 reg |= AXICTL_AXCACHE_OS;
185 bus_write_4(sc->res, TMC_AXICTL, reg);
187 reg = FFCR_EN_FMT | FFCR_EN_TI | FFCR_FON_FLIN |
188 FFCR_FON_TRIG_EVT | FFCR_TRIGON_TRIGIN;
189 bus_write_4(sc->res, TMC_FFCR, reg);
191 bus_write_4(sc->res, TMC_TRG, 8);
193 bus_write_4(sc->res, TMC_DBALO, event->etr.low);
194 bus_write_4(sc->res, TMC_DBAHI, event->etr.high);
195 bus_write_4(sc->res, TMC_RSZ, event->etr.bufsize / 4);
197 bus_write_4(sc->res, TMC_RRP, event->etr.low);
198 bus_write_4(sc->res, TMC_RWP, event->etr.low);
200 reg = bus_read_4(sc->res, TMC_STS);
202 bus_write_4(sc->res, TMC_STS, reg);
210 tmc_init(device_t dev)
212 struct tmc_softc *sc;
215 sc = device_get_softc(dev);
217 /* Unlock Coresight */
218 bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK);
221 bus_write_4(sc->res, TMC_LAR, CORESIGHT_UNLOCK);
223 reg = bus_read_4(sc->res, TMC_DEVID);
224 reg &= DEVID_CONFIGTYPE_M;
226 case DEVID_CONFIGTYPE_ETR:
227 sc->dev_type = CORESIGHT_ETR;
228 dprintf(dev, "ETR configuration found\n");
230 case DEVID_CONFIGTYPE_ETF:
231 sc->dev_type = CORESIGHT_ETF;
232 dprintf(dev, "ETF configuration found\n");
233 if (sc->etf_configured == false) {
234 tmc_configure_etf(dev);
235 sc->etf_configured = true;
239 sc->dev_type = CORESIGHT_UNKNOWN;
247 tmc_enable(device_t dev, struct endpoint *endp,
248 struct coresight_event *event)
250 struct tmc_softc *sc;
253 sc = device_get_softc(dev);
255 if (sc->dev_type == CORESIGHT_ETF)
258 KASSERT(sc->dev_type == CORESIGHT_ETR,
262 * Multiple CPUs can call this same time.
263 * We allow only one running configuration.
266 if (event->etr.flags & ETR_FLAG_ALLOCATE) {
267 event->etr.flags &= ~ETR_FLAG_ALLOCATE;
268 nev = atomic_fetchadd_int(&sc->nev, 1);
272 tmc_configure_etr(dev, endp, event);
281 tmc_disable(device_t dev, struct endpoint *endp,
282 struct coresight_event *event)
284 struct tmc_softc *sc;
287 sc = device_get_softc(dev);
289 /* ETF configuration is static */
290 if (sc->dev_type == CORESIGHT_ETF)
293 KASSERT(sc->dev_type == CORESIGHT_ETR, ("Wrong dev_type"));
295 if (event->etr.flags & ETR_FLAG_RELEASE) {
296 event->etr.flags &= ~ETR_FLAG_RELEASE;
297 nev = atomic_fetchadd_int(&sc->nev, -1);
306 tmc_read(device_t dev, struct endpoint *endp,
307 struct coresight_event *event)
309 struct tmc_softc *sc;
312 sc = device_get_softc(dev);
314 if (sc->dev_type == CORESIGHT_ETF)
318 * Ensure the event we are reading information for
319 * is currently configured one.
321 if (sc->event != event)
324 if (bus_read_4(sc->res, TMC_STS) & STS_FULL) {
325 event->etr.offset = 0;
330 cur_ptr = bus_read_4(sc->res, TMC_RWP);
331 event->etr.offset = (cur_ptr - event->etr.low);
338 tmc_probe(device_t dev)
341 if (!ofw_bus_status_okay(dev))
344 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
347 device_set_desc(dev, "Coresight Trace Memory Controller (TMC)");
349 return (BUS_PROBE_DEFAULT);
353 tmc_attach(device_t dev)
355 struct coresight_desc desc;
356 struct tmc_softc *sc;
358 sc = device_get_softc(dev);
362 if (bus_alloc_resources(dev, tmc_spec, &sc->res) != 0) {
363 device_printf(dev, "cannot allocate resources for device\n");
367 sc->pdata = coresight_get_platform_data(dev);
368 desc.pdata = sc->pdata;
370 desc.dev_type = CORESIGHT_TMC;
371 coresight_register(&desc);
376 static device_method_t tmc_methods[] = {
377 /* Device interface */
378 DEVMETHOD(device_probe, tmc_probe),
379 DEVMETHOD(device_attach, tmc_attach),
381 /* Coresight interface */
382 DEVMETHOD(coresight_init, tmc_init),
383 DEVMETHOD(coresight_enable, tmc_enable),
384 DEVMETHOD(coresight_disable, tmc_disable),
385 DEVMETHOD(coresight_read, tmc_read),
389 static driver_t tmc_driver = {
392 sizeof(struct tmc_softc),
395 static devclass_t tmc_devclass;
397 DRIVER_MODULE(tmc, simplebus, tmc_driver, tmc_devclass, 0, 0);
398 MODULE_VERSION(tmc, 1);