2 * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef _ARM64_CORESIGHT_CORESIGHT_H_
34 #define _ARM64_CORESIGHT_CORESIGHT_H_
36 #include <dev/ofw/openfirm.h>
38 #define CORESIGHT_ITCTRL 0xf00
39 #define CORESIGHT_CLAIMSET 0xfa0
40 #define CORESIGHT_CLAIMCLR 0xfa4
41 #define CORESIGHT_LAR 0xfb0
42 #define CORESIGHT_UNLOCK 0xc5acce55
43 #define CORESIGHT_LSR 0xfb4
44 #define CORESIGHT_AUTHSTATUS 0xfb8
45 #define CORESIGHT_DEVID 0xfc8
46 #define CORESIGHT_DEVTYPE 0xfcc
51 CORESIGHT_DYNAMIC_REPLICATOR,
56 struct coresight_device {
57 TAILQ_ENTRY(coresight_device) link;
60 enum cs_dev_type dev_type;
61 struct coresight_platform_data *pdata;
65 TAILQ_ENTRY(endpoint) link;
71 struct coresight_device *cs_dev;
72 LIST_ENTRY(endpoint) endplink;
75 struct coresight_platform_data {
80 TAILQ_HEAD(endpoint_list, endpoint) endpoints;
83 struct coresight_desc {
84 struct coresight_platform_data *pdata;
86 enum cs_dev_type dev_type;
89 TAILQ_HEAD(coresight_device_list, coresight_device);
91 #define ETM_N_COMPRATOR 16
105 #define ETR_FLAG_ALLOCATE (1 << 0)
106 #define ETR_FLAG_RELEASE (1 << 1)
109 struct coresight_event {
110 LIST_HEAD(, endpoint) endplist;
112 uint64_t addr[ETM_N_COMPRATOR];
115 enum cs_dev_type src;
116 enum cs_dev_type sink;
118 struct etr_state etr;
119 struct etm_state etm;
123 uint64_t addr[ETM_N_COMPRATOR];
128 struct coresight_platform_data * coresight_get_platform_data(device_t dev);
129 struct endpoint * coresight_get_output_endpoint(struct coresight_platform_data *pdata);
130 struct coresight_device * coresight_get_output_device(struct endpoint *endp, struct endpoint **);
131 int coresight_register(struct coresight_desc *desc);
132 int coresight_init_event(int cpu, struct coresight_event *event);
133 void coresight_enable(int cpu, struct coresight_event *event);
134 void coresight_disable(int cpu, struct coresight_event *event);
135 void coresight_read(int cpu, struct coresight_event *event);
137 #endif /* !_ARM64_CORESIGHT_CORESIGHT_H_ */