2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef _ARM64_CORESIGHT_CORESIGHT_TMC_H_
34 #define _ARM64_CORESIGHT_CORESIGHT_TMC_H_
36 #define TMC_RSZ 0x004 /* RAM Size Register */
37 #define TMC_STS 0x00C /* Status Register */
38 #define STS_MEMERR (1 << 5)
39 #define STS_EMPTY (1 << 4)
40 #define STS_FTEMPTY (1 << 3)
41 #define STS_TMCREADY (1 << 2)
42 #define STS_TRIGGERED (1 << 1)
43 #define STS_FULL (1 << 0)
44 #define TMC_RRD 0x010 /* RAM Read Data Register */
45 #define TMC_RRP 0x014 /* RAM Read Pointer Register */
46 #define TMC_RWP 0x018 /* RAM Write Pointer Register */
47 #define TMC_TRG 0x01C /* Trigger Counter Register */
48 #define TMC_CTL 0x020 /* Control Register */
49 #define CTL_TRACECAPTEN (1 << 0) /* Controls trace capture. */
50 #define TMC_RWD 0x024 /* RAM Write Data Register */
51 #define TMC_MODE 0x028 /* Mode Register */
52 #define MODE_HW_FIFO 2
53 #define MODE_SW_FIFO 1
54 #define MODE_CIRCULAR_BUFFER 0
55 #define TMC_LBUFLEVEL 0x02C /* Latched Buffer Fill Level */
56 #define TMC_CBUFLEVEL 0x030 /* Current Buffer Fill Level */
57 #define TMC_BUFWM 0x034 /* Buffer Level Water Mark */
58 #define TMC_RRPHI 0x038 /* RAM Read Pointer High Register */
59 #define TMC_RWPHI 0x03C /* RAM Write Pointer High Register */
60 #define TMC_AXICTL 0x110 /* AXI Control Register */
61 #define AXICTL_WRBURSTLEN_S 8
62 #define AXICTL_WRBURSTLEN_M (0xf << AXICTL_WRBURSTLEN_S)
63 #define AXICTL_WRBURSTLEN_16 (0xf << AXICTL_WRBURSTLEN_S)
64 #define AXICTL_SG_MODE (1 << 7) /* Scatter Gather Mode */
65 #define AXICTL_CACHE_CTRL_BIT3 (1 << 5)
66 #define AXICTL_CACHE_CTRL_BIT2 (1 << 4)
67 #define AXICTL_CACHE_CTRL_BIT1 (1 << 3)
68 #define AXICTL_CACHE_CTRL_BIT0 (1 << 2)
69 #define AXICTL_AXCACHE_OS (0xf << 2)
70 #define AXICTL_PROT_CTRL_BIT1 (1 << 1)
71 #define AXICTL_PROT_CTRL_BIT0 (1 << 0)
72 #define TMC_DBALO 0x118 /* Data Buffer Address Low Register */
73 #define TMC_DBAHI 0x11C /* Data Buffer Address High Register */
74 #define TMC_FFSR 0x300 /* Formatter and Flush Status Register */
75 #define TMC_FFCR 0x304 /* Formatter and Flush Control Register */
76 #define FFCR_EN_FMT (1 << 0)
77 #define FFCR_EN_TI (1 << 1)
78 #define FFCR_FON_FLIN (1 << 4)
79 #define FFCR_FON_TRIG_EVT (1 << 5)
80 #define FFCR_FLUSH_MAN (1 << 6)
81 #define FFCR_TRIGON_TRIGIN (1 << 8)
82 #define TMC_PSCR 0x308 /* Periodic Synchronization Counter Register */
83 #define TMC_ITATBMDATA0 0xED0 /* Integration Test ATB Master Data Register 0 */
84 #define TMC_ITATBMCTR2 0xED4 /* Integration Test ATB Master Interface Control 2 Register */
85 #define TMC_ITATBMCTR1 0xED8 /* Integration Test ATB Master Control Register 1 */
86 #define TMC_ITATBMCTR0 0xEDC /* Integration Test ATB Master Interface Control 0 Register */
87 #define TMC_ITMISCOP0 0xEE0 /* Integration Test Miscellaneous Output Register 0 */
88 #define TMC_ITTRFLIN 0xEE8 /* Integration Test Trigger In and Flush In Register */
89 #define TMC_ITATBDATA0 0xEEC /* Integration Test ATB Data Register 0 */
90 #define TMC_ITATBCTR2 0xEF0 /* Integration Test ATB Control 2 Register */
91 #define TMC_ITATBCTR1 0xEF4 /* Integration Test ATB Control 1 Register */
92 #define TMC_ITATBCTR0 0xEF8 /* Integration Test ATB Control 0 Register */
93 #define TMC_ITCTRL 0xF00 /* Integration Mode Control Register */
94 #define TMC_CLAIMSET 0xFA0 /* Claim Tag Set Register */
95 #define TMC_CLAIMCLR 0xFA4 /* Claim Tag Clear Register */
96 #define TMC_LAR 0xFB0 /* Lock Access Register */
97 #define TMC_LSR 0xFB4 /* Lock Status Register */
98 #define TMC_AUTHSTATUS 0xFB8 /* Authentication Status Register */
99 #define TMC_DEVID 0xFC8 /* Device Configuration Register */
100 #define DEVID_CONFIGTYPE_S 6
101 #define DEVID_CONFIGTYPE_M (0x3 << DEVID_CONFIGTYPE_S)
102 #define DEVID_CONFIGTYPE_ETB (0 << DEVID_CONFIGTYPE_S)
103 #define DEVID_CONFIGTYPE_ETR (1 << DEVID_CONFIGTYPE_S)
104 #define DEVID_CONFIGTYPE_ETF (2 << DEVID_CONFIGTYPE_S)
105 #define TMC_DEVTYPE 0xFCC /* Device Type Identifier Register */
106 #define TMC_PERIPHID4 0xFD0 /* Peripheral ID4 Register */
107 #define TMC_PERIPHID5 0xFD4 /* Peripheral ID5 Register */
108 #define TMC_PERIPHID6 0xFD8 /* Peripheral ID6 Register */
109 #define TMC_PERIPHID7 0xFDC /* Peripheral ID7 Register */
110 #define TMC_PERIPHID0 0xFE0 /* Peripheral ID0 Register */
111 #define TMC_PERIPHID1 0xFE4 /* Peripheral ID1 Register */
112 #define TMC_PERIPHID2 0xFE8 /* Peripheral ID2 Register */
113 #define TMC_PERIPHID3 0xFEC /* Peripheral ID3 Register */
114 #define TMC_COMPID0 0xFF0 /* Component ID0 Register */
115 #define TMC_COMPID1 0xFF4 /* Component ID1 Register */
116 #define TMC_COMPID2 0xFF8 /* Component ID2 Register */
117 #define TMC_COMPID3 0xFFC /* Component ID3 Register */
119 DECLARE_CLASS(tmc_driver);
122 struct resource *res;
125 struct coresight_platform_data *pdata;
127 #define CORESIGHT_UNKNOWN 0
128 #define CORESIGHT_ETR 1
129 #define CORESIGHT_ETF 2
131 struct coresight_event *event;
132 boolean_t etf_configured;
135 int tmc_attach(device_t dev);
137 #endif /* !_ARM64_CORESIGHT_CORESIGHT_TMC_H_ */