sys/arm64/include/armreg.h

   1 /*-
   2  * Copyright (c) 2013, 2014 Andrew Turner
   3  * Copyright (c) 2015,2021 The FreeBSD Foundation
   4  *
   5  * Portions of this software were developed by Andrew Turner
   6  * under sponsorship from the FreeBSD Foundation.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * $FreeBSD$
  30  */
  31
  32 #ifndef _MACHINE_ARMREG_H_
  33 #define _MACHINE_ARMREG_H_
  34
  35 #define INSN_SIZE               4
  36
  37 #define MRS_MASK                        0xfff00000
  38 #define MRS_VALUE                       0xd5300000
  39 #define MRS_SPECIAL(insn)               ((insn) & 0x000fffe0)
  40 #define MRS_REGISTER(insn)              ((insn) & 0x0000001f)
  41 #define  MRS_Op0_SHIFT                  19
  42 #define  MRS_Op0_MASK                   0x00080000
  43 #define  MRS_Op1_SHIFT                  16
  44 #define  MRS_Op1_MASK                   0x00070000
  45 #define  MRS_CRn_SHIFT                  12
  46 #define  MRS_CRn_MASK                   0x0000f000
  47 #define  MRS_CRm_SHIFT                  8
  48 #define  MRS_CRm_MASK                   0x00000f00
  49 #define  MRS_Op2_SHIFT                  5
  50 #define  MRS_Op2_MASK                   0x000000e0
  51 #define  MRS_Rt_SHIFT                   0
  52 #define  MRS_Rt_MASK                    0x0000001f
  53 #define __MRS_REG(op0, op1, crn, crm, op2)                              \
  54     (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) |              \
  55      ((crn) << MRS_CRn_SHIFT) | ((crm) << MRS_CRm_SHIFT) |              \
  56      ((op2) << MRS_Op2_SHIFT))
  57 #define MRS_REG(reg)                                                    \
  58     __MRS_REG(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2)
  59
  60 #define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)                     \
  61     S##op0##_##op1##_C##crn##_C##crm##_##op2
  62 #define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)                      \
  63     __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)
  64 #define MRS_REG_ALT_NAME(reg)                                           \
  65     _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2)
  66
  67
  68 #define READ_SPECIALREG(reg)                                            \
  69 ({      uint64_t _val;                                                  \
  70         __asm __volatile("mrs   %0, " __STRING(reg) : "=&r" (_val));    \
  71         _val;                                                           \
  72 })
  73 #define WRITE_SPECIALREG(reg, _val)                                     \
  74         __asm __volatile("msr   " __STRING(reg) ", %0" : : "r"((uint64_t)_val))
  75
  76 #define UL(x)   UINT64_C(x)
  77
  78 /* CCSIDR_EL1 - Cache Size ID Register */
  79 #define CCSIDR_NumSets_MASK     0x0FFFE000
  80 #define CCSIDR_NumSets64_MASK   0x00FFFFFF00000000
  81 #define CCSIDR_NumSets_SHIFT    13
  82 #define CCSIDR_NumSets64_SHIFT  32
  83 #define CCSIDR_Assoc_MASK       0x00001FF8
  84 #define CCSIDR_Assoc64_MASK     0x0000000000FFFFF8
  85 #define CCSIDR_Assoc_SHIFT      3
  86 #define CCSIDR_Assoc64_SHIFT    3
  87 #define CCSIDR_LineSize_MASK    0x7
  88 #define CCSIDR_NSETS(idr)                                               \
  89         (((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT)
  90 #define CCSIDR_ASSOC(idr)                                               \
  91         (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT)
  92 #define CCSIDR_NSETS_64(idr)                                            \
  93         (((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT)
  94 #define CCSIDR_ASSOC_64(idr)                                            \
  95         (((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT)
  96
  97 /* CLIDR_EL1 - Cache level ID register */
  98 #define CLIDR_CTYPE_MASK        0x7     /* Cache type mask bits */
  99 #define CLIDR_CTYPE_IO          0x1     /* Instruction only */
 100 #define CLIDR_CTYPE_DO          0x2     /* Data only */
 101 #define CLIDR_CTYPE_ID          0x3     /* Split instruction and data */
 102 #define CLIDR_CTYPE_UNIFIED     0x4     /* Unified */
 103
 104 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
 105 #define CNTHCTL_EVNTI_MASK      (0xf << 4) /* Bit to trigger event stream */
 106 #define CNTHCTL_EVNTDIR         (1 << 3) /* Control transition trigger bit */
 107 #define CNTHCTL_EVNTEN          (1 << 2) /* Enable event stream */
 108 #define CNTHCTL_EL1PCEN         (1 << 1) /* Allow EL0/1 physical timer access */
 109 #define CNTHCTL_EL1PCTEN        (1 << 0) /*Allow EL0/1 physical counter access*/
 110
 111 /* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */
 112 #define CNTP_CTL_EL0            MRS_REG(CNTP_CTL_EL0)
 113 #define CNTP_CTL_EL0_op0        3
 114 #define CNTP_CTL_EL0_op1        3
 115 #define CNTP_CTL_EL0_CRn        14
 116 #define CNTP_CTL_EL0_CRm        2
 117 #define CNTP_CTL_EL0_op2        1
 118 #define CNTP_CTL_ENABLE         (1 << 0)
 119 #define CNTP_CTL_IMASK          (1 << 1)
 120 #define CNTP_CTL_ISTATUS        (1 << 2)
 121
 122 /* CNTP_CVAL_EL0 - Counter-timer Physical Timer CompareValue register */
 123 #define CNTP_CVAL_EL0           MRS_REG(CNTP_CVAL_EL0)
 124 #define CNTP_CVAL_EL0_op0       3
 125 #define CNTP_CVAL_EL0_op1       3
 126 #define CNTP_CVAL_EL0_CRn       14
 127 #define CNTP_CVAL_EL0_CRm       2
 128 #define CNTP_CVAL_EL0_op2       2
 129
 130 /* CNTP_TVAL_EL0 - Counter-timer Physical Timer TimerValue register */
 131 #define CNTP_TVAL_EL0           MRS_REG(CNTP_TVAL_EL0)
 132 #define CNTP_TVAL_EL0_op0       3
 133 #define CNTP_TVAL_EL0_op1       3
 134 #define CNTP_TVAL_EL0_CRn       14
 135 #define CNTP_TVAL_EL0_CRm       2
 136 #define CNTP_TVAL_EL0_op2       0
 137
 138 /* CNTPCT_EL0 - Counter-timer Physical Count register */
 139 #define CNTPCT_EL0              MRS_REG(CNTPCT_EL0)
 140 #define CNTPCT_EL0_op0          3
 141 #define CNTPCT_EL0_op1          3
 142 #define CNTPCT_EL0_CRn          14
 143 #define CNTPCT_EL0_CRm          0
 144 #define CNTPCT_EL0_op2          1
 145
 146 /* CPACR_EL1 */
 147 #define CPACR_ZEN_MASK          (0x3 << 16)
 148 #define  CPACR_ZEN_TRAP_ALL1    (0x0 << 16) /* Traps from EL0 and EL1 */
 149 #define  CPACR_ZEN_TRAP_EL0     (0x1 << 16) /* Traps from EL0 */
 150 #define  CPACR_ZEN_TRAP_ALL2    (0x2 << 16) /* Traps from EL0 and EL1 */
 151 #define  CPACR_ZEN_TRAP_NONE    (0x3 << 16) /* No traps */
 152 #define CPACR_FPEN_MASK         (0x3 << 20)
 153 #define  CPACR_FPEN_TRAP_ALL1   (0x0 << 20) /* Traps from EL0 and EL1 */
 154 #define  CPACR_FPEN_TRAP_EL0    (0x1 << 20) /* Traps from EL0 */
 155 #define  CPACR_FPEN_TRAP_ALL2   (0x2 << 20) /* Traps from EL0 and EL1 */
 156 #define  CPACR_FPEN_TRAP_NONE   (0x3 << 20) /* No traps */
 157 #define CPACR_TTA               (0x1 << 28)
 158
 159 /* CSSELR_EL1 - Cache size selection register */
 160 #define CSSELR_Level(i)         (i << 1)
 161 #define CSSELR_InD              0x00000001
 162
 163 /* CTR_EL0 - Cache Type Register */
 164 #define CTR_RES1                (1 << 31)
 165 #define CTR_TminLine_SHIFT      32
 166 #define CTR_TminLine_MASK       (UL(0x3f) << CTR_TminLine_SHIFT)
 167 #define CTR_TminLine_VAL(reg)   ((reg) & CTR_TminLine_MASK)
 168 #define CTR_DIC_SHIFT           29
 169 #define CTR_DIC_MASK            (0x1 << CTR_DIC_SHIFT)
 170 #define CTR_DIC_VAL(reg)        ((reg) & CTR_DIC_MASK)
 171 #define CTR_IDC_SHIFT           28
 172 #define CTR_IDC_MASK            (0x1 << CTR_IDC_SHIFT)
 173 #define CTR_IDC_VAL(reg)        ((reg) & CTR_IDC_MASK)
 174 #define CTR_CWG_SHIFT           24
 175 #define CTR_CWG_MASK            (0xf << CTR_CWG_SHIFT)
 176 #define CTR_CWG_VAL(reg)        ((reg) & CTR_CWG_MASK)
 177 #define CTR_CWG_SIZE(reg)       (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT))
 178 #define CTR_ERG_SHIFT           20
 179 #define CTR_ERG_MASK            (0xf << CTR_ERG_SHIFT)
 180 #define CTR_ERG_VAL(reg)        ((reg) & CTR_ERG_MASK)
 181 #define CTR_ERG_SIZE(reg)       (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT))
 182 #define CTR_DLINE_SHIFT         16
 183 #define CTR_DLINE_MASK          (0xf << CTR_DLINE_SHIFT)
 184 #define CTR_DLINE_VAL(reg)      ((reg) & CTR_DLINE_MASK)
 185 #define CTR_DLINE_SIZE(reg)     (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT))
 186 #define CTR_L1IP_SHIFT          14
 187 #define CTR_L1IP_MASK           (0x3 << CTR_L1IP_SHIFT)
 188 #define CTR_L1IP_VAL(reg)       ((reg) & CTR_L1IP_MASK)
 189 #define  CTR_L1IP_VPIPT         (0 << CTR_L1IP_SHIFT)
 190 #define  CTR_L1IP_AIVIVT        (1 << CTR_L1IP_SHIFT)
 191 #define  CTR_L1IP_VIPT          (2 << CTR_L1IP_SHIFT)
 192 #define  CTR_L1IP_PIPT          (3 << CTR_L1IP_SHIFT)
 193 #define CTR_ILINE_SHIFT         0
 194 #define CTR_ILINE_MASK          (0xf << CTR_ILINE_SHIFT)
 195 #define CTR_ILINE_VAL(reg)      ((reg) & CTR_ILINE_MASK)
 196 #define CTR_ILINE_SIZE(reg)     (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT))
 197
 198 /* DAIFSet/DAIFClear */
 199 #define DAIF_D                  (1 << 3)
 200 #define DAIF_A                  (1 << 2)
 201 #define DAIF_I                  (1 << 1)
 202 #define DAIF_F                  (1 << 0)
 203 #define DAIF_ALL                (DAIF_D | DAIF_A | DAIF_I | DAIF_F)
 204 #define DAIF_INTR               (DAIF_I)        /* All exceptions that pass */
 205                                                 /* through the intr framework */
 206
 207 /* DBGBCR<n>_EL1 - Debug Breakpoint Control Registers */
 208 #define DBGBCR_EL1_op0          2
 209 #define DBGBCR_EL1_op1          0
 210 #define DBGBCR_EL1_CRn          0
 211 /* DBGBCR_EL1_CRm indicates which watchpoint this register is for */
 212 #define DBGBCR_EL1_op2          5
 213 #define DBGBCR_EN               0x1
 214 #define DBGBCR_PMC_SHIFT        1
 215 #define DBGBCR_PMC              (0x3 << DBGBCR_PMC_SHIFT)
 216 #define  DBGBCR_PMC_EL1         (0x1 << DBGBCR_PMC_SHIFT)
 217 #define  DBGBCR_PMC_EL0         (0x2 << DBGBCR_PMC_SHIFT)
 218 #define DBGBCR_BAS_SHIFT        5
 219 #define DBGBCR_BAS              (0xf << DBGBCR_BAS_SHIFT)
 220 #define DBGBCR_HMC_SHIFT        13
 221 #define DBGBCR_HMC              (0x1 << DBGBCR_HMC_SHIFT)
 222 #define DBGBCR_SSC_SHIFT        14
 223 #define DBGBCR_SSC              (0x3 << DBGBCR_SSC_SHIFT)
 224 #define DBGBCR_LBN_SHIFT        16
 225 #define DBGBCR_LBN              (0xf << DBGBCR_LBN_SHIFT)
 226 #define DBGBCR_BT_SHIFT         20
 227 #define DBGBCR_BT               (0xf << DBGBCR_BT_SHIFT)
 228
 229 /* DBGBVR<n>_EL1 - Debug Breakpoint Value Registers */
 230 #define DBGBVR_EL1_op0          2
 231 #define DBGBVR_EL1_op1          0
 232 #define DBGBVR_EL1_CRn          0
 233 /* DBGBVR_EL1_CRm indicates which watchpoint this register is for */
 234 #define DBGBVR_EL1_op2          4
 235
 236 /* DBGWCR<n>_EL1 - Debug Watchpoint Control Registers */
 237 #define DBGWCR_EL1_op0          2
 238 #define DBGWCR_EL1_op1          0
 239 #define DBGWCR_EL1_CRn          0
 240 /* DBGWCR_EL1_CRm indicates which watchpoint this register is for */
 241 #define DBGWCR_EL1_op2          7
 242 #define DBGWCR_EN               0x1
 243 #define DBGWCR_PAC_SHIFT        1
 244 #define DBGWCR_PAC              (0x3 << DBGWCR_PAC_SHIFT)
 245 #define  DBGWCR_PAC_EL1         (0x1 << DBGWCR_PAC_SHIFT)
 246 #define  DBGWCR_PAC_EL0         (0x2 << DBGWCR_PAC_SHIFT)
 247 #define DBGWCR_LSC_SHIFT        3
 248 #define DBGWCR_LSC              (0x3 << DBGWCR_LSC_SHIFT)
 249 #define DBGWCR_BAS_SHIFT        5
 250 #define DBGWCR_BAS              (0xff << DBGWCR_BAS_SHIFT)
 251 #define DBGWCR_HMC_SHIFT        13
 252 #define DBGWCR_HMC              (0x1 << DBGWCR_HMC_SHIFT)
 253 #define DBGWCR_SSC_SHIFT        14
 254 #define DBGWCR_SSC              (0x3 << DBGWCR_SSC_SHIFT)
 255 #define DBGWCR_LBN_SHIFT        16
 256 #define DBGWCR_LBN              (0xf << DBGWCR_LBN_SHIFT)
 257 #define DBGWCR_WT_SHIFT         20
 258 #define DBGWCR_WT               (0x1 << DBGWCR_WT_SHIFT)
 259 #define DBGWCR_MASK_SHIFT       24
 260 #define DBGWCR_MASK             (0x1f << DBGWCR_MASK_SHIFT)
 261
 262 /* DBGWVR<n>_EL1 - Debug Watchpoint Value Registers */
 263 #define DBGWVR_EL1_op0          2
 264 #define DBGWVR_EL1_op1          0
 265 #define DBGWVR_EL1_CRn          0
 266 /* DBGWVR_EL1_CRm indicates which watchpoint this register is for */
 267 #define DBGWVR_EL1_op2          6
 268
 269 /* DCZID_EL0 - Data Cache Zero ID register */
 270 #define DCZID_DZP               (1 << 4) /* DC ZVA prohibited if non-0 */
 271 #define DCZID_BS_SHIFT          0
 272 #define DCZID_BS_MASK           (0xf << DCZID_BS_SHIFT)
 273 #define DCZID_BS_SIZE(reg)      (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
 274
 275 /* DBGAUTHSTATUS_EL1 */
 276 #define DBGAUTHSTATUS_EL1               MRS_REG(DBGAUTHSTATUS_EL1)
 277 #define DBGAUTHSTATUS_EL1_op0           2
 278 #define DBGAUTHSTATUS_EL1_op1           0
 279 #define DBGAUTHSTATUS_EL1_CRn           7
 280 #define DBGAUTHSTATUS_EL1_CRm           14
 281 #define DBGAUTHSTATUS_EL1_op2           6
 282
 283 /* DBGCLAIMCLR_EL1 */
 284 #define DBGCLAIMCLR_EL1                 MRS_REG(DBGCLAIMCLR_EL1)
 285 #define DBGCLAIMCLR_EL1_op0             2
 286 #define DBGCLAIMCLR_EL1_op1             0
 287 #define DBGCLAIMCLR_EL1_CRn             7
 288 #define DBGCLAIMCLR_EL1_CRm             9
 289 #define DBGCLAIMCLR_EL1_op2             6
 290
 291 /* DBGCLAIMSET_EL1 */
 292 #define DBGCLAIMSET_EL1                 MRS_REG(DBGCLAIMSET_EL1)
 293 #define DBGCLAIMSET_EL1_op0             2
 294 #define DBGCLAIMSET_EL1_op1             0
 295 #define DBGCLAIMSET_EL1_CRn             7
 296 #define DBGCLAIMSET_EL1_CRm             8
 297 #define DBGCLAIMSET_EL1_op2             6
 298
 299 /* DBGPRCR_EL1 */
 300 #define DBGPRCR_EL1                     MRS_REG(DBGPRCR_EL1)
 301 #define DBGPRCR_EL1_op0                 2
 302 #define DBGPRCR_EL1_op1                 0
 303 #define DBGPRCR_EL1_CRn                 1
 304 #define DBGPRCR_EL1_CRm                 4
 305 #define DBGPRCR_EL1_op2                 4
 306
 307 /* ESR_ELx */
 308 #define ESR_ELx_ISS_MASK        0x01ffffff
 309 #define  ISS_FP_TFV_SHIFT       23
 310 #define  ISS_FP_TFV             (0x01 << ISS_FP_TFV_SHIFT)
 311 #define  ISS_FP_IOF             0x01
 312 #define  ISS_FP_DZF             0x02
 313 #define  ISS_FP_OFF             0x04
 314 #define  ISS_FP_UFF             0x08
 315 #define  ISS_FP_IXF             0x10
 316 #define  ISS_FP_IDF             0x80
 317 #define  ISS_INSN_FnV           (0x01 << 10)
 318 #define  ISS_INSN_EA            (0x01 << 9)
 319 #define  ISS_INSN_S1PTW         (0x01 << 7)
 320 #define  ISS_INSN_IFSC_MASK     (0x1f << 0)
 321
 322 #define  ISS_MSR_DIR_SHIFT      0
 323 #define  ISS_MSR_DIR            (0x01 << ISS_MSR_DIR_SHIFT)
 324 #define  ISS_MSR_Rt_SHIFT       5
 325 #define  ISS_MSR_Rt_MASK        (0x1f << ISS_MSR_Rt_SHIFT)
 326 #define  ISS_MSR_Rt(x)          (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT)
 327 #define  ISS_MSR_CRm_SHIFT      1
 328 #define  ISS_MSR_CRm_MASK       (0xf << ISS_MSR_CRm_SHIFT)
 329 #define  ISS_MSR_CRm(x)         (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT)
 330 #define  ISS_MSR_CRn_SHIFT      10
 331 #define  ISS_MSR_CRn_MASK       (0xf << ISS_MSR_CRn_SHIFT)
 332 #define  ISS_MSR_CRn(x)         (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT)
 333 #define  ISS_MSR_OP1_SHIFT      14
 334 #define  ISS_MSR_OP1_MASK       (0x7 << ISS_MSR_OP1_SHIFT)
 335 #define  ISS_MSR_OP1(x)         (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT)
 336 #define  ISS_MSR_OP2_SHIFT      17
 337 #define  ISS_MSR_OP2_MASK       (0x7 << ISS_MSR_OP2_SHIFT)
 338 #define  ISS_MSR_OP2(x)         (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT)
 339 #define  ISS_MSR_OP0_SHIFT      20
 340 #define  ISS_MSR_OP0_MASK       (0x3 << ISS_MSR_OP0_SHIFT)
 341 #define  ISS_MSR_OP0(x)         (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT)
 342 #define  ISS_MSR_REG_MASK       \
 343     (ISS_MSR_OP0_MASK | ISS_MSR_OP2_MASK | ISS_MSR_OP1_MASK |   \
 344      ISS_MSR_CRn_MASK | ISS_MSR_CRm_MASK)
 345
 346 #define  ISS_DATA_ISV_SHIFT     24
 347 #define  ISS_DATA_ISV           (0x01 << ISS_DATA_ISV_SHIFT)
 348 #define  ISS_DATA_SAS_SHIFT     22
 349 #define  ISS_DATA_SAS_MASK      (0x03 << ISS_DATA_SAS_SHIFT)
 350 #define  ISS_DATA_SSE_SHIFT     21
 351 #define  ISS_DATA_SSE           (0x01 << ISS_DATA_SSE_SHIFT)
 352 #define  ISS_DATA_SRT_SHIFT     16
 353 #define  ISS_DATA_SRT_MASK      (0x1f << ISS_DATA_SRT_SHIFT)
 354 #define  ISS_DATA_SF            (0x01 << 15)
 355 #define  ISS_DATA_AR            (0x01 << 14)
 356 #define  ISS_DATA_FnV           (0x01 << 10)
 357 #define  ISS_DATA_EA            (0x01 << 9)
 358 #define  ISS_DATA_CM            (0x01 << 8)
 359 #define  ISS_DATA_S1PTW         (0x01 << 7)
 360 #define  ISS_DATA_WnR_SHIFT     6
 361 #define  ISS_DATA_WnR           (0x01 << ISS_DATA_WnR_SHIFT)
 362 #define  ISS_DATA_DFSC_MASK     (0x3f << 0)
 363 #define  ISS_DATA_DFSC_ASF_L0   (0x00 << 0)
 364 #define  ISS_DATA_DFSC_ASF_L1   (0x01 << 0)
 365 #define  ISS_DATA_DFSC_ASF_L2   (0x02 << 0)
 366 #define  ISS_DATA_DFSC_ASF_L3   (0x03 << 0)
 367 #define  ISS_DATA_DFSC_TF_L0    (0x04 << 0)
 368 #define  ISS_DATA_DFSC_TF_L1    (0x05 << 0)
 369 #define  ISS_DATA_DFSC_TF_L2    (0x06 << 0)
 370 #define  ISS_DATA_DFSC_TF_L3    (0x07 << 0)
 371 #define  ISS_DATA_DFSC_AFF_L1   (0x09 << 0)
 372 #define  ISS_DATA_DFSC_AFF_L2   (0x0a << 0)
 373 #define  ISS_DATA_DFSC_AFF_L3   (0x0b << 0)
 374 #define  ISS_DATA_DFSC_PF_L1    (0x0d << 0)
 375 #define  ISS_DATA_DFSC_PF_L2    (0x0e << 0)
 376 #define  ISS_DATA_DFSC_PF_L3    (0x0f << 0)
 377 #define  ISS_DATA_DFSC_EXT      (0x10 << 0)
 378 #define  ISS_DATA_DFSC_EXT_L0   (0x14 << 0)
 379 #define  ISS_DATA_DFSC_EXT_L1   (0x15 << 0)
 380 #define  ISS_DATA_DFSC_EXT_L2   (0x16 << 0)
 381 #define  ISS_DATA_DFSC_EXT_L3   (0x17 << 0)
 382 #define  ISS_DATA_DFSC_ECC      (0x18 << 0)
 383 #define  ISS_DATA_DFSC_ECC_L0   (0x1c << 0)
 384 #define  ISS_DATA_DFSC_ECC_L1   (0x1d << 0)
 385 #define  ISS_DATA_DFSC_ECC_L2   (0x1e << 0)
 386 #define  ISS_DATA_DFSC_ECC_L3   (0x1f << 0)
 387 #define  ISS_DATA_DFSC_ALIGN    (0x21 << 0)
 388 #define  ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0)
 389 #define ESR_ELx_IL              (0x01 << 25)
 390 #define ESR_ELx_EC_SHIFT        26
 391 #define ESR_ELx_EC_MASK         (0x3f << 26)
 392 #define ESR_ELx_EXCEPTION(esr)  (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
 393 #define  EXCP_UNKNOWN           0x00    /* Unkwn exception */
 394 #define  EXCP_TRAP_WFI_WFE      0x01    /* Trapped WFI or WFE */
 395 #define  EXCP_FP_SIMD           0x07    /* VFP/SIMD trap */
 396 #define  EXCP_ILL_STATE         0x0e    /* Illegal execution state */
 397 #define  EXCP_SVC32             0x11    /* SVC trap for AArch32 */
 398 #define  EXCP_SVC64             0x15    /* SVC trap for AArch64 */
 399 #define  EXCP_HVC               0x16    /* HVC trap */
 400 #define  EXCP_MSR               0x18    /* MSR/MRS trap */
 401 #define  EXCP_SVE               0x19    /* SVE trap */
 402 #define  EXCP_FPAC              0x1c    /* Faulting PAC trap */
 403 #define  EXCP_INSN_ABORT_L      0x20    /* Instruction abort, from lower EL */
 404 #define  EXCP_INSN_ABORT        0x21    /* Instruction abort, from same EL */
 405 #define  EXCP_PC_ALIGN          0x22    /* PC alignment fault */
 406 #define  EXCP_DATA_ABORT_L      0x24    /* Data abort, from lower EL */
 407 #define  EXCP_DATA_ABORT        0x25    /* Data abort, from same EL */
 408 #define  EXCP_SP_ALIGN          0x26    /* SP slignment fault */
 409 #define  EXCP_TRAP_FP           0x2c    /* Trapped FP exception */
 410 #define  EXCP_SERROR            0x2f    /* SError interrupt */
 411 #define  EXCP_BRKPT_EL0         0x30    /* Hardware breakpoint, from same EL */
 412 #define  EXCP_SOFTSTP_EL0       0x32    /* Software Step, from lower EL */
 413 #define  EXCP_SOFTSTP_EL1       0x33    /* Software Step, from same EL */
 414 #define  EXCP_WATCHPT_EL0       0x34    /* Watchpoint, from lower EL */
 415 #define  EXCP_WATCHPT_EL1       0x35    /* Watchpoint, from same EL */
 416 #define  EXCP_BRKPT_32          0x38    /* 32bits breakpoint */
 417 #define  EXCP_BRK               0x3c    /* Breakpoint */
 418
 419 /* ICC_CTLR_EL1 */
 420 #define ICC_CTLR_EL1_EOIMODE    (1U << 1)
 421
 422 /* ICC_IAR1_EL1 */
 423 #define ICC_IAR1_EL1_SPUR       (0x03ff)
 424
 425 /* ICC_IGRPEN0_EL1 */
 426 #define ICC_IGRPEN0_EL1_EN      (1U << 0)
 427
 428 /* ICC_PMR_EL1 */
 429 #define ICC_PMR_EL1_PRIO_MASK   (0xFFUL)
 430
 431 /* ICC_SGI1R_EL1 */
 432 #define ICC_SGI1R_EL1                   MRS_REG(ICC_SGI1R_EL1)
 433 #define ICC_SGI1R_EL1_op0               3
 434 #define ICC_SGI1R_EL1_op1               0
 435 #define ICC_SGI1R_EL1_CRn               12
 436 #define ICC_SGI1R_EL1_CRm               11
 437 #define ICC_SGI1R_EL1_op2               5
 438 #define ICC_SGI1R_EL1_TL_MASK           0xffffUL
 439 #define ICC_SGI1R_EL1_AFF1_SHIFT        16
 440 #define ICC_SGI1R_EL1_SGIID_SHIFT       24
 441 #define ICC_SGI1R_EL1_AFF2_SHIFT        32
 442 #define ICC_SGI1R_EL1_AFF3_SHIFT        48
 443 #define ICC_SGI1R_EL1_SGIID_MASK        0xfUL
 444 #define ICC_SGI1R_EL1_IRM               (0x1UL << 40)
 445
 446 /* ICC_SRE_EL1 */
 447 #define ICC_SRE_EL1_SRE         (1U << 0)
 448
 449 /* ID_AA64DFR0_EL1 */
 450 #define ID_AA64DFR0_EL1                 MRS_REG(ID_AA64DFR0_EL1)
 451 #define ID_AA64DFR0_EL1_op0             0x3
 452 #define ID_AA64DFR0_EL1_op1             0x0
 453 #define ID_AA64DFR0_EL1_CRn             0x0
 454 #define ID_AA64DFR0_EL1_CRm             0x5
 455 #define ID_AA64DFR0_EL1_op2             0x0
 456 #define ID_AA64DFR0_DebugVer_SHIFT      0
 457 #define ID_AA64DFR0_DebugVer_MASK       (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)
 458 #define ID_AA64DFR0_DebugVer_VAL(x)     ((x) & ID_AA64DFR0_DebugVer_MASK)
 459 #define  ID_AA64DFR0_DebugVer_8         (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT)
 460 #define  ID_AA64DFR0_DebugVer_8_VHE     (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT)
 461 #define  ID_AA64DFR0_DebugVer_8_2       (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT)
 462 #define  ID_AA64DFR0_DebugVer_8_4       (UL(0x9) << ID_AA64DFR0_DebugVer_SHIFT)
 463 #define ID_AA64DFR0_TraceVer_SHIFT      4
 464 #define ID_AA64DFR0_TraceVer_MASK       (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT)
 465 #define ID_AA64DFR0_TraceVer_VAL(x)     ((x) & ID_AA64DFR0_TraceVer_MASK)
 466 #define  ID_AA64DFR0_TraceVer_NONE      (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT)
 467 #define  ID_AA64DFR0_TraceVer_IMPL      (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT)
 468 #define ID_AA64DFR0_PMUVer_SHIFT        8
 469 #define ID_AA64DFR0_PMUVer_MASK         (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
 470 #define ID_AA64DFR0_PMUVer_VAL(x)       ((x) & ID_AA64DFR0_PMUVer_MASK)
 471 #define  ID_AA64DFR0_PMUVer_NONE        (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT)
 472 #define  ID_AA64DFR0_PMUVer_3           (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT)
 473 #define  ID_AA64DFR0_PMUVer_3_1         (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT)
 474 #define  ID_AA64DFR0_PMUVer_3_4         (UL(0x5) << ID_AA64DFR0_PMUVer_SHIFT)
 475 #define  ID_AA64DFR0_PMUVer_3_5         (UL(0x6) << ID_AA64DFR0_PMUVer_SHIFT)
 476 #define  ID_AA64DFR0_PMUVer_IMPL        (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
 477 #define ID_AA64DFR0_BRPs_SHIFT          12
 478 #define ID_AA64DFR0_BRPs_MASK           (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT)
 479 #define ID_AA64DFR0_BRPs_VAL(x) \
 480     ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1)
 481 #define ID_AA64DFR0_WRPs_SHIFT          20
 482 #define ID_AA64DFR0_WRPs_MASK           (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT)
 483 #define ID_AA64DFR0_WRPs_VAL(x) \
 484     ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1)
 485 #define ID_AA64DFR0_CTX_CMPs_SHIFT      28
 486 #define ID_AA64DFR0_CTX_CMPs_MASK       (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT)
 487 #define ID_AA64DFR0_CTX_CMPs_VAL(x)     \
 488     ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1)
 489 #define ID_AA64DFR0_PMSVer_SHIFT        32
 490 #define ID_AA64DFR0_PMSVer_MASK         (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT)
 491 #define ID_AA64DFR0_PMSVer_VAL(x)       ((x) & ID_AA64DFR0_PMSVer_MASK)
 492 #define  ID_AA64DFR0_PMSVer_NONE        (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT)
 493 #define  ID_AA64DFR0_PMSVer_SPE         (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT)
 494 #define  ID_AA64DFR0_PMSVer_SPE_8_3     (UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT)
 495 #define ID_AA64DFR0_DoubleLock_SHIFT    36
 496 #define ID_AA64DFR0_DoubleLock_MASK     (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT)
 497 #define ID_AA64DFR0_DoubleLock_VAL(x)   ((x) & ID_AA64DFR0_DoubleLock_MASK)
 498 #define  ID_AA64DFR0_DoubleLock_IMPL    (UL(0x0) << ID_AA64DFR0_DoubleLock_SHIFT)
 499 #define  ID_AA64DFR0_DoubleLock_NONE    (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT)
 500 #define ID_AA64DFR0_TraceFilt_SHIFT     40
 501 #define ID_AA64DFR0_TraceFilt_MASK      (UL(0xf) << ID_AA64DFR0_TraceFilt_SHIFT)
 502 #define ID_AA64DFR0_TraceFilt_VAL(x)    ((x) & ID_AA64DFR0_TraceFilt_MASK)
 503 #define  ID_AA64DFR0_TraceFilt_NONE     (UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT)
 504 #define  ID_AA64DFR0_TraceFilt_8_4      (UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT)
 505
 506 /* ID_AA64ISAR0_EL1 */
 507 #define ID_AA64ISAR0_EL1                MRS_REG(ID_AA64ISAR0_EL1)
 508 #define ID_AA64ISAR0_EL1_op0            0x3
 509 #define ID_AA64ISAR0_EL1_op1            0x0
 510 #define ID_AA64ISAR0_EL1_CRn            0x0
 511 #define ID_AA64ISAR0_EL1_CRm            0x6
 512 #define ID_AA64ISAR0_EL1_op2            0x0
 513 #define ID_AA64ISAR0_AES_SHIFT          4
 514 #define ID_AA64ISAR0_AES_MASK           (UL(0xf) << ID_AA64ISAR0_AES_SHIFT)
 515 #define ID_AA64ISAR0_AES_VAL(x)         ((x) & ID_AA64ISAR0_AES_MASK)
 516 #define  ID_AA64ISAR0_AES_NONE          (UL(0x0) << ID_AA64ISAR0_AES_SHIFT)
 517 #define  ID_AA64ISAR0_AES_BASE          (UL(0x1) << ID_AA64ISAR0_AES_SHIFT)
 518 #define  ID_AA64ISAR0_AES_PMULL         (UL(0x2) << ID_AA64ISAR0_AES_SHIFT)
 519 #define ID_AA64ISAR0_SHA1_SHIFT         8
 520 #define ID_AA64ISAR0_SHA1_MASK          (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT)
 521 #define ID_AA64ISAR0_SHA1_VAL(x)        ((x) & ID_AA64ISAR0_SHA1_MASK)
 522 #define  ID_AA64ISAR0_SHA1_NONE         (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT)
 523 #define  ID_AA64ISAR0_SHA1_BASE         (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT)
 524 #define ID_AA64ISAR0_SHA2_SHIFT         12
 525 #define ID_AA64ISAR0_SHA2_MASK          (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT)
 526 #define ID_AA64ISAR0_SHA2_VAL(x)        ((x) & ID_AA64ISAR0_SHA2_MASK)
 527 #define  ID_AA64ISAR0_SHA2_NONE         (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT)
 528 #define  ID_AA64ISAR0_SHA2_BASE         (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT)
 529 #define  ID_AA64ISAR0_SHA2_512          (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT)
 530 #define ID_AA64ISAR0_CRC32_SHIFT        16
 531 #define ID_AA64ISAR0_CRC32_MASK         (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT)
 532 #define ID_AA64ISAR0_CRC32_VAL(x)       ((x) & ID_AA64ISAR0_CRC32_MASK)
 533 #define  ID_AA64ISAR0_CRC32_NONE        (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT)
 534 #define  ID_AA64ISAR0_CRC32_BASE        (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT)
 535 #define ID_AA64ISAR0_Atomic_SHIFT       20
 536 #define ID_AA64ISAR0_Atomic_MASK        (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT)
 537 #define ID_AA64ISAR0_Atomic_VAL(x)      ((x) & ID_AA64ISAR0_Atomic_MASK)
 538 #define  ID_AA64ISAR0_Atomic_NONE       (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT)
 539 #define  ID_AA64ISAR0_Atomic_IMPL       (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT)
 540 #define ID_AA64ISAR0_RDM_SHIFT          28
 541 #define ID_AA64ISAR0_RDM_MASK           (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT)
 542 #define ID_AA64ISAR0_RDM_VAL(x)         ((x) & ID_AA64ISAR0_RDM_MASK)
 543 #define  ID_AA64ISAR0_RDM_NONE          (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT)
 544 #define  ID_AA64ISAR0_RDM_IMPL          (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT)
 545 #define ID_AA64ISAR0_SHA3_SHIFT         32
 546 #define ID_AA64ISAR0_SHA3_MASK          (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT)
 547 #define ID_AA64ISAR0_SHA3_VAL(x)        ((x) & ID_AA64ISAR0_SHA3_MASK)
 548 #define  ID_AA64ISAR0_SHA3_NONE         (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT)
 549 #define  ID_AA64ISAR0_SHA3_IMPL         (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT)
 550 #define ID_AA64ISAR0_SM3_SHIFT          36
 551 #define ID_AA64ISAR0_SM3_MASK           (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT)
 552 #define ID_AA64ISAR0_SM3_VAL(x)         ((x) & ID_AA64ISAR0_SM3_MASK)
 553 #define  ID_AA64ISAR0_SM3_NONE          (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT)
 554 #define  ID_AA64ISAR0_SM3_IMPL          (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT)
 555 #define ID_AA64ISAR0_SM4_SHIFT          40
 556 #define ID_AA64ISAR0_SM4_MASK           (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT)
 557 #define ID_AA64ISAR0_SM4_VAL(x)         ((x) & ID_AA64ISAR0_SM4_MASK)
 558 #define  ID_AA64ISAR0_SM4_NONE          (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT)
 559 #define  ID_AA64ISAR0_SM4_IMPL          (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT)
 560 #define ID_AA64ISAR0_DP_SHIFT           44
 561 #define ID_AA64ISAR0_DP_MASK            (UL(0xf) << ID_AA64ISAR0_DP_SHIFT)
 562 #define ID_AA64ISAR0_DP_VAL(x)          ((x) & ID_AA64ISAR0_DP_MASK)
 563 #define  ID_AA64ISAR0_DP_NONE           (UL(0x0) << ID_AA64ISAR0_DP_SHIFT)
 564 #define  ID_AA64ISAR0_DP_IMPL           (UL(0x1) << ID_AA64ISAR0_DP_SHIFT)
 565 #define ID_AA64ISAR0_FHM_SHIFT          48
 566 #define ID_AA64ISAR0_FHM_MASK           (UL(0xf) << ID_AA64ISAR0_FHM_SHIFT)
 567 #define ID_AA64ISAR0_FHM_VAL(x)         ((x) & ID_AA64ISAR0_FHM_MASK)
 568 #define  ID_AA64ISAR0_FHM_NONE          (UL(0x0) << ID_AA64ISAR0_FHM_SHIFT)
 569 #define  ID_AA64ISAR0_FHM_IMPL          (UL(0x1) << ID_AA64ISAR0_FHM_SHIFT)
 570 #define ID_AA64ISAR0_TS_SHIFT           52
 571 #define ID_AA64ISAR0_TS_MASK            (UL(0xf) << ID_AA64ISAR0_TS_SHIFT)
 572 #define ID_AA64ISAR0_TS_VAL(x)          ((x) & ID_AA64ISAR0_TS_MASK)
 573 #define  ID_AA64ISAR0_TS_NONE           (UL(0x0) << ID_AA64ISAR0_TS_SHIFT)
 574 #define  ID_AA64ISAR0_TS_CondM_8_4      (UL(0x1) << ID_AA64ISAR0_TS_SHIFT)
 575 #define  ID_AA64ISAR0_TS_CondM_8_5      (UL(0x2) << ID_AA64ISAR0_TS_SHIFT)
 576 #define ID_AA64ISAR0_TLB_SHIFT          56
 577 #define ID_AA64ISAR0_TLB_MASK           (UL(0xf) << ID_AA64ISAR0_TLB_SHIFT)
 578 #define ID_AA64ISAR0_TLB_VAL(x)         ((x) & ID_AA64ISAR0_TLB_MASK)
 579 #define  ID_AA64ISAR0_TLB_NONE          (UL(0x0) << ID_AA64ISAR0_TLB_SHIFT)
 580 #define  ID_AA64ISAR0_TLB_TLBIOS        (UL(0x1) << ID_AA64ISAR0_TLB_SHIFT)
 581 #define  ID_AA64ISAR0_TLB_TLBIOSR       (UL(0x2) << ID_AA64ISAR0_TLB_SHIFT)
 582 #define ID_AA64ISAR0_RNDR_SHIFT         60
 583 #define ID_AA64ISAR0_RNDR_MASK          (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT)
 584 #define ID_AA64ISAR0_RNDR_VAL(x)        ((x) & ID_AA64ISAR0_RNDR_MASK)
 585 #define  ID_AA64ISAR0_RNDR_NONE         (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT)
 586 #define  ID_AA64ISAR0_RNDR_IMPL         (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT)
 587
 588 /* ID_AA64ISAR1_EL1 */
 589 #define ID_AA64ISAR1_EL1                MRS_REG(ID_AA64ISAR1_EL1)
 590 #define ID_AA64ISAR1_EL1_op0            0x3
 591 #define ID_AA64ISAR1_EL1_op1            0x0
 592 #define ID_AA64ISAR1_EL1_CRn            0x0
 593 #define ID_AA64ISAR1_EL1_CRm            0x6
 594 #define ID_AA64ISAR1_EL1_op2            0x1
 595 #define ID_AA64ISAR1_DPB_SHIFT          0
 596 #define ID_AA64ISAR1_DPB_MASK           (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
 597 #define ID_AA64ISAR1_DPB_VAL(x)         ((x) & ID_AA64ISAR1_DPB_MASK)
 598 #define  ID_AA64ISAR1_DPB_NONE          (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT)
 599 #define  ID_AA64ISAR1_DPB_DCCVAP        (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT)
 600 #define  ID_AA64ISAR1_DPB_DCCVADP       (UL(0x2) << ID_AA64ISAR1_DPB_SHIFT)
 601 #define ID_AA64ISAR1_APA_SHIFT          4
 602 #define ID_AA64ISAR1_APA_MASK           (UL(0xf) << ID_AA64ISAR1_APA_SHIFT)
 603 #define ID_AA64ISAR1_APA_VAL(x)         ((x) & ID_AA64ISAR1_APA_MASK)
 604 #define  ID_AA64ISAR1_APA_NONE          (UL(0x0) << ID_AA64ISAR1_APA_SHIFT)
 605 #define  ID_AA64ISAR1_APA_PAC           (UL(0x1) << ID_AA64ISAR1_APA_SHIFT)
 606 #define  ID_AA64ISAR1_APA_EPAC          (UL(0x2) << ID_AA64ISAR1_APA_SHIFT)
 607 #define  ID_AA64ISAR1_APA_EPAC2         (UL(0x3) << ID_AA64ISAR1_APA_SHIFT)
 608 #define  ID_AA64ISAR1_APA_FPAC          (UL(0x4) << ID_AA64ISAR1_APA_SHIFT)
 609 #define  ID_AA64ISAR1_APA_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_APA_SHIFT)
 610 #define ID_AA64ISAR1_API_SHIFT          8
 611 #define ID_AA64ISAR1_API_MASK           (UL(0xf) << ID_AA64ISAR1_API_SHIFT)
 612 #define ID_AA64ISAR1_API_VAL(x)         ((x) & ID_AA64ISAR1_API_MASK)
 613 #define  ID_AA64ISAR1_API_NONE          (UL(0x0) << ID_AA64ISAR1_API_SHIFT)
 614 #define  ID_AA64ISAR1_API_PAC           (UL(0x1) << ID_AA64ISAR1_API_SHIFT)
 615 #define  ID_AA64ISAR1_API_EPAC          (UL(0x2) << ID_AA64ISAR1_API_SHIFT)
 616 #define  ID_AA64ISAR1_API_EPAC2         (UL(0x3) << ID_AA64ISAR1_API_SHIFT)
 617 #define  ID_AA64ISAR1_API_FPAC          (UL(0x4) << ID_AA64ISAR1_API_SHIFT)
 618 #define  ID_AA64ISAR1_API_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_API_SHIFT)
 619 #define ID_AA64ISAR1_JSCVT_SHIFT        12
 620 #define ID_AA64ISAR1_JSCVT_MASK         (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT)
 621 #define ID_AA64ISAR1_JSCVT_VAL(x)       ((x) & ID_AA64ISAR1_JSCVT_MASK)
 622 #define  ID_AA64ISAR1_JSCVT_NONE        (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT)
 623 #define  ID_AA64ISAR1_JSCVT_IMPL        (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT)
 624 #define ID_AA64ISAR1_FCMA_SHIFT         16
 625 #define ID_AA64ISAR1_FCMA_MASK          (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT)
 626 #define ID_AA64ISAR1_FCMA_VAL(x)        ((x) & ID_AA64ISAR1_FCMA_MASK)
 627 #define  ID_AA64ISAR1_FCMA_NONE         (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT)
 628 #define  ID_AA64ISAR1_FCMA_IMPL         (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT)
 629 #define ID_AA64ISAR1_LRCPC_SHIFT        20
 630 #define ID_AA64ISAR1_LRCPC_MASK         (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT)
 631 #define ID_AA64ISAR1_LRCPC_VAL(x)       ((x) & ID_AA64ISAR1_LRCPC_MASK)
 632 #define  ID_AA64ISAR1_LRCPC_NONE        (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT)
 633 #define  ID_AA64ISAR1_LRCPC_RCPC_8_3    (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT)
 634 #define  ID_AA64ISAR1_LRCPC_RCPC_8_4    (UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT)
 635 #define ID_AA64ISAR1_GPA_SHIFT          24
 636 #define ID_AA64ISAR1_GPA_MASK           (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT)
 637 #define ID_AA64ISAR1_GPA_VAL(x)         ((x) & ID_AA64ISAR1_GPA_MASK)
 638 #define  ID_AA64ISAR1_GPA_NONE          (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT)
 639 #define  ID_AA64ISAR1_GPA_IMPL          (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT)
 640 #define ID_AA64ISAR1_GPI_SHIFT          28
 641 #define ID_AA64ISAR1_GPI_MASK           (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT)
 642 #define ID_AA64ISAR1_GPI_VAL(x)         ((x) & ID_AA64ISAR1_GPI_MASK)
 643 #define  ID_AA64ISAR1_GPI_NONE          (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT)
 644 #define  ID_AA64ISAR1_GPI_IMPL          (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT)
 645 #define ID_AA64ISAR1_FRINTTS_SHIFT      32
 646 #define ID_AA64ISAR1_FRINTTS_MASK       (UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT)
 647 #define ID_AA64ISAR1_FRINTTS_VAL(x)     ((x) & ID_AA64ISAR1_FRINTTS_MASK)
 648 #define  ID_AA64ISAR1_FRINTTS_NONE      (UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT)
 649 #define  ID_AA64ISAR1_FRINTTS_IMPL      (UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT)
 650 #define ID_AA64ISAR1_SB_SHIFT           36
 651 #define ID_AA64ISAR1_SB_MASK            (UL(0xf) << ID_AA64ISAR1_SB_SHIFT)
 652 #define ID_AA64ISAR1_SB_VAL(x)          ((x) & ID_AA64ISAR1_SB_MASK)
 653 #define  ID_AA64ISAR1_SB_NONE           (UL(0x0) << ID_AA64ISAR1_SB_SHIFT)
 654 #define  ID_AA64ISAR1_SB_IMPL           (UL(0x1) << ID_AA64ISAR1_SB_SHIFT)
 655 #define ID_AA64ISAR1_SPECRES_SHIFT      40
 656 #define ID_AA64ISAR1_SPECRES_MASK       (UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT)
 657 #define ID_AA64ISAR1_SPECRES_VAL(x)     ((x) & ID_AA64ISAR1_SPECRES_MASK)
 658 #define  ID_AA64ISAR1_SPECRES_NONE      (UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT)
 659 #define  ID_AA64ISAR1_SPECRES_IMPL      (UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT)
 660 #define ID_AA64ISAR1_BF16_SHIFT         44
 661 #define ID_AA64ISAR1_BF16_MASK          (UL(0xf) << ID_AA64ISAR1_BF16_SHIFT)
 662 #define ID_AA64ISAR1_BF16_VAL(x)        ((x) & ID_AA64ISAR1_BF16_MASK)
 663 #define  ID_AA64ISAR1_BF16_NONE         (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT)
 664 #define  ID_AA64ISAR1_BF16_IMPL         (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT)
 665 #define ID_AA64ISAR1_DGH_SHIFT          48
 666 #define ID_AA64ISAR1_DGH_MASK           (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT)
 667 #define ID_AA64ISAR1_DGH_VAL(x)         ((x) & ID_AA64ISAR1_DGH_MASK)
 668 #define  ID_AA64ISAR1_DGH_NONE          (UL(0x0) << ID_AA64ISAR1_DGH_SHIFT)
 669 #define  ID_AA64ISAR1_DGH_IMPL          (UL(0x1) << ID_AA64ISAR1_DGH_SHIFT)
 670 #define ID_AA64ISAR1_I8MM_SHIFT         52
 671 #define ID_AA64ISAR1_I8MM_MASK          (UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT)
 672 #define ID_AA64ISAR1_I8MM_VAL(x)        ((x) & ID_AA64ISAR1_I8MM_MASK)
 673 #define  ID_AA64ISAR1_I8MM_NONE         (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT)
 674 #define  ID_AA64ISAR1_I8MM_IMPL         (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT)
 675
 676 /* ID_AA64ISAR2_EL1 */
 677 #define ID_AA64ISAR2_EL1                MRS_REG(ID_AA64ISAR2_EL1)
 678 #define ID_AA64ISAR2_EL1_op0            3
 679 #define ID_AA64ISAR2_EL1_op1            0
 680 #define ID_AA64ISAR2_EL1_CRn            0
 681 #define ID_AA64ISAR2_EL1_CRm            6
 682 #define ID_AA64ISAR2_EL1_op2            2
 683 #define ID_AA64ISAR2_WFxT_SHIFT         0
 684 #define ID_AA64ISAR2_WFxT_MASK          (UL(0xf) << ID_AA64ISAR2_WFxT_SHIFT)
 685 #define ID_AA64ISAR2_WFxT_VAL(x)        ((x) & ID_AA64ISAR2_WFxT_MASK)
 686 #define  ID_AA64ISAR2_WFxT_NONE         (UL(0x0) << ID_AA64ISAR2_WFxT_SHIFT)
 687 #define  ID_AA64ISAR2_WFxT_IMPL         (UL(0x1) << ID_AA64ISAR2_WFxT_SHIFT)
 688 #define ID_AA64ISAR2_RPRES_SHIFT        4
 689 #define ID_AA64ISAR2_RPRES_MASK         (UL(0xf) << ID_AA64ISAR2_RPRES_SHIFT)
 690 #define ID_AA64ISAR2_RPRES_VAL(x)       ((x) & ID_AA64ISAR2_RPRES_MASK)
 691 #define  ID_AA64ISAR2_RPRES_NONE        (UL(0x0) << ID_AA64ISAR2_RPRES_SHIFT)
 692 #define  ID_AA64ISAR2_RPRES_IMPL        (UL(0x1) << ID_AA64ISAR2_RPRES_SHIFT)
 693 #define ID_AA64ISAR2_GPA3_SHIFT         8
 694 #define ID_AA64ISAR2_GPA3_MASK          (UL(0xf) << ID_AA64ISAR2_GPA3_SHIFT)
 695 #define ID_AA64ISAR2_GPA3_VAL(x)        ((x) & ID_AA64ISAR2_GPA3_MASK)
 696 #define  ID_AA64ISAR2_GPA3_NONE         (UL(0x0) << ID_AA64ISAR2_GPA3_SHIFT)
 697 #define  ID_AA64ISAR2_GPA3_IMPL         (UL(0x1) << ID_AA64ISAR2_GPA3_SHIFT)
 698 #define ID_AA64ISAR2_APA3_SHIFT         12
 699 #define ID_AA64ISAR2_APA3_MASK          (UL(0xf) << ID_AA64ISAR2_APA3_SHIFT)
 700 #define ID_AA64ISAR2_APA3_VAL(x)        ((x) & ID_AA64ISAR2_APA3_MASK)
 701 #define  ID_AA64ISAR2_APA3_NONE         (UL(0x0) << ID_AA64ISAR2_APA3_SHIFT)
 702 #define  ID_AA64ISAR2_APA3_PAC          (UL(0x1) << ID_AA64ISAR2_APA3_SHIFT)
 703 #define  ID_AA64ISAR2_APA3_EPAC         (UL(0x2) << ID_AA64ISAR2_APA3_SHIFT)
 704 #define  ID_AA64ISAR2_APA3_EPAC2        (UL(0x3) << ID_AA64ISAR2_APA3_SHIFT)
 705 #define  ID_AA64ISAR2_APA3_FPAC         (UL(0x4) << ID_AA64ISAR2_APA3_SHIFT)
 706 #define  ID_AA64ISAR2_APA3_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR2_APA3_SHIFT)
 707 #define ID_AA64ISAR2_MOPS_SHIFT         16
 708 #define ID_AA64ISAR2_MOPS_MASK          (UL(0xf) << ID_AA64ISAR2_MOPS_SHIFT)
 709 #define ID_AA64ISAR2_MOPS_VAL(x)        ((x) & ID_AA64ISAR2_MOPS_MASK)
 710 #define  ID_AA64ISAR2_MOPS_NONE         (UL(0x0) << ID_AA64ISAR2_MOPS_SHIFT)
 711 #define  ID_AA64ISAR2_MOPS_IMPL         (UL(0x1) << ID_AA64ISAR2_MOPS_SHIFT)
 712 #define ID_AA64ISAR2_BC_SHIFT           20
 713 #define ID_AA64ISAR2_BC_MASK            (UL(0xf) << ID_AA64ISAR2_BC_SHIFT)
 714 #define ID_AA64ISAR2_BC_VAL(x)          ((x) & ID_AA64ISAR2_BC_MASK)
 715 #define  ID_AA64ISAR2_BC_NONE           (UL(0x0) << ID_AA64ISAR2_BC_SHIFT)
 716 #define  ID_AA64ISAR2_BC_IMPL           (UL(0x1) << ID_AA64ISAR2_BC_SHIFT)
 717 #define ID_AA64ISAR2_PAC_frac_SHIFT     28
 718 #define ID_AA64ISAR2_PAC_frac_MASK      (UL(0xf) << ID_AA64ISAR2_PAC_frac_SHIFT)
 719 #define ID_AA64ISAR2_PAC_frac_VAL(x)    ((x) & ID_AA64ISAR2_PAC_frac_MASK)
 720 #define  ID_AA64ISAR2_PAC_frac_NONE     (UL(0x0) << ID_AA64ISAR2_PAC_frac_SHIFT)
 721 #define  ID_AA64ISAR2_PAC_frac_IMPL     (UL(0x1) << ID_AA64ISAR2_PAC_frac_SHIFT)
 722
 723 /* ID_AA64MMFR0_EL1 */
 724 #define ID_AA64MMFR0_EL1                MRS_REG(ID_AA64MMFR0_EL1)
 725 #define ID_AA64MMFR0_EL1_op0            0x3
 726 #define ID_AA64MMFR0_EL1_op1            0x0
 727 #define ID_AA64MMFR0_EL1_CRn            0x0
 728 #define ID_AA64MMFR0_EL1_CRm            0x7
 729 #define ID_AA64MMFR0_EL1_op2            0x0
 730 #define ID_AA64MMFR0_PARange_SHIFT      0
 731 #define ID_AA64MMFR0_PARange_MASK       (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
 732 #define ID_AA64MMFR0_PARange_VAL(x)     ((x) & ID_AA64MMFR0_PARange_MASK)
 733 #define  ID_AA64MMFR0_PARange_4G        (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT)
 734 #define  ID_AA64MMFR0_PARange_64G       (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT)
 735 #define  ID_AA64MMFR0_PARange_1T        (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT)
 736 #define  ID_AA64MMFR0_PARange_4T        (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT)
 737 #define  ID_AA64MMFR0_PARange_16T       (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT)
 738 #define  ID_AA64MMFR0_PARange_256T      (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT)
 739 #define  ID_AA64MMFR0_PARange_4P        (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT)
 740 #define ID_AA64MMFR0_ASIDBits_SHIFT     4
 741 #define ID_AA64MMFR0_ASIDBits_MASK      (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT)
 742 #define ID_AA64MMFR0_ASIDBits_VAL(x)    ((x) & ID_AA64MMFR0_ASIDBits_MASK)
 743 #define  ID_AA64MMFR0_ASIDBits_8        (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT)
 744 #define  ID_AA64MMFR0_ASIDBits_16       (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT)
 745 #define ID_AA64MMFR0_BigEnd_SHIFT       8
 746 #define ID_AA64MMFR0_BigEnd_MASK        (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT)
 747 #define ID_AA64MMFR0_BigEnd_VAL(x)      ((x) & ID_AA64MMFR0_BigEnd_MASK)
 748 #define  ID_AA64MMFR0_BigEnd_FIXED      (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT)
 749 #define  ID_AA64MMFR0_BigEnd_MIXED      (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT)
 750 #define ID_AA64MMFR0_SNSMem_SHIFT       12
 751 #define ID_AA64MMFR0_SNSMem_MASK        (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT)
 752 #define ID_AA64MMFR0_SNSMem_VAL(x)      ((x) & ID_AA64MMFR0_SNSMem_MASK)
 753 #define  ID_AA64MMFR0_SNSMem_NONE       (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT)
 754 #define  ID_AA64MMFR0_SNSMem_DISTINCT   (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT)
 755 #define ID_AA64MMFR0_BigEndEL0_SHIFT    16
 756 #define ID_AA64MMFR0_BigEndEL0_MASK     (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT)
 757 #define ID_AA64MMFR0_BigEndEL0_VAL(x)   ((x) & ID_AA64MMFR0_BigEndEL0_MASK)
 758 #define  ID_AA64MMFR0_BigEndEL0_FIXED   (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT)
 759 #define  ID_AA64MMFR0_BigEndEL0_MIXED   (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT)
 760 #define ID_AA64MMFR0_TGran16_SHIFT      20
 761 #define ID_AA64MMFR0_TGran16_MASK       (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT)
 762 #define ID_AA64MMFR0_TGran16_VAL(x)     ((x) & ID_AA64MMFR0_TGran16_MASK)
 763 #define  ID_AA64MMFR0_TGran16_NONE      (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT)
 764 #define  ID_AA64MMFR0_TGran16_IMPL      (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT)
 765 #define ID_AA64MMFR0_TGran64_SHIFT      24
 766 #define ID_AA64MMFR0_TGran64_MASK       (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
 767 #define ID_AA64MMFR0_TGran64_VAL(x)     ((x) & ID_AA64MMFR0_TGran64_MASK)
 768 #define  ID_AA64MMFR0_TGran64_IMPL      (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT)
 769 #define  ID_AA64MMFR0_TGran64_NONE      (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
 770 #define ID_AA64MMFR0_TGran4_SHIFT       28
 771 #define ID_AA64MMFR0_TGran4_MASK        (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
 772 #define ID_AA64MMFR0_TGran4_VAL(x)      ((x) & ID_AA64MMFR0_TGran4_MASK)
 773 #define  ID_AA64MMFR0_TGran4_IMPL       (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT)
 774 #define  ID_AA64MMFR0_TGran4_NONE       (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
 775 #define ID_AA64MMFR0_TGran16_2_SHIFT    32
 776 #define ID_AA64MMFR0_TGran16_2_MASK     (UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT)
 777 #define ID_AA64MMFR0_TGran16_2_VAL(x)   ((x) & ID_AA64MMFR0_TGran16_2_MASK)
 778 #define  ID_AA64MMFR0_TGran16_2_TGran16 (UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT)
 779 #define  ID_AA64MMFR0_TGran16_2_NONE    (UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT)
 780 #define  ID_AA64MMFR0_TGran16_2_IMPL    (UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT)
 781 #define ID_AA64MMFR0_TGran64_2_SHIFT    36
 782 #define ID_AA64MMFR0_TGran64_2_MASK     (UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT)
 783 #define ID_AA64MMFR0_TGran64_2_VAL(x)   ((x) & ID_AA64MMFR0_TGran64_2_MASK)
 784 #define  ID_AA64MMFR0_TGran64_2_TGran64 (UL(0x0) << ID_AA64MMFR0_TGran64_2_SHIFT)
 785 #define  ID_AA64MMFR0_TGran64_2_NONE    (UL(0x1) << ID_AA64MMFR0_TGran64_2_SHIFT)
 786 #define  ID_AA64MMFR0_TGran64_2_IMPL    (UL(0x2) << ID_AA64MMFR0_TGran64_2_SHIFT)
 787 #define ID_AA64MMFR0_TGran4_2_SHIFT     40
 788 #define ID_AA64MMFR0_TGran4_2_MASK      (UL(0xf) << ID_AA64MMFR0_TGran4_2_SHIFT)
 789 #define ID_AA64MMFR0_TGran4_2_VAL(x)    ((x) & ID_AA64MMFR0_TGran4_2_MASK)
 790 #define  ID_AA64MMFR0_TGran4_2_TGran4   (UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT)
 791 #define  ID_AA64MMFR0_TGran4_2_NONE     (UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT)
 792 #define  ID_AA64MMFR0_TGran4_2_IMPL     (UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT)
 793 #define ID_AA64MMFR0_ExS_SHIFT          44
 794 #define ID_AA64MMFR0_ExS_MASK           (UL(0xf) << ID_AA64MMFR0_ExS_SHIFT)
 795 #define ID_AA64MMFR0_ExS_VAL(x)         ((x) & ID_AA64MMFR0_ExS_MASK)
 796 #define  ID_AA64MMFR0_ExS_ALL           (UL(0x0) << ID_AA64MMFR0_ExS_SHIFT)
 797 #define  ID_AA64MMFR0_ExS_IMPL          (UL(0x1) << ID_AA64MMFR0_ExS_SHIFT)
 798
 799 /* ID_AA64MMFR1_EL1 */
 800 #define ID_AA64MMFR1_EL1                MRS_REG(ID_AA64MMFR1_EL1)
 801 #define ID_AA64MMFR1_EL1_op0            0x3
 802 #define ID_AA64MMFR1_EL1_op1            0x0
 803 #define ID_AA64MMFR1_EL1_CRn            0x0
 804 #define ID_AA64MMFR1_EL1_CRm            0x7
 805 #define ID_AA64MMFR1_EL1_op2            0x1
 806 #define ID_AA64MMFR1_HAFDBS_SHIFT       0
 807 #define ID_AA64MMFR1_HAFDBS_MASK        (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
 808 #define ID_AA64MMFR1_HAFDBS_VAL(x)      ((x) & ID_AA64MMFR1_HAFDBS_MASK)
 809 #define  ID_AA64MMFR1_HAFDBS_NONE       (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT)
 810 #define  ID_AA64MMFR1_HAFDBS_AF         (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT)
 811 #define  ID_AA64MMFR1_HAFDBS_AF_DBS     (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT)
 812 #define ID_AA64MMFR1_VMIDBits_SHIFT     4
 813 #define ID_AA64MMFR1_VMIDBits_MASK      (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT)
 814 #define ID_AA64MMFR1_VMIDBits_VAL(x)    ((x) & ID_AA64MMFR1_VMIDBits_MASK)
 815 #define  ID_AA64MMFR1_VMIDBits_8        (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT)
 816 #define  ID_AA64MMFR1_VMIDBits_16       (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT)
 817 #define ID_AA64MMFR1_VH_SHIFT           8
 818 #define ID_AA64MMFR1_VH_MASK            (UL(0xf) << ID_AA64MMFR1_VH_SHIFT)
 819 #define ID_AA64MMFR1_VH_VAL(x)          ((x) & ID_AA64MMFR1_VH_MASK)
 820 #define  ID_AA64MMFR1_VH_NONE           (UL(0x0) << ID_AA64MMFR1_VH_SHIFT)
 821 #define  ID_AA64MMFR1_VH_IMPL           (UL(0x1) << ID_AA64MMFR1_VH_SHIFT)
 822 #define ID_AA64MMFR1_HPDS_SHIFT         12
 823 #define ID_AA64MMFR1_HPDS_MASK          (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT)
 824 #define ID_AA64MMFR1_HPDS_VAL(x)        ((x) & ID_AA64MMFR1_HPDS_MASK)
 825 #define  ID_AA64MMFR1_HPDS_NONE         (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT)
 826 #define  ID_AA64MMFR1_HPDS_HPD          (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT)
 827 #define  ID_AA64MMFR1_HPDS_TTPBHA       (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT)
 828 #define ID_AA64MMFR1_LO_SHIFT           16
 829 #define ID_AA64MMFR1_LO_MASK            (UL(0xf) << ID_AA64MMFR1_LO_SHIFT)
 830 #define ID_AA64MMFR1_LO_VAL(x)          ((x) & ID_AA64MMFR1_LO_MASK)
 831 #define  ID_AA64MMFR1_LO_NONE           (UL(0x0) << ID_AA64MMFR1_LO_SHIFT)
 832 #define  ID_AA64MMFR1_LO_IMPL           (UL(0x1) << ID_AA64MMFR1_LO_SHIFT)
 833 #define ID_AA64MMFR1_PAN_SHIFT          20
 834 #define ID_AA64MMFR1_PAN_MASK           (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT)
 835 #define ID_AA64MMFR1_PAN_VAL(x)         ((x) & ID_AA64MMFR1_PAN_MASK)
 836 #define  ID_AA64MMFR1_PAN_NONE          (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT)
 837 #define  ID_AA64MMFR1_PAN_IMPL          (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT)
 838 #define  ID_AA64MMFR1_PAN_ATS1E1        (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT)
 839 #define ID_AA64MMFR1_SpecSEI_SHIFT      24
 840 #define ID_AA64MMFR1_SpecSEI_MASK       (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT)
 841 #define ID_AA64MMFR1_SpecSEI_VAL(x)     ((x) & ID_AA64MMFR1_SpecSEI_MASK)
 842 #define  ID_AA64MMFR1_SpecSEI_NONE      (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT)
 843 #define  ID_AA64MMFR1_SpecSEI_IMPL      (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT)
 844 #define ID_AA64MMFR1_XNX_SHIFT          28
 845 #define ID_AA64MMFR1_XNX_MASK           (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT)
 846 #define ID_AA64MMFR1_XNX_VAL(x)         ((x) & ID_AA64MMFR1_XNX_MASK)
 847 #define  ID_AA64MMFR1_XNX_NONE          (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT)
 848 #define  ID_AA64MMFR1_XNX_IMPL          (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT)
 849
 850 /* ID_AA64MMFR2_EL1 */
 851 #define ID_AA64MMFR2_EL1                MRS_REG(ID_AA64MMFR2_EL1)
 852 #define ID_AA64MMFR2_EL1_op0            0x3
 853 #define ID_AA64MMFR2_EL1_op1            0x0
 854 #define ID_AA64MMFR2_EL1_CRn            0x0
 855 #define ID_AA64MMFR2_EL1_CRm            0x7
 856 #define ID_AA64MMFR2_EL1_op2            0x2
 857 #define ID_AA64MMFR2_CnP_SHIFT          0
 858 #define ID_AA64MMFR2_CnP_MASK           (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT)
 859 #define ID_AA64MMFR2_CnP_VAL(x)         ((x) & ID_AA64MMFR2_CnP_MASK)
 860 #define  ID_AA64MMFR2_CnP_NONE          (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT)
 861 #define  ID_AA64MMFR2_CnP_IMPL          (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT)
 862 #define ID_AA64MMFR2_UAO_SHIFT          4
 863 #define ID_AA64MMFR2_UAO_MASK           (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT)
 864 #define ID_AA64MMFR2_UAO_VAL(x)         ((x) & ID_AA64MMFR2_UAO_MASK)
 865 #define  ID_AA64MMFR2_UAO_NONE          (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT)
 866 #define  ID_AA64MMFR2_UAO_IMPL          (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT)
 867 #define ID_AA64MMFR2_LSM_SHIFT          8
 868 #define ID_AA64MMFR2_LSM_MASK           (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT)
 869 #define ID_AA64MMFR2_LSM_VAL(x)         ((x) & ID_AA64MMFR2_LSM_MASK)
 870 #define  ID_AA64MMFR2_LSM_NONE          (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT)
 871 #define  ID_AA64MMFR2_LSM_IMPL          (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT)
 872 #define ID_AA64MMFR2_IESB_SHIFT         12
 873 #define ID_AA64MMFR2_IESB_MASK          (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT)
 874 #define ID_AA64MMFR2_IESB_VAL(x)        ((x) & ID_AA64MMFR2_IESB_MASK)
 875 #define  ID_AA64MMFR2_IESB_NONE         (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT)
 876 #define  ID_AA64MMFR2_IESB_IMPL         (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT)
 877 #define ID_AA64MMFR2_VARange_SHIFT      16
 878 #define ID_AA64MMFR2_VARange_MASK       (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT)
 879 #define ID_AA64MMFR2_VARange_VAL(x)     ((x) & ID_AA64MMFR2_VARange_MASK)
 880 #define  ID_AA64MMFR2_VARange_48        (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT)
 881 #define  ID_AA64MMFR2_VARange_52        (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT)
 882 #define ID_AA64MMFR2_CCIDX_SHIFT        20
 883 #define ID_AA64MMFR2_CCIDX_MASK         (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT)
 884 #define ID_AA64MMFR2_CCIDX_VAL(x)       ((x) & ID_AA64MMFR2_CCIDX_MASK)
 885 #define  ID_AA64MMFR2_CCIDX_32          (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT)
 886 #define  ID_AA64MMFR2_CCIDX_64          (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT)
 887 #define ID_AA64MMFR2_NV_SHIFT           24
 888 #define ID_AA64MMFR2_NV_MASK            (UL(0xf) << ID_AA64MMFR2_NV_SHIFT)
 889 #define ID_AA64MMFR2_NV_VAL(x)          ((x) & ID_AA64MMFR2_NV_MASK)
 890 #define  ID_AA64MMFR2_NV_NONE           (UL(0x0) << ID_AA64MMFR2_NV_SHIFT)
 891 #define  ID_AA64MMFR2_NV_8_3            (UL(0x1) << ID_AA64MMFR2_NV_SHIFT)
 892 #define  ID_AA64MMFR2_NV_8_4            (UL(0x2) << ID_AA64MMFR2_NV_SHIFT)
 893 #define ID_AA64MMFR2_ST_SHIFT           28
 894 #define ID_AA64MMFR2_ST_MASK            (UL(0xf) << ID_AA64MMFR2_ST_SHIFT)
 895 #define ID_AA64MMFR2_ST_VAL(x)          ((x) & ID_AA64MMFR2_ST_MASK)
 896 #define  ID_AA64MMFR2_ST_NONE           (UL(0x0) << ID_AA64MMFR2_ST_SHIFT)
 897 #define  ID_AA64MMFR2_ST_IMPL           (UL(0x1) << ID_AA64MMFR2_ST_SHIFT)
 898 #define ID_AA64MMFR2_AT_SHIFT           32
 899 #define ID_AA64MMFR2_AT_MASK            (UL(0xf) << ID_AA64MMFR2_AT_SHIFT)
 900 #define ID_AA64MMFR2_AT_VAL(x)          ((x) & ID_AA64MMFR2_AT_MASK)
 901 #define  ID_AA64MMFR2_AT_NONE           (UL(0x0) << ID_AA64MMFR2_AT_SHIFT)
 902 #define  ID_AA64MMFR2_AT_IMPL           (UL(0x1) << ID_AA64MMFR2_AT_SHIFT)
 903 #define ID_AA64MMFR2_IDS_SHIFT          36
 904 #define ID_AA64MMFR2_IDS_MASK           (UL(0xf) << ID_AA64MMFR2_IDS_SHIFT)
 905 #define ID_AA64MMFR2_IDS_VAL(x)         ((x) & ID_AA64MMFR2_IDS_MASK)
 906 #define  ID_AA64MMFR2_IDS_NONE          (UL(0x0) << ID_AA64MMFR2_IDS_SHIFT)
 907 #define  ID_AA64MMFR2_IDS_IMPL          (UL(0x1) << ID_AA64MMFR2_IDS_SHIFT)
 908 #define ID_AA64MMFR2_FWB_SHIFT          40
 909 #define ID_AA64MMFR2_FWB_MASK           (UL(0xf) << ID_AA64MMFR2_FWB_SHIFT)
 910 #define ID_AA64MMFR2_FWB_VAL(x)         ((x) & ID_AA64MMFR2_FWB_MASK)
 911 #define  ID_AA64MMFR2_FWB_NONE          (UL(0x0) << ID_AA64MMFR2_FWB_SHIFT)
 912 #define  ID_AA64MMFR2_FWB_IMPL          (UL(0x1) << ID_AA64MMFR2_FWB_SHIFT)
 913 #define ID_AA64MMFR2_TTL_SHIFT          48
 914 #define ID_AA64MMFR2_TTL_MASK           (UL(0xf) << ID_AA64MMFR2_TTL_SHIFT)
 915 #define ID_AA64MMFR2_TTL_VAL(x)         ((x) & ID_AA64MMFR2_TTL_MASK)
 916 #define  ID_AA64MMFR2_TTL_NONE          (UL(0x0) << ID_AA64MMFR2_TTL_SHIFT)
 917 #define  ID_AA64MMFR2_TTL_IMPL          (UL(0x1) << ID_AA64MMFR2_TTL_SHIFT)
 918 #define ID_AA64MMFR2_BBM_SHIFT          52
 919 #define ID_AA64MMFR2_BBM_MASK           (UL(0xf) << ID_AA64MMFR2_BBM_SHIFT)
 920 #define ID_AA64MMFR2_BBM_VAL(x)         ((x) & ID_AA64MMFR2_BBM_MASK)
 921 #define  ID_AA64MMFR2_BBM_LEVEL0        (UL(0x0) << ID_AA64MMFR2_BBM_SHIFT)
 922 #define  ID_AA64MMFR2_BBM_LEVEL1        (UL(0x1) << ID_AA64MMFR2_BBM_SHIFT)
 923 #define  ID_AA64MMFR2_BBM_LEVEL2        (UL(0x2) << ID_AA64MMFR2_BBM_SHIFT)
 924 #define ID_AA64MMFR2_EVT_SHIFT          56
 925 #define ID_AA64MMFR2_EVT_MASK           (UL(0xf) << ID_AA64MMFR2_EVT_SHIFT)
 926 #define ID_AA64MMFR2_EVT_VAL(x)         ((x) & ID_AA64MMFR2_EVT_MASK)
 927 #define  ID_AA64MMFR2_EVT_NONE          (UL(0x0) << ID_AA64MMFR2_EVT_SHIFT)
 928 #define  ID_AA64MMFR2_EVT_8_2           (UL(0x1) << ID_AA64MMFR2_EVT_SHIFT)
 929 #define  ID_AA64MMFR2_EVT_8_5           (UL(0x2) << ID_AA64MMFR2_EVT_SHIFT)
 930 #define ID_AA64MMFR2_E0PD_SHIFT         60
 931 #define ID_AA64MMFR2_E0PD_MASK          (UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT)
 932 #define ID_AA64MMFR2_E0PD_VAL(x)        ((x) & ID_AA64MMFR2_E0PD_MASK)
 933 #define  ID_AA64MMFR2_E0PD_NONE         (UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT)
 934 #define  ID_AA64MMFR2_E0PD_IMPL         (UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT)
 935
 936 /* ID_AA64PFR0_EL1 */
 937 #define ID_AA64PFR0_EL1                 MRS_REG(ID_AA64PFR0_EL1)
 938 #define ID_AA64PFR0_EL1_op0             0x3
 939 #define ID_AA64PFR0_EL1_op1             0x0
 940 #define ID_AA64PFR0_EL1_CRn             0x0
 941 #define ID_AA64PFR0_EL1_CRm             0x4
 942 #define ID_AA64PFR0_EL1_op2             0x0
 943 #define ID_AA64PFR0_EL0_SHIFT           0
 944 #define ID_AA64PFR0_EL0_MASK            (UL(0xf) << ID_AA64PFR0_EL0_SHIFT)
 945 #define ID_AA64PFR0_EL0_VAL(x)          ((x) & ID_AA64PFR0_EL0_MASK)
 946 #define  ID_AA64PFR0_EL0_64             (UL(0x1) << ID_AA64PFR0_EL0_SHIFT)
 947 #define  ID_AA64PFR0_EL0_64_32          (UL(0x2) << ID_AA64PFR0_EL0_SHIFT)
 948 #define ID_AA64PFR0_EL1_SHIFT           4
 949 #define ID_AA64PFR0_EL1_MASK            (UL(0xf) << ID_AA64PFR0_EL1_SHIFT)
 950 #define ID_AA64PFR0_EL1_VAL(x)          ((x) & ID_AA64PFR0_EL1_MASK)
 951 #define  ID_AA64PFR0_EL1_64             (UL(0x1) << ID_AA64PFR0_EL1_SHIFT)
 952 #define  ID_AA64PFR0_EL1_64_32          (UL(0x2) << ID_AA64PFR0_EL1_SHIFT)
 953 #define ID_AA64PFR0_EL2_SHIFT           8
 954 #define ID_AA64PFR0_EL2_MASK            (UL(0xf) << ID_AA64PFR0_EL2_SHIFT)
 955 #define ID_AA64PFR0_EL2_VAL(x)          ((x) & ID_AA64PFR0_EL2_MASK)
 956 #define  ID_AA64PFR0_EL2_NONE           (UL(0x0) << ID_AA64PFR0_EL2_SHIFT)
 957 #define  ID_AA64PFR0_EL2_64             (UL(0x1) << ID_AA64PFR0_EL2_SHIFT)
 958 #define  ID_AA64PFR0_EL2_64_32          (UL(0x2) << ID_AA64PFR0_EL2_SHIFT)
 959 #define ID_AA64PFR0_EL3_SHIFT           12
 960 #define ID_AA64PFR0_EL3_MASK            (UL(0xf) << ID_AA64PFR0_EL3_SHIFT)
 961 #define ID_AA64PFR0_EL3_VAL(x)          ((x) & ID_AA64PFR0_EL3_MASK)
 962 #define  ID_AA64PFR0_EL3_NONE           (UL(0x0) << ID_AA64PFR0_EL3_SHIFT)
 963 #define  ID_AA64PFR0_EL3_64             (UL(0x1) << ID_AA64PFR0_EL3_SHIFT)
 964 #define  ID_AA64PFR0_EL3_64_32          (UL(0x2) << ID_AA64PFR0_EL3_SHIFT)
 965 #define ID_AA64PFR0_FP_SHIFT            16
 966 #define ID_AA64PFR0_FP_MASK             (UL(0xf) << ID_AA64PFR0_FP_SHIFT)
 967 #define ID_AA64PFR0_FP_VAL(x)           ((x) & ID_AA64PFR0_FP_MASK)
 968 #define  ID_AA64PFR0_FP_IMPL            (UL(0x0) << ID_AA64PFR0_FP_SHIFT)
 969 #define  ID_AA64PFR0_FP_HP              (UL(0x1) << ID_AA64PFR0_FP_SHIFT)
 970 #define  ID_AA64PFR0_FP_NONE            (UL(0xf) << ID_AA64PFR0_FP_SHIFT)
 971 #define ID_AA64PFR0_AdvSIMD_SHIFT       20
 972 #define ID_AA64PFR0_AdvSIMD_MASK        (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
 973 #define ID_AA64PFR0_AdvSIMD_VAL(x)      ((x) & ID_AA64PFR0_AdvSIMD_MASK)
 974 #define  ID_AA64PFR0_AdvSIMD_IMPL       (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT)
 975 #define  ID_AA64PFR0_AdvSIMD_HP         (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT)
 976 #define  ID_AA64PFR0_AdvSIMD_NONE       (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
 977 #define ID_AA64PFR0_GIC_BITS            0x4 /* Number of bits in GIC field */
 978 #define ID_AA64PFR0_GIC_SHIFT           24
 979 #define ID_AA64PFR0_GIC_MASK            (UL(0xf) << ID_AA64PFR0_GIC_SHIFT)
 980 #define ID_AA64PFR0_GIC_VAL(x)          ((x) & ID_AA64PFR0_GIC_MASK)
 981 #define  ID_AA64PFR0_GIC_CPUIF_NONE     (UL(0x0) << ID_AA64PFR0_GIC_SHIFT)
 982 #define  ID_AA64PFR0_GIC_CPUIF_EN       (UL(0x1) << ID_AA64PFR0_GIC_SHIFT)
 983 #define  ID_AA64PFR0_GIC_CPUIF_4_1      (UL(0x3) << ID_AA64PFR0_GIC_SHIFT)
 984 #define ID_AA64PFR0_RAS_SHIFT           28
 985 #define ID_AA64PFR0_RAS_MASK            (UL(0xf) << ID_AA64PFR0_RAS_SHIFT)
 986 #define ID_AA64PFR0_RAS_VAL(x)          ((x) & ID_AA64PFR0_RAS_MASK)
 987 #define  ID_AA64PFR0_RAS_NONE           (UL(0x0) << ID_AA64PFR0_RAS_SHIFT)
 988 #define  ID_AA64PFR0_RAS_IMPL           (UL(0x1) << ID_AA64PFR0_RAS_SHIFT)
 989 #define  ID_AA64PFR0_RAS_8_4            (UL(0x2) << ID_AA64PFR0_RAS_SHIFT)
 990 #define ID_AA64PFR0_SVE_SHIFT           32
 991 #define ID_AA64PFR0_SVE_MASK            (UL(0xf) << ID_AA64PFR0_SVE_SHIFT)
 992 #define ID_AA64PFR0_SVE_VAL(x)          ((x) & ID_AA64PFR0_SVE_MASK)
 993 #define  ID_AA64PFR0_SVE_NONE           (UL(0x0) << ID_AA64PFR0_SVE_SHIFT)
 994 #define  ID_AA64PFR0_SVE_IMPL           (UL(0x1) << ID_AA64PFR0_SVE_SHIFT)
 995 #define ID_AA64PFR0_SEL2_SHIFT          36
 996 #define ID_AA64PFR0_SEL2_MASK           (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT)
 997 #define ID_AA64PFR0_SEL2_VAL(x)         ((x) & ID_AA64PFR0_SEL2_MASK)
 998 #define  ID_AA64PFR0_SEL2_NONE          (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT)
 999 #define  ID_AA64PFR0_SEL2_IMPL          (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT)
1000 #define ID_AA64PFR0_MPAM_SHIFT          40
1001 #define ID_AA64PFR0_MPAM_MASK           (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT)
1002 #define ID_AA64PFR0_MPAM_VAL(x)         ((x) & ID_AA64PFR0_MPAM_MASK)
1003 #define  ID_AA64PFR0_MPAM_NONE          (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT)
1004 #define  ID_AA64PFR0_MPAM_IMPL          (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT)
1005 #define ID_AA64PFR0_AMU_SHIFT           44
1006 #define ID_AA64PFR0_AMU_MASK            (UL(0xf) << ID_AA64PFR0_AMU_SHIFT)
1007 #define ID_AA64PFR0_AMU_VAL(x)          ((x) & ID_AA64PFR0_AMU_MASK)
1008 #define  ID_AA64PFR0_AMU_NONE           (UL(0x0) << ID_AA64PFR0_AMU_SHIFT)
1009 #define  ID_AA64PFR0_AMU_V1             (UL(0x1) << ID_AA64PFR0_AMU_SHIFT)
1010 #define ID_AA64PFR0_DIT_SHIFT           48
1011 #define ID_AA64PFR0_DIT_MASK            (UL(0xf) << ID_AA64PFR0_DIT_SHIFT)
1012 #define ID_AA64PFR0_DIT_VAL(x)          ((x) & ID_AA64PFR0_DIT_MASK)
1013 #define  ID_AA64PFR0_DIT_NONE           (UL(0x0) << ID_AA64PFR0_DIT_SHIFT)
1014 #define  ID_AA64PFR0_DIT_PSTATE         (UL(0x1) << ID_AA64PFR0_DIT_SHIFT)
1015 #define ID_AA64PFR0_CSV2_SHIFT          56
1016 #define ID_AA64PFR0_CSV2_MASK           (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT)
1017 #define ID_AA64PFR0_CSV2_VAL(x)         ((x) & ID_AA64PFR0_CSV2_MASK)
1018 #define  ID_AA64PFR0_CSV2_NONE          (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT)
1019 #define  ID_AA64PFR0_CSV2_ISOLATED      (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT)
1020 #define  ID_AA64PFR0_CSV2_SCXTNUM       (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT)
1021 #define ID_AA64PFR0_CSV3_SHIFT          60
1022 #define ID_AA64PFR0_CSV3_MASK           (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT)
1023 #define ID_AA64PFR0_CSV3_VAL(x)         ((x) & ID_AA64PFR0_CSV3_MASK)
1024 #define  ID_AA64PFR0_CSV3_NONE          (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT)
1025 #define  ID_AA64PFR0_CSV3_ISOLATED      (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT)
1026
1027 /* ID_AA64PFR1_EL1 */
1028 #define ID_AA64PFR1_EL1                 MRS_REG(ID_AA64PFR1_EL1)
1029 #define ID_AA64PFR1_EL1_op0             0x3
1030 #define ID_AA64PFR1_EL1_op1             0x0
1031 #define ID_AA64PFR1_EL1_CRn             0x0
1032 #define ID_AA64PFR1_EL1_CRm             0x4
1033 #define ID_AA64PFR1_EL1_op2             0x1
1034 #define ID_AA64PFR1_BT_SHIFT            0
1035 #define ID_AA64PFR1_BT_MASK             (UL(0xf) << ID_AA64PFR1_BT_SHIFT)
1036 #define ID_AA64PFR1_BT_VAL(x)           ((x) & ID_AA64PFR1_BT_MASK)
1037 #define  ID_AA64PFR1_BT_NONE            (UL(0x0) << ID_AA64PFR1_BT_SHIFT)
1038 #define  ID_AA64PFR1_BT_IMPL            (UL(0x1) << ID_AA64PFR1_BT_SHIFT)
1039 #define ID_AA64PFR1_SSBS_SHIFT          4
1040 #define ID_AA64PFR1_SSBS_MASK           (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT)
1041 #define ID_AA64PFR1_SSBS_VAL(x)         ((x) & ID_AA64PFR1_SSBS_MASK)
1042 #define  ID_AA64PFR1_SSBS_NONE          (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT)
1043 #define  ID_AA64PFR1_SSBS_PSTATE        (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT)
1044 #define  ID_AA64PFR1_SSBS_PSTATE_MSR    (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT)
1045 #define ID_AA64PFR1_MTE_SHIFT           8
1046 #define ID_AA64PFR1_MTE_MASK            (UL(0xf) << ID_AA64PFR1_MTE_SHIFT)
1047 #define ID_AA64PFR1_MTE_VAL(x)          ((x) & ID_AA64PFR1_MTE_MASK)
1048 #define  ID_AA64PFR1_MTE_NONE           (UL(0x0) << ID_AA64PFR1_MTE_SHIFT)
1049 #define  ID_AA64PFR1_MTE_IMPL_EL0       (UL(0x1) << ID_AA64PFR1_MTE_SHIFT)
1050 #define  ID_AA64PFR1_MTE_IMPL           (UL(0x2) << ID_AA64PFR1_MTE_SHIFT)
1051 #define ID_AA64PFR1_RAS_frac_SHIFT      12
1052 #define ID_AA64PFR1_RAS_frac_MASK       (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT)
1053 #define ID_AA64PFR1_RAS_frac_VAL(x)     ((x) & ID_AA64PFR1_RAS_frac_MASK)
1054 #define  ID_AA64PFR1_RAS_frac_V1        (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT)
1055 #define  ID_AA64PFR1_RAS_frac_V2        (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT)
1056
1057 /* ID_AA64ZFR0_EL1 */
1058 #define ID_AA64ZFR0_EL1                 MRS_REG(ID_AA64ZFR0_EL1)
1059 #define ID_AA64ZFR0_EL1_REG             MRS_REG_ALT_NAME(ID_AA64ZFR0_EL1)
1060 #define ID_AA64ZFR0_EL1_op0             3
1061 #define ID_AA64ZFR0_EL1_op1             0
1062 #define ID_AA64ZFR0_EL1_CRn             0
1063 #define ID_AA64ZFR0_EL1_CRm             4
1064 #define ID_AA64ZFR0_EL1_op2             4
1065 #define ID_AA64ZFR0_SVEver_SHIFT        0
1066 #define ID_AA64ZFR0_SVEver_MASK         (UL(0xf) << ID_AA64ZFR0_SVEver_SHIFT)
1067 #define ID_AA64ZFR0_SVEver_VAL(x)       ((x) & ID_AA64ZFR0_SVEver_MASK
1068 #define ID_AA64ZFR0_SVEver_SVE1         (UL(0x0) << ID_AA64ZFR0_SVEver_SHIFT)
1069 #define ID_AA64ZFR0_SVEver_SVE2         (UL(0x1) << ID_AA64ZFR0_SVEver_SHIFT)
1070 #define ID_AA64ZFR0_AES_SHIFT           4
1071 #define ID_AA64ZFR0_AES_MASK            (UL(0xf) << ID_AA64ZFR0_AES_SHIFT)
1072 #define ID_AA64ZFR0_AES_VAL(x)          ((x) & ID_AA64ZFR0_AES_MASK
1073 #define ID_AA64ZFR0_AES_NONE            (UL(0x0) << ID_AA64ZFR0_AES_SHIFT)
1074 #define ID_AA64ZFR0_AES_BASE            (UL(0x1) << ID_AA64ZFR0_AES_SHIFT)
1075 #define ID_AA64ZFR0_AES_PMULL           (UL(0x2) << ID_AA64ZFR0_AES_SHIFT)
1076 #define ID_AA64ZFR0_BitPerm_SHIFT       16
1077 #define ID_AA64ZFR0_BitPerm_MASK        (UL(0xf) << ID_AA64ZFR0_BitPerm_SHIFT)
1078 #define ID_AA64ZFR0_BitPerm_VAL(x)      ((x) & ID_AA64ZFR0_BitPerm_MASK
1079 #define ID_AA64ZFR0_BitPerm_NONE        (UL(0x0) << ID_AA64ZFR0_BitPerm_SHIFT)
1080 #define ID_AA64ZFR0_BitPerm_IMPL        (UL(0x1) << ID_AA64ZFR0_BitPerm_SHIFT)
1081 #define ID_AA64ZFR0_BF16_SHIFT          20
1082 #define ID_AA64ZFR0_BF16_MASK           (UL(0xf) << ID_AA64ZFR0_BF16_SHIFT)
1083 #define ID_AA64ZFR0_BF16_VAL(x)         ((x) & ID_AA64ZFR0_BF16_MASK
1084 #define ID_AA64ZFR0_BF16_NONE           (UL(0x0) << ID_AA64ZFR0_BF16_SHIFT)
1085 #define ID_AA64ZFR0_BF16_BASE           (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT)
1086 #define ID_AA64ZFR0_BF16_EBF            (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT)
1087 #define ID_AA64ZFR0_SHA3_SHIFT          32
1088 #define ID_AA64ZFR0_SHA3_MASK           (UL(0xf) << ID_AA64ZFR0_SHA3_SHIFT)
1089 #define ID_AA64ZFR0_SHA3_VAL(x)         ((x) & ID_AA64ZFR0_SHA3_MASK
1090 #define ID_AA64ZFR0_SHA3_NONE           (UL(0x0) << ID_AA64ZFR0_SHA3_SHIFT)
1091 #define ID_AA64ZFR0_SHA3_IMPL           (UL(0x1) << ID_AA64ZFR0_SHA3_SHIFT)
1092 #define ID_AA64ZFR0_SM4_SHIFT           40
1093 #define ID_AA64ZFR0_SM4_MASK            (UL(0xf) << ID_AA64ZFR0_SM4_SHIFT)
1094 #define ID_AA64ZFR0_SM4_VAL(x)          ((x) & ID_AA64ZFR0_SM4_MASK
1095 #define ID_AA64ZFR0_SM4_NONE            (UL(0x0) << ID_AA64ZFR0_SM4_SHIFT)
1096 #define ID_AA64ZFR0_SM4_IMPL            (UL(0x1) << ID_AA64ZFR0_SM4_SHIFT)
1097 #define ID_AA64ZFR0_I8MM_SHIFT          44
1098 #define ID_AA64ZFR0_I8MM_MASK           (UL(0xf) << ID_AA64ZFR0_I8MM_SHIFT)
1099 #define ID_AA64ZFR0_I8MM_VAL(x)         ((x) & ID_AA64ZFR0_I8MM_MASK
1100 #define ID_AA64ZFR0_I8MM_NONE           (UL(0x0) << ID_AA64ZFR0_I8MM_SHIFT)
1101 #define ID_AA64ZFR0_I8MM_IMPL           (UL(0x1) << ID_AA64ZFR0_I8MM_SHIFT)
1102 #define ID_AA64ZFR0_F32MM_SHIFT         52
1103 #define ID_AA64ZFR0_F32MM_MASK          (UL(0xf) << ID_AA64ZFR0_F32MM_SHIFT)
1104 #define ID_AA64ZFR0_F32MM_VAL(x)        ((x) & ID_AA64ZFR0_F32MM_MASK
1105 #define ID_AA64ZFR0_F32MM_NONE          (UL(0x0) << ID_AA64ZFR0_F32MM_SHIFT)
1106 #define ID_AA64ZFR0_F32MM_IMPL          (UL(0x1) << ID_AA64ZFR0_F32MM_SHIFT)
1107 #define ID_AA64ZFR0_F64MM_SHIFT         56
1108 #define ID_AA64ZFR0_F64MM_MASK          (UL(0xf) << ID_AA64ZFR0_F64MM_SHIFT)
1109 #define ID_AA64ZFR0_F64MM_VAL(x)        ((x) & ID_AA64ZFR0_F64MM_MASK
1110 #define ID_AA64ZFR0_F64MM_NONE          (UL(0x0) << ID_AA64ZFR0_F64MM_SHIFT)
1111 #define ID_AA64ZFR0_F64MM_IMPL          (UL(0x1) << ID_AA64ZFR0_F64MM_SHIFT)
1112
1113 /* ID_ISAR5_EL1 */
1114 #define ID_ISAR5_EL1                    MRS_REG(ID_ISAR5_EL1)
1115 #define ID_ISAR5_EL1_op0                0x3
1116 #define ID_ISAR5_EL1_op1                0x0
1117 #define ID_ISAR5_EL1_CRn                0x0
1118 #define ID_ISAR5_EL1_CRm                0x2
1119 #define ID_ISAR5_EL1_op2                0x5
1120 #define ID_ISAR5_SEVL_SHIFT             0
1121 #define ID_ISAR5_SEVL_MASK              (UL(0xf) << ID_ISAR5_SEVL_SHIFT)
1122 #define ID_ISAR5_SEVL_VAL(x)            ((x) & ID_ISAR5_SEVL_MASK)
1123 #define  ID_ISAR5_SEVL_NOP              (UL(0x0) << ID_ISAR5_SEVL_SHIFT)
1124 #define  ID_ISAR5_SEVL_IMPL             (UL(0x1) << ID_ISAR5_SEVL_SHIFT)
1125 #define ID_ISAR5_AES_SHIFT              4
1126 #define ID_ISAR5_AES_MASK               (UL(0xf) << ID_ISAR5_AES_SHIFT)
1127 #define ID_ISAR5_AES_VAL(x)             ((x) & ID_ISAR5_AES_MASK)
1128 #define  ID_ISAR5_AES_NONE              (UL(0x0) << ID_ISAR5_AES_SHIFT)
1129 #define  ID_ISAR5_AES_BASE              (UL(0x1) << ID_ISAR5_AES_SHIFT)
1130 #define  ID_ISAR5_AES_VMULL             (UL(0x2) << ID_ISAR5_AES_SHIFT)
1131 #define ID_ISAR5_SHA1_SHIFT             8
1132 #define ID_ISAR5_SHA1_MASK              (UL(0xf) << ID_ISAR5_SHA1_SHIFT)
1133 #define ID_ISAR5_SHA1_VAL(x)            ((x) & ID_ISAR5_SHA1_MASK)
1134 #define  ID_ISAR5_SHA1_NONE             (UL(0x0) << ID_ISAR5_SHA1_SHIFT)
1135 #define  ID_ISAR5_SHA1_IMPL             (UL(0x1) << ID_ISAR5_SHA1_SHIFT)
1136 #define ID_ISAR5_SHA2_SHIFT             12
1137 #define ID_ISAR5_SHA2_MASK              (UL(0xf) << ID_ISAR5_SHA2_SHIFT)
1138 #define ID_ISAR5_SHA2_VAL(x)            ((x) & ID_ISAR5_SHA2_MASK)
1139 #define  ID_ISAR5_SHA2_NONE             (UL(0x0) << ID_ISAR5_SHA2_SHIFT)
1140 #define  ID_ISAR5_SHA2_IMPL             (UL(0x1) << ID_ISAR5_SHA2_SHIFT)
1141 #define ID_ISAR5_CRC32_SHIFT            16
1142 #define ID_ISAR5_CRC32_MASK             (UL(0xf) << ID_ISAR5_CRC32_SHIFT)
1143 #define ID_ISAR5_CRC32_VAL(x)           ((x) & ID_ISAR5_CRC32_MASK)
1144 #define  ID_ISAR5_CRC32_NONE            (UL(0x0) << ID_ISAR5_CRC32_SHIFT)
1145 #define  ID_ISAR5_CRC32_IMPL            (UL(0x1) << ID_ISAR5_CRC32_SHIFT)
1146 #define ID_ISAR5_RDM_SHIFT              24
1147 #define ID_ISAR5_RDM_MASK               (UL(0xf) << ID_ISAR5_RDM_SHIFT)
1148 #define ID_ISAR5_RDM_VAL(x)             ((x) & ID_ISAR5_RDM_MASK)
1149 #define  ID_ISAR5_RDM_NONE              (UL(0x0) << ID_ISAR5_RDM_SHIFT)
1150 #define  ID_ISAR5_RDM_IMPL              (UL(0x1) << ID_ISAR5_RDM_SHIFT)
1151 #define ID_ISAR5_VCMA_SHIFT             28
1152 #define ID_ISAR5_VCMA_MASK              (UL(0xf) << ID_ISAR5_VCMA_SHIFT)
1153 #define ID_ISAR5_VCMA_VAL(x)            ((x) & ID_ISAR5_VCMA_MASK)
1154 #define  ID_ISAR5_VCMA_NONE             (UL(0x0) << ID_ISAR5_VCMA_SHIFT)
1155 #define  ID_ISAR5_VCMA_IMPL             (UL(0x1) << ID_ISAR5_VCMA_SHIFT)
1156
1157 /* MAIR_EL1 - Memory Attribute Indirection Register */
1158 #define MAIR_ATTR_MASK(idx)     (0xff << ((n)* 8))
1159 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
1160 #define  MAIR_DEVICE_nGnRnE     0x00
1161 #define  MAIR_DEVICE_nGnRE      0x04
1162 #define  MAIR_NORMAL_NC         0x44
1163 #define  MAIR_NORMAL_WT         0xbb
1164 #define  MAIR_NORMAL_WB         0xff
1165
1166 /* MDCCINT_EL1 */
1167 #define MDCCINT_EL1                     MRS_REG(MDCCINT_EL1)
1168 #define MDCCINT_EL1_op0                 2
1169 #define MDCCINT_EL1_op1                 0
1170 #define MDCCINT_EL1_CRn                 0
1171 #define MDCCINT_EL1_CRm                 2
1172 #define MDCCINT_EL1_op2                 0
1173
1174 /* MDCCSR_EL0 */
1175 #define MDCCSR_EL0                      MRS_REG(MDCCSR_EL0)
1176 #define MDCCSR_EL0_op0                  2
1177 #define MDCCSR_EL0_op1                  3
1178 #define MDCCSR_EL0_CRn                  0
1179 #define MDCCSR_EL0_CRm                  1
1180 #define MDCCSR_EL0_op2                  0
1181
1182 /* MDSCR_EL1 - Monitor Debug System Control Register */
1183 #define MDSCR_EL1                       MRS_REG(MDSCR_EL1)
1184 #define MDSCR_EL1_op0                   2
1185 #define MDSCR_EL1_op1                   0
1186 #define MDSCR_EL1_CRn                   0
1187 #define MDSCR_EL1_CRm                   2
1188 #define MDSCR_EL1_op2                   2
1189 #define MDSCR_SS_SHIFT                  0
1190 #define MDSCR_SS                        (UL(0x1) << MDSCR_SS_SHIFT)
1191 #define MDSCR_KDE_SHIFT                 13
1192 #define MDSCR_KDE                       (UL(0x1) << MDSCR_KDE_SHIFT)
1193 #define MDSCR_MDE_SHIFT                 15
1194 #define MDSCR_MDE                       (UL(0x1) << MDSCR_MDE_SHIFT)
1195
1196 /* MVFR0_EL1 */
1197 #define MVFR0_EL1                       MRS_REG(MVFR0_EL1)
1198 #define MVFR0_EL1_op0                   0x3
1199 #define MVFR0_EL1_op1                   0x0
1200 #define MVFR0_EL1_CRn                   0x0
1201 #define MVFR0_EL1_CRm                   0x3
1202 #define MVFR0_EL1_op2                   0x0
1203 #define MVFR0_SIMDReg_SHIFT             0
1204 #define MVFR0_SIMDReg_MASK              (UL(0xf) << MVFR0_SIMDReg_SHIFT)
1205 #define MVFR0_SIMDReg_VAL(x)            ((x) & MVFR0_SIMDReg_MASK)
1206 #define  MVFR0_SIMDReg_NONE             (UL(0x0) << MVFR0_SIMDReg_SHIFT)
1207 #define  MVFR0_SIMDReg_FP               (UL(0x1) << MVFR0_SIMDReg_SHIFT)
1208 #define  MVFR0_SIMDReg_AdvSIMD          (UL(0x2) << MVFR0_SIMDReg_SHIFT)
1209 #define MVFR0_FPSP_SHIFT                4
1210 #define MVFR0_FPSP_MASK                 (UL(0xf) << MVFR0_FPSP_SHIFT)
1211 #define MVFR0_FPSP_VAL(x)               ((x) & MVFR0_FPSP_MASK)
1212 #define  MVFR0_FPSP_NONE                (UL(0x0) << MVFR0_FPSP_SHIFT)
1213 #define  MVFR0_FPSP_VFP_v2              (UL(0x1) << MVFR0_FPSP_SHIFT)
1214 #define  MVFR0_FPSP_VFP_v3_v4           (UL(0x2) << MVFR0_FPSP_SHIFT)
1215 #define MVFR0_FPDP_SHIFT                8
1216 #define MVFR0_FPDP_MASK                 (UL(0xf) << MVFR0_FPDP_SHIFT)
1217 #define MVFR0_FPDP_VAL(x)               ((x) & MVFR0_FPDP_MASK)
1218 #define  MVFR0_FPDP_NONE                (UL(0x0) << MVFR0_FPDP_SHIFT)
1219 #define  MVFR0_FPDP_VFP_v2              (UL(0x1) << MVFR0_FPDP_SHIFT)
1220 #define  MVFR0_FPDP_VFP_v3_v4           (UL(0x2) << MVFR0_FPDP_SHIFT)
1221 #define MVFR0_FPTrap_SHIFT              12
1222 #define MVFR0_FPTrap_MASK               (UL(0xf) << MVFR0_FPTrap_SHIFT)
1223 #define MVFR0_FPTrap_VAL(x)             ((x) & MVFR0_FPTrap_MASK)
1224 #define  MVFR0_FPTrap_NONE              (UL(0x0) << MVFR0_FPTrap_SHIFT)
1225 #define  MVFR0_FPTrap_IMPL              (UL(0x1) << MVFR0_FPTrap_SHIFT)
1226 #define MVFR0_FPDivide_SHIFT            16
1227 #define MVFR0_FPDivide_MASK             (UL(0xf) << MVFR0_FPDivide_SHIFT)
1228 #define MVFR0_FPDivide_VAL(x)           ((x) & MVFR0_FPDivide_MASK)
1229 #define  MVFR0_FPDivide_NONE            (UL(0x0) << MVFR0_FPDivide_SHIFT)
1230 #define  MVFR0_FPDivide_IMPL            (UL(0x1) << MVFR0_FPDivide_SHIFT)
1231 #define MVFR0_FPSqrt_SHIFT              20
1232 #define MVFR0_FPSqrt_MASK               (UL(0xf) << MVFR0_FPSqrt_SHIFT)
1233 #define MVFR0_FPSqrt_VAL(x)             ((x) & MVFR0_FPSqrt_MASK)
1234 #define  MVFR0_FPSqrt_NONE              (UL(0x0) << MVFR0_FPSqrt_SHIFT)
1235 #define  MVFR0_FPSqrt_IMPL              (UL(0x1) << MVFR0_FPSqrt_SHIFT)
1236 #define MVFR0_FPShVec_SHIFT             24
1237 #define MVFR0_FPShVec_MASK              (UL(0xf) << MVFR0_FPShVec_SHIFT)
1238 #define MVFR0_FPShVec_VAL(x)            ((x) & MVFR0_FPShVec_MASK)
1239 #define  MVFR0_FPShVec_NONE             (UL(0x0) << MVFR0_FPShVec_SHIFT)
1240 #define  MVFR0_FPShVec_IMPL             (UL(0x1) << MVFR0_FPShVec_SHIFT)
1241 #define MVFR0_FPRound_SHIFT             28
1242 #define MVFR0_FPRound_MASK              (UL(0xf) << MVFR0_FPRound_SHIFT)
1243 #define MVFR0_FPRound_VAL(x)            ((x) & MVFR0_FPRound_MASK)
1244 #define  MVFR0_FPRound_NONE             (UL(0x0) << MVFR0_FPRound_SHIFT)
1245 #define  MVFR0_FPRound_IMPL             (UL(0x1) << MVFR0_FPRound_SHIFT)
1246
1247 /* MVFR1_EL1 */
1248 #define MVFR1_EL1                       MRS_REG(MVFR1_EL1)
1249 #define MVFR1_EL1_op0                   0x3
1250 #define MVFR1_EL1_op1                   0x0
1251 #define MVFR1_EL1_CRn                   0x0
1252 #define MVFR1_EL1_CRm                   0x3
1253 #define MVFR1_EL1_op2                   0x1
1254 #define MVFR1_FPFtZ_SHIFT               0
1255 #define MVFR1_FPFtZ_MASK                (UL(0xf) << MVFR1_FPFtZ_SHIFT)
1256 #define MVFR1_FPFtZ_VAL(x)              ((x) & MVFR1_FPFtZ_MASK)
1257 #define  MVFR1_FPFtZ_NONE               (UL(0x0) << MVFR1_FPFtZ_SHIFT)
1258 #define  MVFR1_FPFtZ_IMPL               (UL(0x1) << MVFR1_FPFtZ_SHIFT)
1259 #define MVFR1_FPDNaN_SHIFT              4
1260 #define MVFR1_FPDNaN_MASK               (UL(0xf) << MVFR1_FPDNaN_SHIFT)
1261 #define MVFR1_FPDNaN_VAL(x)             ((x) & MVFR1_FPDNaN_MASK)
1262 #define  MVFR1_FPDNaN_NONE              (UL(0x0) << MVFR1_FPDNaN_SHIFT)
1263 #define  MVFR1_FPDNaN_IMPL              (UL(0x1) << MVFR1_FPDNaN_SHIFT)
1264 #define MVFR1_SIMDLS_SHIFT              8
1265 #define MVFR1_SIMDLS_MASK               (UL(0xf) << MVFR1_SIMDLS_SHIFT)
1266 #define MVFR1_SIMDLS_VAL(x)             ((x) & MVFR1_SIMDLS_MASK)
1267 #define  MVFR1_SIMDLS_NONE              (UL(0x0) << MVFR1_SIMDLS_SHIFT)
1268 #define  MVFR1_SIMDLS_IMPL              (UL(0x1) << MVFR1_SIMDLS_SHIFT)
1269 #define MVFR1_SIMDInt_SHIFT             12
1270 #define MVFR1_SIMDInt_MASK              (UL(0xf) << MVFR1_SIMDInt_SHIFT)
1271 #define MVFR1_SIMDInt_VAL(x)            ((x) & MVFR1_SIMDInt_MASK)
1272 #define  MVFR1_SIMDInt_NONE             (UL(0x0) << MVFR1_SIMDInt_SHIFT)
1273 #define  MVFR1_SIMDInt_IMPL             (UL(0x1) << MVFR1_SIMDInt_SHIFT)
1274 #define MVFR1_SIMDSP_SHIFT              16
1275 #define MVFR1_SIMDSP_MASK               (UL(0xf) << MVFR1_SIMDSP_SHIFT)
1276 #define MVFR1_SIMDSP_VAL(x)             ((x) & MVFR1_SIMDSP_MASK)
1277 #define  MVFR1_SIMDSP_NONE              (UL(0x0) << MVFR1_SIMDSP_SHIFT)
1278 #define  MVFR1_SIMDSP_IMPL              (UL(0x1) << MVFR1_SIMDSP_SHIFT)
1279 #define MVFR1_SIMDHP_SHIFT              20
1280 #define MVFR1_SIMDHP_MASK               (UL(0xf) << MVFR1_SIMDHP_SHIFT)
1281 #define MVFR1_SIMDHP_VAL(x)             ((x) & MVFR1_SIMDHP_MASK)
1282 #define  MVFR1_SIMDHP_NONE              (UL(0x0) << MVFR1_SIMDHP_SHIFT)
1283 #define  MVFR1_SIMDHP_CONV_SP           (UL(0x1) << MVFR1_SIMDHP_SHIFT)
1284 #define  MVFR1_SIMDHP_ARITH             (UL(0x2) << MVFR1_SIMDHP_SHIFT)
1285 #define MVFR1_FPHP_SHIFT                24
1286 #define MVFR1_FPHP_MASK                 (UL(0xf) << MVFR1_FPHP_SHIFT)
1287 #define MVFR1_FPHP_VAL(x)               ((x) & MVFR1_FPHP_MASK)
1288 #define  MVFR1_FPHP_NONE                (UL(0x0) << MVFR1_FPHP_SHIFT)
1289 #define  MVFR1_FPHP_CONV_SP             (UL(0x1) << MVFR1_FPHP_SHIFT)
1290 #define  MVFR1_FPHP_CONV_DP             (UL(0x2) << MVFR1_FPHP_SHIFT)
1291 #define  MVFR1_FPHP_ARITH               (UL(0x3) << MVFR1_FPHP_SHIFT)
1292 #define MVFR1_SIMDFMAC_SHIFT            28
1293 #define MVFR1_SIMDFMAC_MASK             (UL(0xf) << MVFR1_SIMDFMAC_SHIFT)
1294 #define MVFR1_SIMDFMAC_VAL(x)           ((x) & MVFR1_SIMDFMAC_MASK)
1295 #define  MVFR1_SIMDFMAC_NONE            (UL(0x0) << MVFR1_SIMDFMAC_SHIFT)
1296 #define  MVFR1_SIMDFMAC_IMPL            (UL(0x1) << MVFR1_SIMDFMAC_SHIFT)
1297
1298 /* OSDLR_EL1 */
1299 #define OSDLR_EL1                       MRS_REG(OSDLR_EL1)
1300 #define OSDLR_EL1_op0                   2
1301 #define OSDLR_EL1_op1                   0
1302 #define OSDLR_EL1_CRn                   1
1303 #define OSDLR_EL1_CRm                   3
1304 #define OSDLR_EL1_op2                   4
1305
1306 /* OSLAR_EL1 */
1307 #define OSLAR_EL1                       MRS_REG(OSLAR_EL1)
1308 #define OSLAR_EL1_op0                   2
1309 #define OSLAR_EL1_op1                   0
1310 #define OSLAR_EL1_CRn                   1
1311 #define OSLAR_EL1_CRm                   0
1312 #define OSLAR_EL1_op2                   4
1313
1314 /* OSLSR_EL1 */
1315 #define OSLSR_EL1                       MRS_REG(OSLSR_EL1)
1316 #define OSLSR_EL1_op0                   2
1317 #define OSLSR_EL1_op1                   0
1318 #define OSLSR_EL1_CRn                   1
1319 #define OSLSR_EL1_CRm                   1
1320 #define OSLSR_EL1_op2                   4
1321
1322 /* PAR_EL1 - Physical Address Register */
1323 #define PAR_F_SHIFT             0
1324 #define PAR_F                   (0x1 << PAR_F_SHIFT)
1325 #define PAR_SUCCESS(x)          (((x) & PAR_F) == 0)
1326 /* When PAR_F == 0 (success) */
1327 #define PAR_LOW_MASK            0xfff
1328 #define PAR_SH_SHIFT            7
1329 #define PAR_SH_MASK             (0x3 << PAR_SH_SHIFT)
1330 #define PAR_NS_SHIFT            9
1331 #define PAR_NS_MASK             (0x3 << PAR_NS_SHIFT)
1332 #define PAR_PA_SHIFT            12
1333 #define PAR_PA_MASK             0x0000fffffffff000
1334 #define PAR_ATTR_SHIFT          56
1335 #define PAR_ATTR_MASK           (0xff << PAR_ATTR_SHIFT)
1336 /* When PAR_F == 1 (aborted) */
1337 #define PAR_FST_SHIFT           1
1338 #define PAR_FST_MASK            (0x3f << PAR_FST_SHIFT)
1339 #define PAR_PTW_SHIFT           8
1340 #define PAR_PTW_MASK            (0x1 << PAR_PTW_SHIFT)
1341 #define PAR_S_SHIFT             9
1342 #define PAR_S_MASK              (0x1 << PAR_S_SHIFT)
1343
1344 /* PMBIDR_EL1 */
1345 #define PMBIDR_EL1                      MRS_REG(PMBIDR_EL1)
1346 #define PMBIDR_EL1_op0                  0x3
1347 #define PMBIDR_EL1_op1                  0x0
1348 #define PMBIDR_EL1_CRn                  0x9
1349 #define PMBIDR_EL1_CRm                  0xa
1350 #define PMBIDR_EL1_op2                  0x7
1351 #define PMBIDR_Align_SHIFT              0
1352 #define PMBIDR_Align_MASK               (UL(0xf) << PMBIDR_Align_SHIFT)
1353 #define PMBIDR_P_SHIFT                  4
1354 #define PMBIDR_P                        (UL(0x1) << PMBIDR_P_SHIFT)
1355 #define PMBIDR_F_SHIFT                  5
1356 #define PMBIDR_F                        (UL(0x1) << PMBIDR_F_SHIFT)
1357
1358 /* PMBLIMITR_EL1 */
1359 #define PMBLIMITR_EL1                   MRS_REG(PMBLIMITR_EL1)
1360 #define PMBLIMITR_EL1_op0               0x3
1361 #define PMBLIMITR_EL1_op1               0x0
1362 #define PMBLIMITR_EL1_CRn               0x9
1363 #define PMBLIMITR_EL1_CRm               0xa
1364 #define PMBLIMITR_EL1_op2               0x0
1365 #define PMBLIMITR_E_SHIFT               0
1366 #define PMBLIMITR_E                     (UL(0x1) << PMBLIMITR_E_SHIFT)
1367 #define PMBLIMITR_FM_SHIFT              1
1368 #define PMBLIMITR_FM_MASK               (UL(0x3) << PMBLIMITR_FM_SHIFT)
1369 #define PMBLIMITR_PMFZ_SHIFT            5
1370 #define PMBLIMITR_PMFZ                  (UL(0x1) << PMBLIMITR_PMFZ_SHIFT)
1371 #define PMBLIMITR_LIMIT_SHIFT           12
1372 #define PMBLIMITR_LIMIT_MASK            \
1373     (UL(0xfffffffffffff) << PMBLIMITR_LIMIT_SHIFT)
1374
1375 /* PMBPTR_EL1 */
1376 #define PMBPTR_EL1                      MRS_REG(PMBPTR_EL1)
1377 #define PMBPTR_EL1_op0                  0x3
1378 #define PMBPTR_EL1_op1                  0x0
1379 #define PMBPTR_EL1_CRn                  0x9
1380 #define PMBPTR_EL1_CRm                  0xa
1381 #define PMBPTR_EL1_op2                  0x1
1382 #define PMBPTR_PTR_SHIFT                0
1383 #define PMBPTR_PTR_MASK                 \
1384     (UL(0xffffffffffffffff) << PMBPTR_PTR_SHIFT)
1385
1386 /* PMBSR_EL1 */
1387 #define PMBSR_EL1                       MRS_REG(PMBSR_EL1)
1388 #define PMBSR_EL1_op0                   0x3
1389 #define PMBSR_EL1_op1                   0x0
1390 #define PMBSR_EL1_CRn                   0x9
1391 #define PMBSR_EL1_CRm                   0xa
1392 #define PMBSR_EL1_op2                   0x3
1393 #define PMBSR_MSS_SHIFT                 0
1394 #define PMBSR_MSS_MASK                  (UL(0xffff) << PMBSR_MSS_SHIFT)
1395 #define PMBSR_COLL_SHIFT                16
1396 #define PMBSR_COLL                      (UL(0x1) << PMBSR_COLL_SHIFT)
1397 #define PMBSR_S_SHIFT                   17
1398 #define PMBSR_S                         (UL(0x1) << PMBSR_S_SHIFT)
1399 #define PMBSR_EA_SHIFT                  18
1400 #define PMBSR_EA                        (UL(0x1) << PMBSR_EA_SHIFT)
1401 #define PMBSR_DL_SHIFT                  19
1402 #define PMBSR_DL                        (UL(0x1) << PMBSR_DL_SHIFT)
1403 #define PMBSR_EC_SHIFT                  26
1404 #define PMBSR_EC_MASK                   (UL(0x3f) << PMBSR_EC_SHIFT)
1405
1406 /* PMCCFILTR_EL0 */
1407 #define PMCCFILTR_EL0                   MRS_REG(PMCCFILTR_EL0)
1408 #define PMCCFILTR_EL0_op0               3
1409 #define PMCCFILTR_EL0_op1               3
1410 #define PMCCFILTR_EL0_CRn               14
1411 #define PMCCFILTR_EL0_CRm               15
1412 #define PMCCFILTR_EL0_op2               7
1413
1414 /* PMCCNTR_EL0 */
1415 #define PMCCNTR_EL0                     MRS_REG(PMCCNTR_EL0)
1416 #define PMCCNTR_EL0_op0                 3
1417 #define PMCCNTR_EL0_op1                 3
1418 #define PMCCNTR_EL0_CRn                 9
1419 #define PMCCNTR_EL0_CRm                 13
1420 #define PMCCNTR_EL0_op2                 0
1421
1422 /* PMCEID0_EL0 */
1423 #define PMCEID0_EL0                     MRS_REG(PMCEID0_EL0)
1424 #define PMCEID0_EL0_op0                 3
1425 #define PMCEID0_EL0_op1                 3
1426 #define PMCEID0_EL0_CRn                 9
1427 #define PMCEID0_EL0_CRm                 12
1428 #define PMCEID0_EL0_op2                 6
1429
1430 /* PMCEID1_EL0 */
1431 #define PMCEID1_EL0                     MRS_REG(PMCEID1_EL0)
1432 #define PMCEID1_EL0_op0                 3
1433 #define PMCEID1_EL0_op1                 3
1434 #define PMCEID1_EL0_CRn                 9
1435 #define PMCEID1_EL0_CRm                 12
1436 #define PMCEID1_EL0_op2                 7
1437
1438 /* PMCNTENCLR_EL0 */
1439 #define PMCNTENCLR_EL0                  MRS_REG(PMCNTENCLR_EL0)
1440 #define PMCNTENCLR_EL0_op0              3
1441 #define PMCNTENCLR_EL0_op1              3
1442 #define PMCNTENCLR_EL0_CRn              9
1443 #define PMCNTENCLR_EL0_CRm              12
1444 #define PMCNTENCLR_EL0_op2              2
1445
1446 /* PMCNTENSET_EL0 */
1447 #define PMCNTENSET_EL0                  MRS_REG(PMCNTENSET_EL0)
1448 #define PMCNTENSET_EL0_op0              3
1449 #define PMCNTENSET_EL0_op1              3
1450 #define PMCNTENSET_EL0_CRn              9
1451 #define PMCNTENSET_EL0_CRm              12
1452 #define PMCNTENSET_EL0_op2              1
1453
1454 /* PMCR_EL0 - Perfomance Monitoring Counters */
1455 #define PMCR_EL0                        MRS_REG(PMCR_EL0)
1456 #define PMCR_EL0_op0                    3
1457 #define PMCR_EL0_op1                    3
1458 #define PMCR_EL0_CRn                    9
1459 #define PMCR_EL0_CRm                    12
1460 #define PMCR_EL0_op2                    0
1461 #define PMCR_E                          (1 << 0) /* Enable all counters */
1462 #define PMCR_P                          (1 << 1) /* Reset all counters */
1463 #define PMCR_C                          (1 << 2) /* Clock counter reset */
1464 #define PMCR_D                          (1 << 3) /* CNTR counts every 64 clk cycles */
1465 #define PMCR_X                          (1 << 4) /* Export to ext. monitoring (ETM) */
1466 #define PMCR_DP                         (1 << 5) /* Disable CCNT if non-invasive debug*/
1467 #define PMCR_LC                         (1 << 6) /* Long cycle count enable */
1468 #define PMCR_IMP_SHIFT                  24      /* Implementer code */
1469 #define PMCR_IMP_MASK                   (0xff << PMCR_IMP_SHIFT)
1470 #define  PMCR_IMP_ARM                   0x41
1471 #define PMCR_IDCODE_SHIFT               16      /* Identification code */
1472 #define PMCR_IDCODE_MASK                (0xff << PMCR_IDCODE_SHIFT)
1473 #define  PMCR_IDCODE_CORTEX_A57         0x01
1474 #define  PMCR_IDCODE_CORTEX_A72         0x02
1475 #define  PMCR_IDCODE_CORTEX_A53         0x03
1476 #define  PMCR_IDCODE_CORTEX_A73         0x04
1477 #define  PMCR_IDCODE_CORTEX_A35         0x0a
1478 #define  PMCR_IDCODE_CORTEX_A76         0x0b
1479 #define  PMCR_IDCODE_NEOVERSE_N1        0x0c
1480 #define  PMCR_IDCODE_CORTEX_A77         0x10
1481 #define  PMCR_IDCODE_CORTEX_A55         0x45
1482 #define  PMCR_IDCODE_NEOVERSE_E1        0x46
1483 #define  PMCR_IDCODE_CORTEX_A75         0x4a
1484 #define PMCR_N_SHIFT                    11  /* Number of counters implemented */
1485 #define PMCR_N_MASK                     (0x1f << PMCR_N_SHIFT)
1486
1487 /* PMEVCNTR<n>_EL0 */
1488 #define PMEVCNTR_EL0_op0                3
1489 #define PMEVCNTR_EL0_op1                3
1490 #define PMEVCNTR_EL0_CRn                14
1491 #define PMEVCNTR_EL0_CRm                8
1492 /*
1493  * PMEVCNTRn_EL0_CRm[1:0] holds the upper 2 bits of 'n'
1494  * PMEVCNTRn_EL0_op2 holds the lower 3 bits of 'n'
1495  */
1496
1497 /* PMEVTYPER<n>_EL0 - Performance Monitoring Event Type */
1498 #define PMEVTYPER_EL0_op0               3
1499 #define PMEVTYPER_EL0_op1               3
1500 #define PMEVTYPER_EL0_CRn               14
1501 #define PMEVTYPER_EL0_CRm               12
1502 /*
1503  * PMEVTYPERn_EL0_CRm[1:0] holds the upper 2 bits of 'n'
1504  * PMEVTYPERn_EL0_op2 holds the lower 3 bits of 'n'
1505  */
1506 #define PMEVTYPER_EVTCOUNT_MASK         0x000003ff /* ARMv8.0 */
1507 #define PMEVTYPER_EVTCOUNT_8_1_MASK     0x0000ffff /* ARMv8.1+ */
1508 #define PMEVTYPER_MT                    (1 << 25) /* Multithreading */
1509 #define PMEVTYPER_M                     (1 << 26) /* Secure EL3 filtering */
1510 #define PMEVTYPER_NSH                   (1 << 27) /* Non-secure hypervisor filtering */
1511 #define PMEVTYPER_NSU                   (1 << 28) /* Non-secure user filtering */
1512 #define PMEVTYPER_NSK                   (1 << 29) /* Non-secure kernel filtering */
1513 #define PMEVTYPER_U                     (1 << 30) /* User filtering */
1514 #define PMEVTYPER_P                     (1 << 31) /* Privileged filtering */
1515
1516 /* PMINTENCLR_EL1 */
1517 #define PMINTENCLR_EL1                  MRS_REG(PMINTENCLR_EL1)
1518 #define PMINTENCLR_EL1_op0              3
1519 #define PMINTENCLR_EL1_op1              0
1520 #define PMINTENCLR_EL1_CRn              9
1521 #define PMINTENCLR_EL1_CRm              14
1522 #define PMINTENCLR_EL1_op2              2
1523
1524 /* PMINTENSET_EL1 */
1525 #define PMINTENSET_EL1                  MRS_REG(PMINTENSET_EL1)
1526 #define PMINTENSET_EL1_op0              3
1527 #define PMINTENSET_EL1_op1              0
1528 #define PMINTENSET_EL1_CRn              9
1529 #define PMINTENSET_EL1_CRm              14
1530 #define PMINTENSET_EL1_op2              1
1531
1532 /* PMMIR_EL1 */
1533 #define PMMIR_EL1                       MRS_REG(PMMIR_EL1)
1534 #define PMMIR_EL1_op0                   3
1535 #define PMMIR_EL1_op1                   0
1536 #define PMMIR_EL1_CRn                   9
1537 #define PMMIR_EL1_CRm                   14
1538 #define PMMIR_EL1_op2                   6
1539
1540 /* PMOVSCLR_EL0 */
1541 #define PMOVSCLR_EL0                    MRS_REG(PMOVSCLR_EL0)
1542 #define PMOVSCLR_EL0_op0                3
1543 #define PMOVSCLR_EL0_op1                3
1544 #define PMOVSCLR_EL0_CRn                9
1545 #define PMOVSCLR_EL0_CRm                12
1546 #define PMOVSCLR_EL0_op2                3
1547
1548 /* PMOVSSET_EL0 */
1549 #define PMOVSSET_EL0                    MRS_REG(PMOVSSET_EL0)
1550 #define PMOVSSET_EL0_op0                3
1551 #define PMOVSSET_EL0_op1                3
1552 #define PMOVSSET_EL0_CRn                9
1553 #define PMOVSSET_EL0_CRm                14
1554 #define PMOVSSET_EL0_op2                3
1555
1556 /* PMSCR_EL1 */
1557 #define PMSCR_EL1                       MRS_REG(PMSCR_EL1)
1558 #define PMSCR_EL1_op0                   0x3
1559 #define PMSCR_EL1_op1                   0x0
1560 #define PMSCR_EL1_CRn                   0x9
1561 #define PMSCR_EL1_CRm                   0x9
1562 #define PMSCR_EL1_op2                   0x0
1563 #define PMSCR_E0SPE_SHIFT               0
1564 #define PMSCR_E0SPE                     (UL(0x1) << PMSCR_E0SPE_SHIFT)
1565 #define PMSCR_E1SPE_SHIFT               1
1566 #define PMSCR_E1SPE                     (UL(0x1) << PMSCR_E1SPE_SHIFT)
1567 #define PMSCR_CX_SHIFT                  3
1568 #define PMSCR_CX                        (UL(0x1) << PMSCR_CX_SHIFT)
1569 #define PMSCR_PA_SHIFT                  4
1570 #define PMSCR_PA                        (UL(0x1) << PMSCR_PA_SHIFT)
1571 #define PMSCR_TS_SHIFT                  5
1572 #define PMSCR_TS                        (UL(0x1) << PMSCR_TS_SHIFT)
1573 #define PMSCR_PCT_SHIFT                 6
1574 #define PMSCR_PCT_MASK                  (UL(0x3) << PMSCR_PCT_SHIFT)
1575
1576 /* PMSELR_EL0 */
1577 #define PMSELR_EL0                      MRS_REG(PMSELR_EL0)
1578 #define PMSELR_EL0_op0                  3
1579 #define PMSELR_EL0_op1                  3
1580 #define PMSELR_EL0_CRn                  9
1581 #define PMSELR_EL0_CRm                  12
1582 #define PMSELR_EL0_op2                  5
1583 #define PMSELR_SEL_MASK                 0x1f
1584
1585 /* PMSEVFR_EL1 */
1586 #define PMSEVFR_EL1                     MRS_REG(PMSEVFR_EL1)
1587 #define PMSEVFR_EL1_op0                 0x3
1588 #define PMSEVFR_EL1_op1                 0x0
1589 #define PMSEVFR_EL1_CRn                 0x9
1590 #define PMSEVFR_EL1_CRm                 0x9
1591 #define PMSEVFR_EL1_op2                 0x5
1592
1593 /* PMSFCR_EL1 */
1594 #define PMSFCR_EL1                      MRS_REG(PMSFCR_EL1)
1595 #define PMSFCR_EL1_op0                  0x3
1596 #define PMSFCR_EL1_op1                  0x0
1597 #define PMSFCR_EL1_CRn                  0x9
1598 #define PMSFCR_EL1_CRm                  0x9
1599 #define PMSFCR_EL1_op2                  0x4
1600 #define PMSFCR_FE_SHIFT                 0
1601 #define PMSFCR_FE                       (UL(0x1) << PMSFCR_FE_SHIFT)
1602 #define PMSFCR_FT_SHIFT                 1
1603 #define PMSFCR_FT                       (UL(0x1) << PMSFCR_FT_SHIFT)
1604 #define PMSFCR_FL_SHIFT                 2
1605 #define PMSFCR_FL                       (UL(0x1) << PMSFCR_FL_SHIFT)
1606 #define PMSFCR_FnE_SHIFT                3
1607 #define PMSFCR_FnE                      (UL(0x1) << PMSFCR_FnE_SHIFT)
1608 #define PMSFCR_B_SHIFT                  16
1609 #define PMSFCR_B                        (UL(0x1) << PMSFCR_B_SHIFT)
1610 #define PMSFCR_LD_SHIFT                 17
1611 #define PMSFCR_LD                       (UL(0x1) << PMSFCR_LD_SHIFT)
1612 #define PMSFCR_ST_SHIFT                 18
1613 #define PMSFCR_ST                       (UL(0x1) << PMSFCR_ST_SHIFT)
1614
1615 /* PMSICR_EL1 */
1616 #define PMSICR_EL1                      MRS_REG(PMSICR_EL1)
1617 #define PMSICR_EL1_op0                  0x3
1618 #define PMSICR_EL1_op1                  0x0
1619 #define PMSICR_EL1_CRn                  0x9
1620 #define PMSICR_EL1_CRm                  0x9
1621 #define PMSICR_EL1_op2                  0x2
1622 #define PMSICR_COUNT_SHIFT              0
1623 #define PMSICR_COUNT_MASK               (UL(0xffffffff) << PMSICR_COUNT_SHIFT)
1624 #define PMSICR_ECOUNT_SHIFT             56
1625 #define PMSICR_ECOUNT_MASK              (UL(0xff) << PMSICR_ECOUNT_SHIFT)
1626
1627 /* PMSIDR_EL1 */
1628 #define PMSIDR_EL1                      MRS_REG(PMSIDR_EL1)
1629 #define PMSIDR_EL1_op0                  0x3
1630 #define PMSIDR_EL1_op1                  0x0
1631 #define PMSIDR_EL1_CRn                  0x9
1632 #define PMSIDR_EL1_CRm                  0x9
1633 #define PMSIDR_EL1_op2                  0x7
1634 #define PMSIDR_FE_SHIFT                 0
1635 #define PMSIDR_FE                       (UL(0x1) << PMSIDR_FE_SHIFT)
1636 #define PMSIDR_FT_SHIFT                 1
1637 #define PMSIDR_FT                       (UL(0x1) << PMSIDR_FT_SHIFT)
1638 #define PMSIDR_FL_SHIFT                 2
1639 #define PMSIDR_FL                       (UL(0x1) << PMSIDR_FL_SHIFT)
1640 #define PMSIDR_ArchInst_SHIFT           3
1641 #define PMSIDR_ArchInst                 (UL(0x1) << PMSIDR_ArchInst_SHIFT)
1642 #define PMSIDR_LDS_SHIFT                4
1643 #define PMSIDR_LDS                      (UL(0x1) << PMSIDR_LDS_SHIFT)
1644 #define PMSIDR_ERnd_SHIFT               5
1645 #define PMSIDR_ERnd                     (UL(0x1) << PMSIDR_ERnd_SHIFT)
1646 #define PMSIDR_FnE_SHIFT                6
1647 #define PMSIDR_FnE                      (UL(0x1) << PMSIDR_FnE_SHIFT)
1648 #define PMSIDR_Interval_SHIFT           8
1649 #define PMSIDR_Interval_MASK            (UL(0xf) << PMSIDR_Interval_SHIFT)
1650 #define PMSIDR_MaxSize_SHIFT            12
1651 #define PMSIDR_MaxSize_MASK             (UL(0xf) << PMSIDR_MaxSize_SHIFT)
1652 #define PMSIDR_CountSize_SHIFT          16
1653 #define PMSIDR_CountSize_MASK           (UL(0xf) << PMSIDR_CountSize_SHIFT)
1654 #define PMSIDR_Format_SHIFT             20
1655 #define PMSIDR_Format_MASK              (UL(0xf) << PMSIDR_Format_SHIFT)
1656 #define PMSIDR_PBT_SHIFT                24
1657 #define PMSIDR_PBT                      (UL(0x1) << PMSIDR_PBT_SHIFT)
1658
1659 /* PMSIRR_EL1 */
1660 #define PMSIRR_EL1                      MRS_REG(PMSIRR_EL1)
1661 #define PMSIRR_EL1_op0                  0x3
1662 #define PMSIRR_EL1_op1                  0x0
1663 #define PMSIRR_EL1_CRn                  0x9
1664 #define PMSIRR_EL1_CRm                  0x9
1665 #define PMSIRR_EL1_op2                  0x3
1666 #define PMSIRR_RND_SHIFT                0
1667 #define PMSIRR_RND                      (UL(0x1) << PMSIRR_RND_SHIFT)
1668 #define PMSIRR_INTERVAL_SHIFT           8
1669 #define PMSIRR_INTERVAL_MASK            (UL(0xffffff) << PMSIRR_INTERVAL_SHIFT)
1670
1671 /* PMSLATFR_EL1 */
1672 #define PMSLATFR_EL1                    MRS_REG(PMSLATFR_EL1)
1673 #define PMSLATFR_EL1_op0                0x3
1674 #define PMSLATFR_EL1_op1                0x0
1675 #define PMSLATFR_EL1_CRn                0x9
1676 #define PMSLATFR_EL1_CRm                0x9
1677 #define PMSLATFR_EL1_op2                0x6
1678 #define PMSLATFR_MINLAT_SHIFT           0
1679 #define PMSLATFR_MINLAT_MASK            (UL(0xfff) << PMSLATFR_MINLAT_SHIFT)
1680
1681 /* PMSNEVFR_EL1 */
1682 #define PMSNEVFR_EL1                    MRS_REG(PMSNEVFR_EL1)
1683 #define PMSNEVFR_EL1_op0                0x3
1684 #define PMSNEVFR_EL1_op1                0x0
1685 #define PMSNEVFR_EL1_CRn                0x9
1686 #define PMSNEVFR_EL1_CRm                0x9
1687 #define PMSNEVFR_EL1_op2                0x1
1688
1689 /* PMSWINC_EL0 */
1690 #define PMSWINC_EL0                     MRS_REG(PMSWINC_EL0)
1691 #define PMSWINC_EL0_op0                 3
1692 #define PMSWINC_EL0_op1                 3
1693 #define PMSWINC_EL0_CRn                 9
1694 #define PMSWINC_EL0_CRm                 12
1695 #define PMSWINC_EL0_op2                 4
1696
1697 /* PMUSERENR_EL0 */
1698 #define PMUSERENR_EL0                   MRS_REG(PMUSERENR_EL0)
1699 #define PMUSERENR_EL0_op0               3
1700 #define PMUSERENR_EL0_op1               3
1701 #define PMUSERENR_EL0_CRn               9
1702 #define PMUSERENR_EL0_CRm               14
1703 #define PMUSERENR_EL0_op2               0
1704
1705 /* PMXEVCNTR_EL0 */
1706 #define PMXEVCNTR_EL0                   MRS_REG(PMXEVCNTR_EL0)
1707 #define PMXEVCNTR_EL0_op0               3
1708 #define PMXEVCNTR_EL0_op1               3
1709 #define PMXEVCNTR_EL0_CRn               9
1710 #define PMXEVCNTR_EL0_CRm               13
1711 #define PMXEVCNTR_EL0_op2               2
1712
1713 /* PMXEVTYPER_EL0 */
1714 #define PMXEVTYPER_EL0                  MRS_REG(PMXEVTYPER_EL0)
1715 #define PMXEVTYPER_EL0_op0              3
1716 #define PMXEVTYPER_EL0_op1              3
1717 #define PMXEVTYPER_EL0_CRn              9
1718 #define PMXEVTYPER_EL0_CRm              13
1719 #define PMXEVTYPER_EL0_op2              1
1720
1721 /* SCTLR_EL1 - System Control Register */
1722 #define SCTLR_RES1      0x30d00800      /* Reserved ARMv8.0, write 1 */
1723 #define SCTLR_M                         (UL(0x1) << 0)
1724 #define SCTLR_A                         (UL(0x1) << 1)
1725 #define SCTLR_C                         (UL(0x1) << 2)
1726 #define SCTLR_SA                        (UL(0x1) << 3)
1727 #define SCTLR_SA0                       (UL(0x1) << 4)
1728 #define SCTLR_CP15BEN                   (UL(0x1) << 5)
1729 #define SCTLR_nAA                       (UL(0x1) << 6)
1730 #define SCTLR_ITD                       (UL(0x1) << 7)
1731 #define SCTLR_SED                       (UL(0x1) << 8)
1732 #define SCTLR_UMA                       (UL(0x1) << 9)
1733 #define SCTLR_EnRCTX                    (UL(0x1) << 10)
1734 #define SCTLR_EOS                       (UL(0x1) << 11)
1735 #define SCTLR_I                         (UL(0x1) << 12)
1736 #define SCTLR_EnDB                      (UL(0x1) << 13)
1737 #define SCTLR_DZE                       (UL(0x1) << 14)
1738 #define SCTLR_UCT                       (UL(0x1) << 15)
1739 #define SCTLR_nTWI                      (UL(0x1) << 16)
1740 /* Bit 17 is reserved */
1741 #define SCTLR_nTWE                      (UL(0x1) << 18)
1742 #define SCTLR_WXN                       (UL(0x1) << 19)
1743 #define SCTLR_TSCXT                     (UL(0x1) << 20)
1744 #define SCTLR_IESB                      (UL(0x1) << 21)
1745 #define SCTLR_EIS                       (UL(0x1) << 22)
1746 #define SCTLR_SPAN                      (UL(0x1) << 23)
1747 #define SCTLR_E0E                       (UL(0x1) << 24)
1748 #define SCTLR_EE                        (UL(0x1) << 25)
1749 #define SCTLR_UCI                       (UL(0x1) << 26)
1750 #define SCTLR_EnDA                      (UL(0x1) << 27)
1751 #define SCTLR_nTLSMD                    (UL(0x1) << 28)
1752 #define SCTLR_LSMAOE                    (UL(0x1) << 29)
1753 #define SCTLR_EnIB                      (UL(0x1) << 30)
1754 #define SCTLR_EnIA                      (UL(0x1) << 31)
1755 /* Bits 34:32 are reserved */
1756 #define SCTLR_BT0                       (UL(0x1) << 35)
1757 #define SCTLR_BT1                       (UL(0x1) << 36)
1758 #define SCTLR_ITFSB                     (UL(0x1) << 37)
1759 #define SCTLR_TCF0_MASK                 (UL(0x3) << 38)
1760 #define SCTLR_TCF_MASK                  (UL(0x3) << 40)
1761 #define SCTLR_ATA0                      (UL(0x1) << 42)
1762 #define SCTLR_ATA                       (UL(0x1) << 43)
1763 #define SCTLR_DSSBS                     (UL(0x1) << 44)
1764 #define SCTLR_TWEDEn                    (UL(0x1) << 45)
1765 #define SCTLR_TWEDEL_MASK               (UL(0xf) << 46)
1766 /* Bits 53:50 are reserved */
1767 #define SCTLR_EnASR                     (UL(0x1) << 54)
1768 #define SCTLR_EnAS0                     (UL(0x1) << 55)
1769 #define SCTLR_EnALS                     (UL(0x1) << 56)
1770 #define SCTLR_EPAN                      (UL(0x1) << 57)
1771
1772 /* SPSR_EL1 */
1773 /*
1774  * When the exception is taken in AArch64:
1775  * M[3:2] is the exception level
1776  * M[1]   is unused
1777  * M[0]   is the SP select:
1778  *         0: always SP0
1779  *         1: current ELs SP
1780  */
1781 #define PSR_M_EL0t      0x00000000
1782 #define PSR_M_EL1t      0x00000004
1783 #define PSR_M_EL1h      0x00000005
1784 #define PSR_M_EL2t      0x00000008
1785 #define PSR_M_EL2h      0x00000009
1786 #define PSR_M_64        0x00000000
1787 #define PSR_M_32        0x00000010
1788 #define PSR_M_MASK      0x0000000f
1789
1790 #define PSR_T           0x00000020
1791
1792 #define PSR_AARCH32     0x00000010
1793 #define PSR_F           0x00000040
1794 #define PSR_I           0x00000080
1795 #define PSR_A           0x00000100
1796 #define PSR_D           0x00000200
1797 #define PSR_DAIF        (PSR_D | PSR_A | PSR_I | PSR_F)
1798 /* The default DAIF mask. These bits are valid in spsr_el1 and daif */
1799 #define PSR_DAIF_DEFAULT (PSR_F)
1800 #define PSR_IL          0x00100000
1801 #define PSR_SS          0x00200000
1802 #define PSR_V           0x10000000
1803 #define PSR_C           0x20000000
1804 #define PSR_Z           0x40000000
1805 #define PSR_N           0x80000000
1806 #define PSR_FLAGS       0xf0000000
1807 /* PSR fields that can be set from 32-bit and 64-bit processes */
1808 #define PSR_SETTABLE_32 PSR_FLAGS
1809 #define PSR_SETTABLE_64 (PSR_FLAGS | PSR_SS)
1810
1811 /* TCR_EL1 - Translation Control Register */
1812 /* Bits 63:59 are reserved */
1813 #define TCR_TCMA1_SHIFT         58
1814 #define TCR_TCMA1               (1UL << TCR_TCMA1_SHIFT)
1815 #define TCR_TCMA0_SHIFT         57
1816 #define TCR_TCMA0               (1UL << TCR_TCMA0_SHIFT)
1817 #define TCR_E0PD1_SHIFT         56
1818 #define TCR_E0PD1               (1UL << TCR_E0PD1_SHIFT)
1819 #define TCR_E0PD0_SHIFT         55
1820 #define TCR_E0PD0               (1UL << TCR_E0PD0_SHIFT)
1821 #define TCR_NFD1_SHIFT          54
1822 #define TCR_NFD1                (1UL << TCR_NFD1_SHIFT)
1823 #define TCR_NFD0_SHIFT          53
1824 #define TCR_NFD0                (1UL << TCR_NFD0_SHIFT)
1825 #define TCR_TBID1_SHIFT         52
1826 #define TCR_TBID1               (1UL << TCR_TBID1_SHIFT)
1827 #define TCR_TBID0_SHIFT         51
1828 #define TCR_TBID0               (1UL << TCR_TBID0_SHIFT)
1829 #define TCR_HWU162_SHIFT        50
1830 #define TCR_HWU162              (1UL << TCR_HWU162_SHIFT)
1831 #define TCR_HWU161_SHIFT        49
1832 #define TCR_HWU161              (1UL << TCR_HWU161_SHIFT)
1833 #define TCR_HWU160_SHIFT        48
1834 #define TCR_HWU160              (1UL << TCR_HWU160_SHIFT)
1835 #define TCR_HWU159_SHIFT        47
1836 #define TCR_HWU159              (1UL << TCR_HWU159_SHIFT)
1837 #define TCR_HWU1                \
1838     (TCR_HWU159 | TCR_HWU160 | TCR_HWU161 | TCR_HWU162)
1839 #define TCR_HWU062_SHIFT        46
1840 #define TCR_HWU062              (1UL << TCR_HWU062_SHIFT)
1841 #define TCR_HWU061_SHIFT        45
1842 #define TCR_HWU061              (1UL << TCR_HWU061_SHIFT)
1843 #define TCR_HWU060_SHIFT        44
1844 #define TCR_HWU060              (1UL << TCR_HWU060_SHIFT)
1845 #define TCR_HWU059_SHIFT        43
1846 #define TCR_HWU059              (1UL << TCR_HWU059_SHIFT)
1847 #define TCR_HWU0                \
1848     (TCR_HWU059 | TCR_HWU060 | TCR_HWU061 | TCR_HWU062)
1849 #define TCR_HPD1_SHIFT          42
1850 #define TCR_HPD1                (1UL << TCR_HPD1_SHIFT)
1851 #define TCR_HPD0_SHIFT          41
1852 #define TCR_HPD0                (1UL << TCR_HPD0_SHIFT)
1853 #define TCR_HD_SHIFT            40
1854 #define TCR_HD                  (1UL << TCR_HD_SHIFT)
1855 #define TCR_HA_SHIFT            39
1856 #define TCR_HA                  (1UL << TCR_HA_SHIFT)
1857 #define TCR_TBI1_SHIFT          38
1858 #define TCR_TBI1                (1UL << TCR_TBI1_SHIFT)
1859 #define TCR_TBI0_SHIFT          37
1860 #define TCR_TBI0                (1U << TCR_TBI0_SHIFT)
1861 #define TCR_ASID_SHIFT          36
1862 #define TCR_ASID_WIDTH          1
1863 #define TCR_ASID_16             (1UL << TCR_ASID_SHIFT)
1864 /* Bit 35 is reserved */
1865 #define TCR_IPS_SHIFT           32
1866 #define TCR_IPS_WIDTH           3
1867 #define TCR_IPS_32BIT           (0UL << TCR_IPS_SHIFT)
1868 #define TCR_IPS_36BIT           (1UL << TCR_IPS_SHIFT)
1869 #define TCR_IPS_40BIT           (2UL << TCR_IPS_SHIFT)
1870 #define TCR_IPS_42BIT           (3UL << TCR_IPS_SHIFT)
1871 #define TCR_IPS_44BIT           (4UL << TCR_IPS_SHIFT)
1872 #define TCR_IPS_48BIT           (5UL << TCR_IPS_SHIFT)
1873 #define TCR_TG1_SHIFT           30
1874 #define TCR_TG1_16K             (1UL << TCR_TG1_SHIFT)
1875 #define TCR_TG1_4K              (2UL << TCR_TG1_SHIFT)
1876 #define TCR_TG1_64K             (3UL << TCR_TG1_SHIFT)
1877 #define TCR_SH1_SHIFT           28
1878 #define TCR_SH1_IS              (3UL << TCR_SH1_SHIFT)
1879 #define TCR_ORGN1_SHIFT         26
1880 #define TCR_ORGN1_WBWA          (1UL << TCR_ORGN1_SHIFT)
1881 #define TCR_IRGN1_SHIFT         24
1882 #define TCR_IRGN1_WBWA          (1UL << TCR_IRGN1_SHIFT)
1883 #define TCR_EPD1_SHIFT          23
1884 #define TCR_EPD1                (1UL << TCR_EPD1_SHIFT)
1885 #define TCR_A1_SHIFT            22
1886 #define TCR_A1                  (0x1UL << TCR_A1_SHIFT)
1887 #define TCR_T1SZ_SHIFT          16
1888 #define TCR_T1SZ(x)             ((x) << TCR_T1SZ_SHIFT)
1889 #define TCR_TG0_SHIFT           14
1890 #define TCR_TG0_4K              (0UL << TCR_TG0_SHIFT)
1891 #define TCR_TG0_64K             (1UL << TCR_TG0_SHIFT)
1892 #define TCR_TG0_16K             (2UL << TCR_TG0_SHIFT)
1893 #define TCR_SH0_SHIFT           12
1894 #define TCR_SH0_IS              (3UL << TCR_SH0_SHIFT)
1895 #define TCR_ORGN0_SHIFT         10
1896 #define TCR_ORGN0_WBWA          (1UL << TCR_ORGN0_SHIFT)
1897 #define TCR_IRGN0_SHIFT         8
1898 #define TCR_IRGN0_WBWA          (1UL << TCR_IRGN0_SHIFT)
1899 #define TCR_EPD0_SHIFT          7
1900 #define TCR_EPD0                (1UL << TCR_EPD1_SHIFT)
1901 /* Bit 6 is reserved */
1902 #define TCR_T0SZ_SHIFT          0
1903 #define TCR_T0SZ_MASK           0x3f
1904 #define TCR_T0SZ(x)             ((x) << TCR_T0SZ_SHIFT)
1905 #define TCR_TxSZ(x)             (TCR_T1SZ(x) | TCR_T0SZ(x))
1906
1907 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
1908                                 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
1909 #ifdef SMP
1910 #define TCR_SMP_ATTRS   (TCR_SH0_IS | TCR_SH1_IS)
1911 #else
1912 #define TCR_SMP_ATTRS   0
1913 #endif
1914
1915 /* TTBR0_EL1 & TTBR1_EL1 - Translation Table Base Register 0 & 1 */
1916 #define TTBR_ASID_SHIFT         48
1917 #define TTBR_ASID_MASK          (0xfffful << TTBR_ASID_SHIFT)
1918 #define TTBR_BADDR              0x0000fffffffffffeul
1919 #define TTBR_CnP_SHIFT          0
1920 #define TTBR_CnP                (1ul << TTBR_CnP_SHIFT)
1921
1922 /* ZCR_EL1 - SVE Control Register */
1923 #define ZCR_LEN_SHIFT           0
1924 #define ZCR_LEN_MASK            (0xf << ZCR_LEN_SHIFT)
1925 #define ZCR_LEN_BYTES(x)        ((((x) & ZCR_LEN_MASK) + 1) * 16)
1926
1927 #endif /* !_MACHINE_ARMREG_H_ */