sys/arm64/include/armreg.h

   1 /*-
   2  * Copyright (c) 2013, 2014 Andrew Turner
   3  * Copyright (c) 2015,2021 The FreeBSD Foundation
   4  *
   5  * Portions of this software were developed by Andrew Turner
   6  * under sponsorship from the FreeBSD Foundation.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  29
  30 #ifndef _MACHINE_ARMREG_H_
  31 #define _MACHINE_ARMREG_H_
  32
  33 #define INSN_SIZE               4
  34
  35 #define MRS_MASK                        0xfff00000
  36 #define MRS_VALUE                       0xd5300000
  37 #define MRS_SPECIAL(insn)               ((insn) & 0x000fffe0)
  38 #define MRS_REGISTER(insn)              ((insn) & 0x0000001f)
  39 #define  MRS_Op0_SHIFT                  19
  40 #define  MRS_Op0_MASK                   0x00080000
  41 #define  MRS_Op1_SHIFT                  16
  42 #define  MRS_Op1_MASK                   0x00070000
  43 #define  MRS_CRn_SHIFT                  12
  44 #define  MRS_CRn_MASK                   0x0000f000
  45 #define  MRS_CRm_SHIFT                  8
  46 #define  MRS_CRm_MASK                   0x00000f00
  47 #define  MRS_Op2_SHIFT                  5
  48 #define  MRS_Op2_MASK                   0x000000e0
  49 #define  MRS_Rt_SHIFT                   0
  50 #define  MRS_Rt_MASK                    0x0000001f
  51 #define __MRS_REG(op0, op1, crn, crm, op2)                              \
  52     (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) |              \
  53      ((crn) << MRS_CRn_SHIFT) | ((crm) << MRS_CRm_SHIFT) |              \
  54      ((op2) << MRS_Op2_SHIFT))
  55 #define MRS_REG(reg)                                                    \
  56     __MRS_REG(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2)
  57
  58 #define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)                     \
  59     S##op0##_##op1##_C##crn##_C##crm##_##op2
  60 #define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)                      \
  61     __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)
  62 #define MRS_REG_ALT_NAME(reg)                                           \
  63     _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2)
  64
  65
  66 #define READ_SPECIALREG(reg)                                            \
  67 ({      uint64_t _val;                                                  \
  68         __asm __volatile("mrs   %0, " __STRING(reg) : "=&r" (_val));    \
  69         _val;                                                           \
  70 })
  71 #define WRITE_SPECIALREG(reg, _val)                                     \
  72         __asm __volatile("msr   " __STRING(reg) ", %0" : : "r"((uint64_t)_val))
  73
  74 #define UL(x)   UINT64_C(x)
  75
  76 /* CCSIDR_EL1 - Cache Size ID Register */
  77 #define CCSIDR_NumSets_MASK     0x0FFFE000
  78 #define CCSIDR_NumSets64_MASK   0x00FFFFFF00000000
  79 #define CCSIDR_NumSets_SHIFT    13
  80 #define CCSIDR_NumSets64_SHIFT  32
  81 #define CCSIDR_Assoc_MASK       0x00001FF8
  82 #define CCSIDR_Assoc64_MASK     0x0000000000FFFFF8
  83 #define CCSIDR_Assoc_SHIFT      3
  84 #define CCSIDR_Assoc64_SHIFT    3
  85 #define CCSIDR_LineSize_MASK    0x7
  86 #define CCSIDR_NSETS(idr)                                               \
  87         (((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT)
  88 #define CCSIDR_ASSOC(idr)                                               \
  89         (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT)
  90 #define CCSIDR_NSETS_64(idr)                                            \
  91         (((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT)
  92 #define CCSIDR_ASSOC_64(idr)                                            \
  93         (((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT)
  94
  95 /* CLIDR_EL1 - Cache level ID register */
  96 #define CLIDR_CTYPE_MASK        0x7     /* Cache type mask bits */
  97 #define CLIDR_CTYPE_IO          0x1     /* Instruction only */
  98 #define CLIDR_CTYPE_DO          0x2     /* Data only */
  99 #define CLIDR_CTYPE_ID          0x3     /* Split instruction and data */
 100 #define CLIDR_CTYPE_UNIFIED     0x4     /* Unified */
 101
 102 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
 103 #define CNTHCTL_EVNTI_MASK      (0xf << 4) /* Bit to trigger event stream */
 104 #define CNTHCTL_EVNTDIR         (1 << 3) /* Control transition trigger bit */
 105 #define CNTHCTL_EVNTEN          (1 << 2) /* Enable event stream */
 106 #define CNTHCTL_EL1PCEN         (1 << 1) /* Allow EL0/1 physical timer access */
 107 #define CNTHCTL_EL1PCTEN        (1 << 0) /*Allow EL0/1 physical counter access*/
 108
 109 /* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */
 110 #define CNTP_CTL_EL0            MRS_REG(CNTP_CTL_EL0)
 111 #define CNTP_CTL_EL0_op0        3
 112 #define CNTP_CTL_EL0_op1        3
 113 #define CNTP_CTL_EL0_CRn        14
 114 #define CNTP_CTL_EL0_CRm        2
 115 #define CNTP_CTL_EL0_op2        1
 116 #define CNTP_CTL_ENABLE         (1 << 0)
 117 #define CNTP_CTL_IMASK          (1 << 1)
 118 #define CNTP_CTL_ISTATUS        (1 << 2)
 119
 120 /* CNTP_CVAL_EL0 - Counter-timer Physical Timer CompareValue register */
 121 #define CNTP_CVAL_EL0           MRS_REG(CNTP_CVAL_EL0)
 122 #define CNTP_CVAL_EL0_op0       3
 123 #define CNTP_CVAL_EL0_op1       3
 124 #define CNTP_CVAL_EL0_CRn       14
 125 #define CNTP_CVAL_EL0_CRm       2
 126 #define CNTP_CVAL_EL0_op2       2
 127
 128 /* CNTP_TVAL_EL0 - Counter-timer Physical Timer TimerValue register */
 129 #define CNTP_TVAL_EL0           MRS_REG(CNTP_TVAL_EL0)
 130 #define CNTP_TVAL_EL0_op0       3
 131 #define CNTP_TVAL_EL0_op1       3
 132 #define CNTP_TVAL_EL0_CRn       14
 133 #define CNTP_TVAL_EL0_CRm       2
 134 #define CNTP_TVAL_EL0_op2       0
 135
 136 /* CNTPCT_EL0 - Counter-timer Physical Count register */
 137 #define CNTPCT_EL0              MRS_REG(CNTPCT_EL0)
 138 #define CNTPCT_EL0_op0          3
 139 #define CNTPCT_EL0_op1          3
 140 #define CNTPCT_EL0_CRn          14
 141 #define CNTPCT_EL0_CRm          0
 142 #define CNTPCT_EL0_op2          1
 143
 144 /* CPACR_EL1 */
 145 #define CPACR_ZEN_MASK          (0x3 << 16)
 146 #define  CPACR_ZEN_TRAP_ALL1    (0x0 << 16) /* Traps from EL0 and EL1 */
 147 #define  CPACR_ZEN_TRAP_EL0     (0x1 << 16) /* Traps from EL0 */
 148 #define  CPACR_ZEN_TRAP_ALL2    (0x2 << 16) /* Traps from EL0 and EL1 */
 149 #define  CPACR_ZEN_TRAP_NONE    (0x3 << 16) /* No traps */
 150 #define CPACR_FPEN_MASK         (0x3 << 20)
 151 #define  CPACR_FPEN_TRAP_ALL1   (0x0 << 20) /* Traps from EL0 and EL1 */
 152 #define  CPACR_FPEN_TRAP_EL0    (0x1 << 20) /* Traps from EL0 */
 153 #define  CPACR_FPEN_TRAP_ALL2   (0x2 << 20) /* Traps from EL0 and EL1 */
 154 #define  CPACR_FPEN_TRAP_NONE   (0x3 << 20) /* No traps */
 155 #define CPACR_TTA               (0x1 << 28)
 156
 157 /* CSSELR_EL1 - Cache size selection register */
 158 #define CSSELR_Level(i)         (i << 1)
 159 #define CSSELR_InD              0x00000001
 160
 161 /* CTR_EL0 - Cache Type Register */
 162 #define CTR_RES1                (1 << 31)
 163 #define CTR_TminLine_SHIFT      32
 164 #define CTR_TminLine_MASK       (UL(0x3f) << CTR_TminLine_SHIFT)
 165 #define CTR_TminLine_VAL(reg)   ((reg) & CTR_TminLine_MASK)
 166 #define CTR_DIC_SHIFT           29
 167 #define CTR_DIC_MASK            (0x1 << CTR_DIC_SHIFT)
 168 #define CTR_DIC_VAL(reg)        ((reg) & CTR_DIC_MASK)
 169 #define CTR_IDC_SHIFT           28
 170 #define CTR_IDC_MASK            (0x1 << CTR_IDC_SHIFT)
 171 #define CTR_IDC_VAL(reg)        ((reg) & CTR_IDC_MASK)
 172 #define CTR_CWG_SHIFT           24
 173 #define CTR_CWG_MASK            (0xf << CTR_CWG_SHIFT)
 174 #define CTR_CWG_VAL(reg)        ((reg) & CTR_CWG_MASK)
 175 #define CTR_CWG_SIZE(reg)       (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT))
 176 #define CTR_ERG_SHIFT           20
 177 #define CTR_ERG_MASK            (0xf << CTR_ERG_SHIFT)
 178 #define CTR_ERG_VAL(reg)        ((reg) & CTR_ERG_MASK)
 179 #define CTR_ERG_SIZE(reg)       (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT))
 180 #define CTR_DLINE_SHIFT         16
 181 #define CTR_DLINE_MASK          (0xf << CTR_DLINE_SHIFT)
 182 #define CTR_DLINE_VAL(reg)      ((reg) & CTR_DLINE_MASK)
 183 #define CTR_DLINE_SIZE(reg)     (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT))
 184 #define CTR_L1IP_SHIFT          14
 185 #define CTR_L1IP_MASK           (0x3 << CTR_L1IP_SHIFT)
 186 #define CTR_L1IP_VAL(reg)       ((reg) & CTR_L1IP_MASK)
 187 #define  CTR_L1IP_VPIPT         (0 << CTR_L1IP_SHIFT)
 188 #define  CTR_L1IP_AIVIVT        (1 << CTR_L1IP_SHIFT)
 189 #define  CTR_L1IP_VIPT          (2 << CTR_L1IP_SHIFT)
 190 #define  CTR_L1IP_PIPT          (3 << CTR_L1IP_SHIFT)
 191 #define CTR_ILINE_SHIFT         0
 192 #define CTR_ILINE_MASK          (0xf << CTR_ILINE_SHIFT)
 193 #define CTR_ILINE_VAL(reg)      ((reg) & CTR_ILINE_MASK)
 194 #define CTR_ILINE_SIZE(reg)     (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT))
 195
 196 /* DAIFSet/DAIFClear */
 197 #define DAIF_D                  (1 << 3)
 198 #define DAIF_A                  (1 << 2)
 199 #define DAIF_I                  (1 << 1)
 200 #define DAIF_F                  (1 << 0)
 201 #define DAIF_ALL                (DAIF_D | DAIF_A | DAIF_I | DAIF_F)
 202 #define DAIF_INTR               (DAIF_I)        /* All exceptions that pass */
 203                                                 /* through the intr framework */
 204
 205 /* DBGBCR<n>_EL1 - Debug Breakpoint Control Registers */
 206 #define DBGBCR_EL1_op0          2
 207 #define DBGBCR_EL1_op1          0
 208 #define DBGBCR_EL1_CRn          0
 209 /* DBGBCR_EL1_CRm indicates which watchpoint this register is for */
 210 #define DBGBCR_EL1_op2          5
 211 #define DBGBCR_EN               0x1
 212 #define DBGBCR_PMC_SHIFT        1
 213 #define DBGBCR_PMC              (0x3 << DBGBCR_PMC_SHIFT)
 214 #define  DBGBCR_PMC_EL1         (0x1 << DBGBCR_PMC_SHIFT)
 215 #define  DBGBCR_PMC_EL0         (0x2 << DBGBCR_PMC_SHIFT)
 216 #define DBGBCR_BAS_SHIFT        5
 217 #define DBGBCR_BAS              (0xf << DBGBCR_BAS_SHIFT)
 218 #define DBGBCR_HMC_SHIFT        13
 219 #define DBGBCR_HMC              (0x1 << DBGBCR_HMC_SHIFT)
 220 #define DBGBCR_SSC_SHIFT        14
 221 #define DBGBCR_SSC              (0x3 << DBGBCR_SSC_SHIFT)
 222 #define DBGBCR_LBN_SHIFT        16
 223 #define DBGBCR_LBN              (0xf << DBGBCR_LBN_SHIFT)
 224 #define DBGBCR_BT_SHIFT         20
 225 #define DBGBCR_BT               (0xf << DBGBCR_BT_SHIFT)
 226
 227 /* DBGBVR<n>_EL1 - Debug Breakpoint Value Registers */
 228 #define DBGBVR_EL1_op0          2
 229 #define DBGBVR_EL1_op1          0
 230 #define DBGBVR_EL1_CRn          0
 231 /* DBGBVR_EL1_CRm indicates which watchpoint this register is for */
 232 #define DBGBVR_EL1_op2          4
 233
 234 /* DBGWCR<n>_EL1 - Debug Watchpoint Control Registers */
 235 #define DBGWCR_EL1_op0          2
 236 #define DBGWCR_EL1_op1          0
 237 #define DBGWCR_EL1_CRn          0
 238 /* DBGWCR_EL1_CRm indicates which watchpoint this register is for */
 239 #define DBGWCR_EL1_op2          7
 240 #define DBGWCR_EN               0x1
 241 #define DBGWCR_PAC_SHIFT        1
 242 #define DBGWCR_PAC              (0x3 << DBGWCR_PAC_SHIFT)
 243 #define  DBGWCR_PAC_EL1         (0x1 << DBGWCR_PAC_SHIFT)
 244 #define  DBGWCR_PAC_EL0         (0x2 << DBGWCR_PAC_SHIFT)
 245 #define DBGWCR_LSC_SHIFT        3
 246 #define DBGWCR_LSC              (0x3 << DBGWCR_LSC_SHIFT)
 247 #define DBGWCR_BAS_SHIFT        5
 248 #define DBGWCR_BAS              (0xff << DBGWCR_BAS_SHIFT)
 249 #define DBGWCR_HMC_SHIFT        13
 250 #define DBGWCR_HMC              (0x1 << DBGWCR_HMC_SHIFT)
 251 #define DBGWCR_SSC_SHIFT        14
 252 #define DBGWCR_SSC              (0x3 << DBGWCR_SSC_SHIFT)
 253 #define DBGWCR_LBN_SHIFT        16
 254 #define DBGWCR_LBN              (0xf << DBGWCR_LBN_SHIFT)
 255 #define DBGWCR_WT_SHIFT         20
 256 #define DBGWCR_WT               (0x1 << DBGWCR_WT_SHIFT)
 257 #define DBGWCR_MASK_SHIFT       24
 258 #define DBGWCR_MASK             (0x1f << DBGWCR_MASK_SHIFT)
 259
 260 /* DBGWVR<n>_EL1 - Debug Watchpoint Value Registers */
 261 #define DBGWVR_EL1_op0          2
 262 #define DBGWVR_EL1_op1          0
 263 #define DBGWVR_EL1_CRn          0
 264 /* DBGWVR_EL1_CRm indicates which watchpoint this register is for */
 265 #define DBGWVR_EL1_op2          6
 266
 267 /* DCZID_EL0 - Data Cache Zero ID register */
 268 #define DCZID_DZP               (1 << 4) /* DC ZVA prohibited if non-0 */
 269 #define DCZID_BS_SHIFT          0
 270 #define DCZID_BS_MASK           (0xf << DCZID_BS_SHIFT)
 271 #define DCZID_BS_SIZE(reg)      (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
 272
 273 /* DBGAUTHSTATUS_EL1 */
 274 #define DBGAUTHSTATUS_EL1               MRS_REG(DBGAUTHSTATUS_EL1)
 275 #define DBGAUTHSTATUS_EL1_op0           2
 276 #define DBGAUTHSTATUS_EL1_op1           0
 277 #define DBGAUTHSTATUS_EL1_CRn           7
 278 #define DBGAUTHSTATUS_EL1_CRm           14
 279 #define DBGAUTHSTATUS_EL1_op2           6
 280
 281 /* DBGCLAIMCLR_EL1 */
 282 #define DBGCLAIMCLR_EL1                 MRS_REG(DBGCLAIMCLR_EL1)
 283 #define DBGCLAIMCLR_EL1_op0             2
 284 #define DBGCLAIMCLR_EL1_op1             0
 285 #define DBGCLAIMCLR_EL1_CRn             7
 286 #define DBGCLAIMCLR_EL1_CRm             9
 287 #define DBGCLAIMCLR_EL1_op2             6
 288
 289 /* DBGCLAIMSET_EL1 */
 290 #define DBGCLAIMSET_EL1                 MRS_REG(DBGCLAIMSET_EL1)
 291 #define DBGCLAIMSET_EL1_op0             2
 292 #define DBGCLAIMSET_EL1_op1             0
 293 #define DBGCLAIMSET_EL1_CRn             7
 294 #define DBGCLAIMSET_EL1_CRm             8
 295 #define DBGCLAIMSET_EL1_op2             6
 296
 297 /* DBGPRCR_EL1 */
 298 #define DBGPRCR_EL1                     MRS_REG(DBGPRCR_EL1)
 299 #define DBGPRCR_EL1_op0                 2
 300 #define DBGPRCR_EL1_op1                 0
 301 #define DBGPRCR_EL1_CRn                 1
 302 #define DBGPRCR_EL1_CRm                 4
 303 #define DBGPRCR_EL1_op2                 4
 304
 305 /* ESR_ELx */
 306 #define ESR_ELx_ISS_MASK        0x01ffffff
 307 #define  ISS_FP_TFV_SHIFT       23
 308 #define  ISS_FP_TFV             (0x01 << ISS_FP_TFV_SHIFT)
 309 #define  ISS_FP_IOF             0x01
 310 #define  ISS_FP_DZF             0x02
 311 #define  ISS_FP_OFF             0x04
 312 #define  ISS_FP_UFF             0x08
 313 #define  ISS_FP_IXF             0x10
 314 #define  ISS_FP_IDF             0x80
 315 #define  ISS_INSN_FnV           (0x01 << 10)
 316 #define  ISS_INSN_EA            (0x01 << 9)
 317 #define  ISS_INSN_S1PTW         (0x01 << 7)
 318 #define  ISS_INSN_IFSC_MASK     (0x1f << 0)
 319
 320 #define  ISS_WFx_TI_SHIFT       0
 321 #define  ISS_WFx_TI_MASK        (0x03 << ISS_WFx_TI_SHIFT)
 322 #define  ISS_WFx_TI_WFI         (0x00 << ISS_WFx_TI_SHIFT)
 323 #define  ISS_WFx_TI_WFE         (0x01 << ISS_WFx_TI_SHIFT)
 324 #define  ISS_WFx_TI_WFIT        (0x02 << ISS_WFx_TI_SHIFT)
 325 #define  ISS_WFx_TI_WFET        (0x03 << ISS_WFx_TI_SHIFT)
 326 #define  ISS_WFx_RV_SHIFT       2
 327 #define  ISS_WFx_RV_MASK        (0x01 << ISS_WFx_RV_SHIFT)
 328 #define  ISS_WFx_RV_INVALID     (0x00 << ISS_WFx_RV_SHIFT)
 329 #define  ISS_WFx_RV_VALID       (0x01 << ISS_WFx_RV_SHIFT)
 330 #define  ISS_WFx_RN_SHIFT       5
 331 #define  ISS_WFx_RN_MASK        (0x1f << ISS_WFx_RN_SHIFT)
 332 #define  ISS_WFx_RN(x)          (((x) & ISS_WFx_RN_MASK) >> ISS_WFx_RN_SHIFT)
 333 #define  ISS_WFx_COND_SHIFT     20
 334 #define  ISS_WFx_COND_MASK      (0x0f << ISS_WFx_COND_SHIFT)
 335 #define  ISS_WFx_CV_SHIFT       24
 336 #define  ISS_WFx_CV_MASK        (0x01 << ISS_WFx_CV_SHIFT)
 337 #define  ISS_WFx_CV_INVALID     (0x00 << ISS_WFx_CV_SHIFT)
 338 #define  ISS_WFx_CV_VALID       (0x01 << ISS_WFx_CV_SHIFT)
 339
 340 #define  ISS_MSR_DIR_SHIFT      0
 341 #define  ISS_MSR_DIR            (0x01 << ISS_MSR_DIR_SHIFT)
 342 #define  ISS_MSR_Rt_SHIFT       5
 343 #define  ISS_MSR_Rt_MASK        (0x1f << ISS_MSR_Rt_SHIFT)
 344 #define  ISS_MSR_Rt(x)          (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT)
 345 #define  ISS_MSR_CRm_SHIFT      1
 346 #define  ISS_MSR_CRm_MASK       (0xf << ISS_MSR_CRm_SHIFT)
 347 #define  ISS_MSR_CRm(x)         (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT)
 348 #define  ISS_MSR_CRn_SHIFT      10
 349 #define  ISS_MSR_CRn_MASK       (0xf << ISS_MSR_CRn_SHIFT)
 350 #define  ISS_MSR_CRn(x)         (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT)
 351 #define  ISS_MSR_OP1_SHIFT      14
 352 #define  ISS_MSR_OP1_MASK       (0x7 << ISS_MSR_OP1_SHIFT)
 353 #define  ISS_MSR_OP1(x)         (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT)
 354 #define  ISS_MSR_OP2_SHIFT      17
 355 #define  ISS_MSR_OP2_MASK       (0x7 << ISS_MSR_OP2_SHIFT)
 356 #define  ISS_MSR_OP2(x)         (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT)
 357 #define  ISS_MSR_OP0_SHIFT      20
 358 #define  ISS_MSR_OP0_MASK       (0x3 << ISS_MSR_OP0_SHIFT)
 359 #define  ISS_MSR_OP0(x)         (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT)
 360 #define  ISS_MSR_REG_MASK       \
 361     (ISS_MSR_OP0_MASK | ISS_MSR_OP2_MASK | ISS_MSR_OP1_MASK |   \
 362      ISS_MSR_CRn_MASK | ISS_MSR_CRm_MASK)
 363
 364 #define  ISS_DATA_ISV_SHIFT     24
 365 #define  ISS_DATA_ISV           (0x01 << ISS_DATA_ISV_SHIFT)
 366 #define  ISS_DATA_SAS_SHIFT     22
 367 #define  ISS_DATA_SAS_MASK      (0x03 << ISS_DATA_SAS_SHIFT)
 368 #define  ISS_DATA_SSE_SHIFT     21
 369 #define  ISS_DATA_SSE           (0x01 << ISS_DATA_SSE_SHIFT)
 370 #define  ISS_DATA_SRT_SHIFT     16
 371 #define  ISS_DATA_SRT_MASK      (0x1f << ISS_DATA_SRT_SHIFT)
 372 #define  ISS_DATA_SF            (0x01 << 15)
 373 #define  ISS_DATA_AR            (0x01 << 14)
 374 #define  ISS_DATA_FnV           (0x01 << 10)
 375 #define  ISS_DATA_EA            (0x01 << 9)
 376 #define  ISS_DATA_CM            (0x01 << 8)
 377 #define  ISS_DATA_S1PTW         (0x01 << 7)
 378 #define  ISS_DATA_WnR_SHIFT     6
 379 #define  ISS_DATA_WnR           (0x01 << ISS_DATA_WnR_SHIFT)
 380 #define  ISS_DATA_DFSC_MASK     (0x3f << 0)
 381 #define  ISS_DATA_DFSC_ASF_L0   (0x00 << 0)
 382 #define  ISS_DATA_DFSC_ASF_L1   (0x01 << 0)
 383 #define  ISS_DATA_DFSC_ASF_L2   (0x02 << 0)
 384 #define  ISS_DATA_DFSC_ASF_L3   (0x03 << 0)
 385 #define  ISS_DATA_DFSC_TF_L0    (0x04 << 0)
 386 #define  ISS_DATA_DFSC_TF_L1    (0x05 << 0)
 387 #define  ISS_DATA_DFSC_TF_L2    (0x06 << 0)
 388 #define  ISS_DATA_DFSC_TF_L3    (0x07 << 0)
 389 #define  ISS_DATA_DFSC_AFF_L1   (0x09 << 0)
 390 #define  ISS_DATA_DFSC_AFF_L2   (0x0a << 0)
 391 #define  ISS_DATA_DFSC_AFF_L3   (0x0b << 0)
 392 #define  ISS_DATA_DFSC_PF_L1    (0x0d << 0)
 393 #define  ISS_DATA_DFSC_PF_L2    (0x0e << 0)
 394 #define  ISS_DATA_DFSC_PF_L3    (0x0f << 0)
 395 #define  ISS_DATA_DFSC_EXT      (0x10 << 0)
 396 #define  ISS_DATA_DFSC_EXT_L0   (0x14 << 0)
 397 #define  ISS_DATA_DFSC_EXT_L1   (0x15 << 0)
 398 #define  ISS_DATA_DFSC_EXT_L2   (0x16 << 0)
 399 #define  ISS_DATA_DFSC_EXT_L3   (0x17 << 0)
 400 #define  ISS_DATA_DFSC_ECC      (0x18 << 0)
 401 #define  ISS_DATA_DFSC_ECC_L0   (0x1c << 0)
 402 #define  ISS_DATA_DFSC_ECC_L1   (0x1d << 0)
 403 #define  ISS_DATA_DFSC_ECC_L2   (0x1e << 0)
 404 #define  ISS_DATA_DFSC_ECC_L3   (0x1f << 0)
 405 #define  ISS_DATA_DFSC_ALIGN    (0x21 << 0)
 406 #define  ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0)
 407 #define ESR_ELx_IL              (0x01 << 25)
 408 #define ESR_ELx_EC_SHIFT        26
 409 #define ESR_ELx_EC_MASK         (0x3f << 26)
 410 #define ESR_ELx_EXCEPTION(esr)  (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
 411 #define  EXCP_UNKNOWN           0x00    /* Unkwn exception */
 412 #define  EXCP_TRAP_WFI_WFE      0x01    /* Trapped WFI or WFE */
 413 #define  EXCP_FP_SIMD           0x07    /* VFP/SIMD trap */
 414 #define  EXCP_ILL_STATE         0x0e    /* Illegal execution state */
 415 #define  EXCP_SVC32             0x11    /* SVC trap for AArch32 */
 416 #define  EXCP_SVC64             0x15    /* SVC trap for AArch64 */
 417 #define  EXCP_HVC               0x16    /* HVC trap */
 418 #define  EXCP_MSR               0x18    /* MSR/MRS trap */
 419 #define  EXCP_SVE               0x19    /* SVE trap */
 420 #define  EXCP_FPAC              0x1c    /* Faulting PAC trap */
 421 #define  EXCP_INSN_ABORT_L      0x20    /* Instruction abort, from lower EL */
 422 #define  EXCP_INSN_ABORT        0x21    /* Instruction abort, from same EL */
 423 #define  EXCP_PC_ALIGN          0x22    /* PC alignment fault */
 424 #define  EXCP_DATA_ABORT_L      0x24    /* Data abort, from lower EL */
 425 #define  EXCP_DATA_ABORT        0x25    /* Data abort, from same EL */
 426 #define  EXCP_SP_ALIGN          0x26    /* SP slignment fault */
 427 #define  EXCP_TRAP_FP           0x2c    /* Trapped FP exception */
 428 #define  EXCP_SERROR            0x2f    /* SError interrupt */
 429 #define  EXCP_BRKPT_EL0         0x30    /* Hardware breakpoint, from same EL */
 430 #define  EXCP_SOFTSTP_EL0       0x32    /* Software Step, from lower EL */
 431 #define  EXCP_SOFTSTP_EL1       0x33    /* Software Step, from same EL */
 432 #define  EXCP_WATCHPT_EL0       0x34    /* Watchpoint, from lower EL */
 433 #define  EXCP_WATCHPT_EL1       0x35    /* Watchpoint, from same EL */
 434 #define  EXCP_BRKPT_32          0x38    /* 32bits breakpoint */
 435 #define  EXCP_BRK               0x3c    /* Breakpoint */
 436
 437 /* ICC_CTLR_EL1 */
 438 #define ICC_CTLR_EL1_EOIMODE    (1U << 1)
 439
 440 /* ICC_IAR1_EL1 */
 441 #define ICC_IAR1_EL1_SPUR       (0x03ff)
 442
 443 /* ICC_IGRPEN0_EL1 */
 444 #define ICC_IGRPEN0_EL1_EN      (1U << 0)
 445
 446 /* ICC_PMR_EL1 */
 447 #define ICC_PMR_EL1_PRIO_MASK   (0xFFUL)
 448
 449 /* ICC_SGI1R_EL1 */
 450 #define ICC_SGI1R_EL1                   MRS_REG(ICC_SGI1R_EL1)
 451 #define ICC_SGI1R_EL1_op0               3
 452 #define ICC_SGI1R_EL1_op1               0
 453 #define ICC_SGI1R_EL1_CRn               12
 454 #define ICC_SGI1R_EL1_CRm               11
 455 #define ICC_SGI1R_EL1_op2               5
 456 #define ICC_SGI1R_EL1_TL_SHIFT          0
 457 #define ICC_SGI1R_EL1_TL_MASK           (0xffffUL << ICC_SGI1R_EL1_TL_SHIFT)
 458 #define ICC_SGI1R_EL1_TL_VAL(x)         ((x) & ICC_SGI1R_EL1_TL_MASK)
 459 #define ICC_SGI1R_EL1_AFF1_SHIFT        16
 460 #define ICC_SGI1R_EL1_AFF1_MASK         (0xfful << ICC_SGI1R_EL1_AFF1_SHIFT)
 461 #define ICC_SGI1R_EL1_AFF1_VAL(x)       ((x) & ICC_SGI1R_EL1_AFF1_MASK)
 462 #define ICC_SGI1R_EL1_SGIID_SHIFT       24
 463 #define ICC_SGI1R_EL1_SGIID_MASK        (0xfUL << ICC_SGI1R_EL1_SGIID_SHIFT)
 464 #define ICC_SGI1R_EL1_SGIID_VAL(x)      ((x) & ICC_SGI1R_EL1_SGIID_MASK)
 465 #define ICC_SGI1R_EL1_AFF2_SHIFT        32
 466 #define ICC_SGI1R_EL1_AFF2_MASK         (0xfful << ICC_SGI1R_EL1_AFF2_SHIFT)
 467 #define ICC_SGI1R_EL1_AFF2_VAL(x)       ((x) & ICC_SGI1R_EL1_AFF2_MASK)
 468 #define ICC_SGI1R_EL1_RS_SHIFT          44
 469 #define ICC_SGI1R_EL1_RS_MASK           (0xful << ICC_SGI1R_EL1_RS_SHIFT)
 470 #define ICC_SGI1R_EL1_RS_VAL(x)         ((x) & ICC_SGI1R_EL1_RS_MASK)
 471 #define ICC_SGI1R_EL1_AFF3_SHIFT        48
 472 #define ICC_SGI1R_EL1_AFF3_MASK         (0xfful << ICC_SGI1R_EL1_AFF3_SHIFT)
 473 #define ICC_SGI1R_EL1_AFF3_VAL(x)       ((x) & ICC_SGI1R_EL1_AFF3_MASK)
 474 #define ICC_SGI1R_EL1_IRM               (0x1UL << 40)
 475
 476 /* ICC_SRE_EL1 */
 477 #define ICC_SRE_EL1_SRE         (1U << 0)
 478
 479 /* ID_AA64AFR0_EL1 */
 480 #define ID_AA64AFR0_EL1                 MRS_REG(ID_AA64AFR0_EL1)
 481 #define ID_AA64AFR0_EL1_op0             3
 482 #define ID_AA64AFR0_EL1_op1             0
 483 #define ID_AA64AFR0_EL1_CRn             0
 484 #define ID_AA64AFR0_EL1_CRm             5
 485 #define ID_AA64AFR0_EL1_op2             4
 486
 487 /* ID_AA64AFR1_EL1 */
 488 #define ID_AA64AFR1_EL1                 MRS_REG(ID_AA64AFR1_EL1)
 489 #define ID_AA64AFR1_EL1_op0             3
 490 #define ID_AA64AFR1_EL1_op1             0
 491 #define ID_AA64AFR1_EL1_CRn             0
 492 #define ID_AA64AFR1_EL1_CRm             5
 493 #define ID_AA64AFR1_EL1_op2             5
 494
 495 /* ID_AA64DFR0_EL1 */
 496 #define ID_AA64DFR0_EL1                 MRS_REG(ID_AA64DFR0_EL1)
 497 #define ID_AA64DFR0_EL1_op0             0x3
 498 #define ID_AA64DFR0_EL1_op1             0x0
 499 #define ID_AA64DFR0_EL1_CRn             0x0
 500 #define ID_AA64DFR0_EL1_CRm             0x5
 501 #define ID_AA64DFR0_EL1_op2             0x0
 502 #define ID_AA64DFR0_DebugVer_SHIFT      0
 503 #define ID_AA64DFR0_DebugVer_MASK       (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)
 504 #define ID_AA64DFR0_DebugVer_VAL(x)     ((x) & ID_AA64DFR0_DebugVer_MASK)
 505 #define  ID_AA64DFR0_DebugVer_8         (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT)
 506 #define  ID_AA64DFR0_DebugVer_8_VHE     (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT)
 507 #define  ID_AA64DFR0_DebugVer_8_2       (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT)
 508 #define  ID_AA64DFR0_DebugVer_8_4       (UL(0x9) << ID_AA64DFR0_DebugVer_SHIFT)
 509 #define ID_AA64DFR0_TraceVer_SHIFT      4
 510 #define ID_AA64DFR0_TraceVer_MASK       (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT)
 511 #define ID_AA64DFR0_TraceVer_VAL(x)     ((x) & ID_AA64DFR0_TraceVer_MASK)
 512 #define  ID_AA64DFR0_TraceVer_NONE      (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT)
 513 #define  ID_AA64DFR0_TraceVer_IMPL      (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT)
 514 #define ID_AA64DFR0_PMUVer_SHIFT        8
 515 #define ID_AA64DFR0_PMUVer_MASK         (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
 516 #define ID_AA64DFR0_PMUVer_VAL(x)       ((x) & ID_AA64DFR0_PMUVer_MASK)
 517 #define  ID_AA64DFR0_PMUVer_NONE        (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT)
 518 #define  ID_AA64DFR0_PMUVer_3           (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT)
 519 #define  ID_AA64DFR0_PMUVer_3_1         (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT)
 520 #define  ID_AA64DFR0_PMUVer_3_4         (UL(0x5) << ID_AA64DFR0_PMUVer_SHIFT)
 521 #define  ID_AA64DFR0_PMUVer_3_5         (UL(0x6) << ID_AA64DFR0_PMUVer_SHIFT)
 522 #define  ID_AA64DFR0_PMUVer_IMPL        (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
 523 #define ID_AA64DFR0_BRPs_SHIFT          12
 524 #define ID_AA64DFR0_BRPs_MASK           (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT)
 525 #define ID_AA64DFR0_BRPs_VAL(x) \
 526     ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1)
 527 #define ID_AA64DFR0_WRPs_SHIFT          20
 528 #define ID_AA64DFR0_WRPs_MASK           (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT)
 529 #define ID_AA64DFR0_WRPs_VAL(x) \
 530     ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1)
 531 #define ID_AA64DFR0_CTX_CMPs_SHIFT      28
 532 #define ID_AA64DFR0_CTX_CMPs_MASK       (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT)
 533 #define ID_AA64DFR0_CTX_CMPs_VAL(x)     \
 534     ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1)
 535 #define ID_AA64DFR0_PMSVer_SHIFT        32
 536 #define ID_AA64DFR0_PMSVer_MASK         (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT)
 537 #define ID_AA64DFR0_PMSVer_VAL(x)       ((x) & ID_AA64DFR0_PMSVer_MASK)
 538 #define  ID_AA64DFR0_PMSVer_NONE        (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT)
 539 #define  ID_AA64DFR0_PMSVer_SPE         (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT)
 540 #define  ID_AA64DFR0_PMSVer_SPE_8_3     (UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT)
 541 #define ID_AA64DFR0_DoubleLock_SHIFT    36
 542 #define ID_AA64DFR0_DoubleLock_MASK     (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT)
 543 #define ID_AA64DFR0_DoubleLock_VAL(x)   ((x) & ID_AA64DFR0_DoubleLock_MASK)
 544 #define  ID_AA64DFR0_DoubleLock_IMPL    (UL(0x0) << ID_AA64DFR0_DoubleLock_SHIFT)
 545 #define  ID_AA64DFR0_DoubleLock_NONE    (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT)
 546 #define ID_AA64DFR0_TraceFilt_SHIFT     40
 547 #define ID_AA64DFR0_TraceFilt_MASK      (UL(0xf) << ID_AA64DFR0_TraceFilt_SHIFT)
 548 #define ID_AA64DFR0_TraceFilt_VAL(x)    ((x) & ID_AA64DFR0_TraceFilt_MASK)
 549 #define  ID_AA64DFR0_TraceFilt_NONE     (UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT)
 550 #define  ID_AA64DFR0_TraceFilt_8_4      (UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT)
 551
 552 /* ID_AA64DFR1_EL1 */
 553 #define ID_AA64DFR1_EL1                 MRS_REG(ID_AA64DFR1_EL1)
 554 #define ID_AA64DFR1_EL1_op0             3
 555 #define ID_AA64DFR1_EL1_op1             0
 556 #define ID_AA64DFR1_EL1_CRn             0
 557 #define ID_AA64DFR1_EL1_CRm             5
 558 #define ID_AA64DFR1_EL1_op2             1
 559
 560 /* ID_AA64ISAR0_EL1 */
 561 #define ID_AA64ISAR0_EL1                MRS_REG(ID_AA64ISAR0_EL1)
 562 #define ID_AA64ISAR0_EL1_op0            0x3
 563 #define ID_AA64ISAR0_EL1_op1            0x0
 564 #define ID_AA64ISAR0_EL1_CRn            0x0
 565 #define ID_AA64ISAR0_EL1_CRm            0x6
 566 #define ID_AA64ISAR0_EL1_op2            0x0
 567 #define ID_AA64ISAR0_AES_SHIFT          4
 568 #define ID_AA64ISAR0_AES_MASK           (UL(0xf) << ID_AA64ISAR0_AES_SHIFT)
 569 #define ID_AA64ISAR0_AES_VAL(x)         ((x) & ID_AA64ISAR0_AES_MASK)
 570 #define  ID_AA64ISAR0_AES_NONE          (UL(0x0) << ID_AA64ISAR0_AES_SHIFT)
 571 #define  ID_AA64ISAR0_AES_BASE          (UL(0x1) << ID_AA64ISAR0_AES_SHIFT)
 572 #define  ID_AA64ISAR0_AES_PMULL         (UL(0x2) << ID_AA64ISAR0_AES_SHIFT)
 573 #define ID_AA64ISAR0_SHA1_SHIFT         8
 574 #define ID_AA64ISAR0_SHA1_MASK          (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT)
 575 #define ID_AA64ISAR0_SHA1_VAL(x)        ((x) & ID_AA64ISAR0_SHA1_MASK)
 576 #define  ID_AA64ISAR0_SHA1_NONE         (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT)
 577 #define  ID_AA64ISAR0_SHA1_BASE         (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT)
 578 #define ID_AA64ISAR0_SHA2_SHIFT         12
 579 #define ID_AA64ISAR0_SHA2_MASK          (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT)
 580 #define ID_AA64ISAR0_SHA2_VAL(x)        ((x) & ID_AA64ISAR0_SHA2_MASK)
 581 #define  ID_AA64ISAR0_SHA2_NONE         (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT)
 582 #define  ID_AA64ISAR0_SHA2_BASE         (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT)
 583 #define  ID_AA64ISAR0_SHA2_512          (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT)
 584 #define ID_AA64ISAR0_CRC32_SHIFT        16
 585 #define ID_AA64ISAR0_CRC32_MASK         (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT)
 586 #define ID_AA64ISAR0_CRC32_VAL(x)       ((x) & ID_AA64ISAR0_CRC32_MASK)
 587 #define  ID_AA64ISAR0_CRC32_NONE        (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT)
 588 #define  ID_AA64ISAR0_CRC32_BASE        (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT)
 589 #define ID_AA64ISAR0_Atomic_SHIFT       20
 590 #define ID_AA64ISAR0_Atomic_MASK        (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT)
 591 #define ID_AA64ISAR0_Atomic_VAL(x)      ((x) & ID_AA64ISAR0_Atomic_MASK)
 592 #define  ID_AA64ISAR0_Atomic_NONE       (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT)
 593 #define  ID_AA64ISAR0_Atomic_IMPL       (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT)
 594 #define ID_AA64ISAR0_RDM_SHIFT          28
 595 #define ID_AA64ISAR0_RDM_MASK           (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT)
 596 #define ID_AA64ISAR0_RDM_VAL(x)         ((x) & ID_AA64ISAR0_RDM_MASK)
 597 #define  ID_AA64ISAR0_RDM_NONE          (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT)
 598 #define  ID_AA64ISAR0_RDM_IMPL          (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT)
 599 #define ID_AA64ISAR0_SHA3_SHIFT         32
 600 #define ID_AA64ISAR0_SHA3_MASK          (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT)
 601 #define ID_AA64ISAR0_SHA3_VAL(x)        ((x) & ID_AA64ISAR0_SHA3_MASK)
 602 #define  ID_AA64ISAR0_SHA3_NONE         (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT)
 603 #define  ID_AA64ISAR0_SHA3_IMPL         (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT)
 604 #define ID_AA64ISAR0_SM3_SHIFT          36
 605 #define ID_AA64ISAR0_SM3_MASK           (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT)
 606 #define ID_AA64ISAR0_SM3_VAL(x)         ((x) & ID_AA64ISAR0_SM3_MASK)
 607 #define  ID_AA64ISAR0_SM3_NONE          (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT)
 608 #define  ID_AA64ISAR0_SM3_IMPL          (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT)
 609 #define ID_AA64ISAR0_SM4_SHIFT          40
 610 #define ID_AA64ISAR0_SM4_MASK           (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT)
 611 #define ID_AA64ISAR0_SM4_VAL(x)         ((x) & ID_AA64ISAR0_SM4_MASK)
 612 #define  ID_AA64ISAR0_SM4_NONE          (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT)
 613 #define  ID_AA64ISAR0_SM4_IMPL          (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT)
 614 #define ID_AA64ISAR0_DP_SHIFT           44
 615 #define ID_AA64ISAR0_DP_MASK            (UL(0xf) << ID_AA64ISAR0_DP_SHIFT)
 616 #define ID_AA64ISAR0_DP_VAL(x)          ((x) & ID_AA64ISAR0_DP_MASK)
 617 #define  ID_AA64ISAR0_DP_NONE           (UL(0x0) << ID_AA64ISAR0_DP_SHIFT)
 618 #define  ID_AA64ISAR0_DP_IMPL           (UL(0x1) << ID_AA64ISAR0_DP_SHIFT)
 619 #define ID_AA64ISAR0_FHM_SHIFT          48
 620 #define ID_AA64ISAR0_FHM_MASK           (UL(0xf) << ID_AA64ISAR0_FHM_SHIFT)
 621 #define ID_AA64ISAR0_FHM_VAL(x)         ((x) & ID_AA64ISAR0_FHM_MASK)
 622 #define  ID_AA64ISAR0_FHM_NONE          (UL(0x0) << ID_AA64ISAR0_FHM_SHIFT)
 623 #define  ID_AA64ISAR0_FHM_IMPL          (UL(0x1) << ID_AA64ISAR0_FHM_SHIFT)
 624 #define ID_AA64ISAR0_TS_SHIFT           52
 625 #define ID_AA64ISAR0_TS_MASK            (UL(0xf) << ID_AA64ISAR0_TS_SHIFT)
 626 #define ID_AA64ISAR0_TS_VAL(x)          ((x) & ID_AA64ISAR0_TS_MASK)
 627 #define  ID_AA64ISAR0_TS_NONE           (UL(0x0) << ID_AA64ISAR0_TS_SHIFT)
 628 #define  ID_AA64ISAR0_TS_CondM_8_4      (UL(0x1) << ID_AA64ISAR0_TS_SHIFT)
 629 #define  ID_AA64ISAR0_TS_CondM_8_5      (UL(0x2) << ID_AA64ISAR0_TS_SHIFT)
 630 #define ID_AA64ISAR0_TLB_SHIFT          56
 631 #define ID_AA64ISAR0_TLB_MASK           (UL(0xf) << ID_AA64ISAR0_TLB_SHIFT)
 632 #define ID_AA64ISAR0_TLB_VAL(x)         ((x) & ID_AA64ISAR0_TLB_MASK)
 633 #define  ID_AA64ISAR0_TLB_NONE          (UL(0x0) << ID_AA64ISAR0_TLB_SHIFT)
 634 #define  ID_AA64ISAR0_TLB_TLBIOS        (UL(0x1) << ID_AA64ISAR0_TLB_SHIFT)
 635 #define  ID_AA64ISAR0_TLB_TLBIOSR       (UL(0x2) << ID_AA64ISAR0_TLB_SHIFT)
 636 #define ID_AA64ISAR0_RNDR_SHIFT         60
 637 #define ID_AA64ISAR0_RNDR_MASK          (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT)
 638 #define ID_AA64ISAR0_RNDR_VAL(x)        ((x) & ID_AA64ISAR0_RNDR_MASK)
 639 #define  ID_AA64ISAR0_RNDR_NONE         (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT)
 640 #define  ID_AA64ISAR0_RNDR_IMPL         (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT)
 641
 642 /* ID_AA64ISAR1_EL1 */
 643 #define ID_AA64ISAR1_EL1                MRS_REG(ID_AA64ISAR1_EL1)
 644 #define ID_AA64ISAR1_EL1_op0            0x3
 645 #define ID_AA64ISAR1_EL1_op1            0x0
 646 #define ID_AA64ISAR1_EL1_CRn            0x0
 647 #define ID_AA64ISAR1_EL1_CRm            0x6
 648 #define ID_AA64ISAR1_EL1_op2            0x1
 649 #define ID_AA64ISAR1_DPB_SHIFT          0
 650 #define ID_AA64ISAR1_DPB_MASK           (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
 651 #define ID_AA64ISAR1_DPB_VAL(x)         ((x) & ID_AA64ISAR1_DPB_MASK)
 652 #define  ID_AA64ISAR1_DPB_NONE          (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT)
 653 #define  ID_AA64ISAR1_DPB_DCCVAP        (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT)
 654 #define  ID_AA64ISAR1_DPB_DCCVADP       (UL(0x2) << ID_AA64ISAR1_DPB_SHIFT)
 655 #define ID_AA64ISAR1_APA_SHIFT          4
 656 #define ID_AA64ISAR1_APA_MASK           (UL(0xf) << ID_AA64ISAR1_APA_SHIFT)
 657 #define ID_AA64ISAR1_APA_VAL(x)         ((x) & ID_AA64ISAR1_APA_MASK)
 658 #define  ID_AA64ISAR1_APA_NONE          (UL(0x0) << ID_AA64ISAR1_APA_SHIFT)
 659 #define  ID_AA64ISAR1_APA_PAC           (UL(0x1) << ID_AA64ISAR1_APA_SHIFT)
 660 #define  ID_AA64ISAR1_APA_EPAC          (UL(0x2) << ID_AA64ISAR1_APA_SHIFT)
 661 #define  ID_AA64ISAR1_APA_EPAC2         (UL(0x3) << ID_AA64ISAR1_APA_SHIFT)
 662 #define  ID_AA64ISAR1_APA_FPAC          (UL(0x4) << ID_AA64ISAR1_APA_SHIFT)
 663 #define  ID_AA64ISAR1_APA_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_APA_SHIFT)
 664 #define ID_AA64ISAR1_API_SHIFT          8
 665 #define ID_AA64ISAR1_API_MASK           (UL(0xf) << ID_AA64ISAR1_API_SHIFT)
 666 #define ID_AA64ISAR1_API_VAL(x)         ((x) & ID_AA64ISAR1_API_MASK)
 667 #define  ID_AA64ISAR1_API_NONE          (UL(0x0) << ID_AA64ISAR1_API_SHIFT)
 668 #define  ID_AA64ISAR1_API_PAC           (UL(0x1) << ID_AA64ISAR1_API_SHIFT)
 669 #define  ID_AA64ISAR1_API_EPAC          (UL(0x2) << ID_AA64ISAR1_API_SHIFT)
 670 #define  ID_AA64ISAR1_API_EPAC2         (UL(0x3) << ID_AA64ISAR1_API_SHIFT)
 671 #define  ID_AA64ISAR1_API_FPAC          (UL(0x4) << ID_AA64ISAR1_API_SHIFT)
 672 #define  ID_AA64ISAR1_API_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_API_SHIFT)
 673 #define ID_AA64ISAR1_JSCVT_SHIFT        12
 674 #define ID_AA64ISAR1_JSCVT_MASK         (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT)
 675 #define ID_AA64ISAR1_JSCVT_VAL(x)       ((x) & ID_AA64ISAR1_JSCVT_MASK)
 676 #define  ID_AA64ISAR1_JSCVT_NONE        (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT)
 677 #define  ID_AA64ISAR1_JSCVT_IMPL        (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT)
 678 #define ID_AA64ISAR1_FCMA_SHIFT         16
 679 #define ID_AA64ISAR1_FCMA_MASK          (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT)
 680 #define ID_AA64ISAR1_FCMA_VAL(x)        ((x) & ID_AA64ISAR1_FCMA_MASK)
 681 #define  ID_AA64ISAR1_FCMA_NONE         (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT)
 682 #define  ID_AA64ISAR1_FCMA_IMPL         (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT)
 683 #define ID_AA64ISAR1_LRCPC_SHIFT        20
 684 #define ID_AA64ISAR1_LRCPC_MASK         (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT)
 685 #define ID_AA64ISAR1_LRCPC_VAL(x)       ((x) & ID_AA64ISAR1_LRCPC_MASK)
 686 #define  ID_AA64ISAR1_LRCPC_NONE        (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT)
 687 #define  ID_AA64ISAR1_LRCPC_RCPC_8_3    (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT)
 688 #define  ID_AA64ISAR1_LRCPC_RCPC_8_4    (UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT)
 689 #define ID_AA64ISAR1_GPA_SHIFT          24
 690 #define ID_AA64ISAR1_GPA_MASK           (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT)
 691 #define ID_AA64ISAR1_GPA_VAL(x)         ((x) & ID_AA64ISAR1_GPA_MASK)
 692 #define  ID_AA64ISAR1_GPA_NONE          (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT)
 693 #define  ID_AA64ISAR1_GPA_IMPL          (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT)
 694 #define ID_AA64ISAR1_GPI_SHIFT          28
 695 #define ID_AA64ISAR1_GPI_MASK           (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT)
 696 #define ID_AA64ISAR1_GPI_VAL(x)         ((x) & ID_AA64ISAR1_GPI_MASK)
 697 #define  ID_AA64ISAR1_GPI_NONE          (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT)
 698 #define  ID_AA64ISAR1_GPI_IMPL          (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT)
 699 #define ID_AA64ISAR1_FRINTTS_SHIFT      32
 700 #define ID_AA64ISAR1_FRINTTS_MASK       (UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT)
 701 #define ID_AA64ISAR1_FRINTTS_VAL(x)     ((x) & ID_AA64ISAR1_FRINTTS_MASK)
 702 #define  ID_AA64ISAR1_FRINTTS_NONE      (UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT)
 703 #define  ID_AA64ISAR1_FRINTTS_IMPL      (UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT)
 704 #define ID_AA64ISAR1_SB_SHIFT           36
 705 #define ID_AA64ISAR1_SB_MASK            (UL(0xf) << ID_AA64ISAR1_SB_SHIFT)
 706 #define ID_AA64ISAR1_SB_VAL(x)          ((x) & ID_AA64ISAR1_SB_MASK)
 707 #define  ID_AA64ISAR1_SB_NONE           (UL(0x0) << ID_AA64ISAR1_SB_SHIFT)
 708 #define  ID_AA64ISAR1_SB_IMPL           (UL(0x1) << ID_AA64ISAR1_SB_SHIFT)
 709 #define ID_AA64ISAR1_SPECRES_SHIFT      40
 710 #define ID_AA64ISAR1_SPECRES_MASK       (UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT)
 711 #define ID_AA64ISAR1_SPECRES_VAL(x)     ((x) & ID_AA64ISAR1_SPECRES_MASK)
 712 #define  ID_AA64ISAR1_SPECRES_NONE      (UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT)
 713 #define  ID_AA64ISAR1_SPECRES_IMPL      (UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT)
 714 #define ID_AA64ISAR1_BF16_SHIFT         44
 715 #define ID_AA64ISAR1_BF16_MASK          (UL(0xf) << ID_AA64ISAR1_BF16_SHIFT)
 716 #define ID_AA64ISAR1_BF16_VAL(x)        ((x) & ID_AA64ISAR1_BF16_MASK)
 717 #define  ID_AA64ISAR1_BF16_NONE         (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT)
 718 #define  ID_AA64ISAR1_BF16_IMPL         (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT)
 719 #define ID_AA64ISAR1_DGH_SHIFT          48
 720 #define ID_AA64ISAR1_DGH_MASK           (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT)
 721 #define ID_AA64ISAR1_DGH_VAL(x)         ((x) & ID_AA64ISAR1_DGH_MASK)
 722 #define  ID_AA64ISAR1_DGH_NONE          (UL(0x0) << ID_AA64ISAR1_DGH_SHIFT)
 723 #define  ID_AA64ISAR1_DGH_IMPL          (UL(0x1) << ID_AA64ISAR1_DGH_SHIFT)
 724 #define ID_AA64ISAR1_I8MM_SHIFT         52
 725 #define ID_AA64ISAR1_I8MM_MASK          (UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT)
 726 #define ID_AA64ISAR1_I8MM_VAL(x)        ((x) & ID_AA64ISAR1_I8MM_MASK)
 727 #define  ID_AA64ISAR1_I8MM_NONE         (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT)
 728 #define  ID_AA64ISAR1_I8MM_IMPL         (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT)
 729
 730 /* ID_AA64ISAR2_EL1 */
 731 #define ID_AA64ISAR2_EL1                MRS_REG(ID_AA64ISAR2_EL1)
 732 #define ID_AA64ISAR2_EL1_op0            3
 733 #define ID_AA64ISAR2_EL1_op1            0
 734 #define ID_AA64ISAR2_EL1_CRn            0
 735 #define ID_AA64ISAR2_EL1_CRm            6
 736 #define ID_AA64ISAR2_EL1_op2            2
 737 #define ID_AA64ISAR2_WFxT_SHIFT         0
 738 #define ID_AA64ISAR2_WFxT_MASK          (UL(0xf) << ID_AA64ISAR2_WFxT_SHIFT)
 739 #define ID_AA64ISAR2_WFxT_VAL(x)        ((x) & ID_AA64ISAR2_WFxT_MASK)
 740 #define  ID_AA64ISAR2_WFxT_NONE         (UL(0x0) << ID_AA64ISAR2_WFxT_SHIFT)
 741 #define  ID_AA64ISAR2_WFxT_IMPL         (UL(0x1) << ID_AA64ISAR2_WFxT_SHIFT)
 742 #define ID_AA64ISAR2_RPRES_SHIFT        4
 743 #define ID_AA64ISAR2_RPRES_MASK         (UL(0xf) << ID_AA64ISAR2_RPRES_SHIFT)
 744 #define ID_AA64ISAR2_RPRES_VAL(x)       ((x) & ID_AA64ISAR2_RPRES_MASK)
 745 #define  ID_AA64ISAR2_RPRES_NONE        (UL(0x0) << ID_AA64ISAR2_RPRES_SHIFT)
 746 #define  ID_AA64ISAR2_RPRES_IMPL        (UL(0x1) << ID_AA64ISAR2_RPRES_SHIFT)
 747 #define ID_AA64ISAR2_GPA3_SHIFT         8
 748 #define ID_AA64ISAR2_GPA3_MASK          (UL(0xf) << ID_AA64ISAR2_GPA3_SHIFT)
 749 #define ID_AA64ISAR2_GPA3_VAL(x)        ((x) & ID_AA64ISAR2_GPA3_MASK)
 750 #define  ID_AA64ISAR2_GPA3_NONE         (UL(0x0) << ID_AA64ISAR2_GPA3_SHIFT)
 751 #define  ID_AA64ISAR2_GPA3_IMPL         (UL(0x1) << ID_AA64ISAR2_GPA3_SHIFT)
 752 #define ID_AA64ISAR2_APA3_SHIFT         12
 753 #define ID_AA64ISAR2_APA3_MASK          (UL(0xf) << ID_AA64ISAR2_APA3_SHIFT)
 754 #define ID_AA64ISAR2_APA3_VAL(x)        ((x) & ID_AA64ISAR2_APA3_MASK)
 755 #define  ID_AA64ISAR2_APA3_NONE         (UL(0x0) << ID_AA64ISAR2_APA3_SHIFT)
 756 #define  ID_AA64ISAR2_APA3_PAC          (UL(0x1) << ID_AA64ISAR2_APA3_SHIFT)
 757 #define  ID_AA64ISAR2_APA3_EPAC         (UL(0x2) << ID_AA64ISAR2_APA3_SHIFT)
 758 #define  ID_AA64ISAR2_APA3_EPAC2        (UL(0x3) << ID_AA64ISAR2_APA3_SHIFT)
 759 #define  ID_AA64ISAR2_APA3_FPAC         (UL(0x4) << ID_AA64ISAR2_APA3_SHIFT)
 760 #define  ID_AA64ISAR2_APA3_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR2_APA3_SHIFT)
 761 #define ID_AA64ISAR2_MOPS_SHIFT         16
 762 #define ID_AA64ISAR2_MOPS_MASK          (UL(0xf) << ID_AA64ISAR2_MOPS_SHIFT)
 763 #define ID_AA64ISAR2_MOPS_VAL(x)        ((x) & ID_AA64ISAR2_MOPS_MASK)
 764 #define  ID_AA64ISAR2_MOPS_NONE         (UL(0x0) << ID_AA64ISAR2_MOPS_SHIFT)
 765 #define  ID_AA64ISAR2_MOPS_IMPL         (UL(0x1) << ID_AA64ISAR2_MOPS_SHIFT)
 766 #define ID_AA64ISAR2_BC_SHIFT           20
 767 #define ID_AA64ISAR2_BC_MASK            (UL(0xf) << ID_AA64ISAR2_BC_SHIFT)
 768 #define ID_AA64ISAR2_BC_VAL(x)          ((x) & ID_AA64ISAR2_BC_MASK)
 769 #define  ID_AA64ISAR2_BC_NONE           (UL(0x0) << ID_AA64ISAR2_BC_SHIFT)
 770 #define  ID_AA64ISAR2_BC_IMPL           (UL(0x1) << ID_AA64ISAR2_BC_SHIFT)
 771 #define ID_AA64ISAR2_PAC_frac_SHIFT     28
 772 #define ID_AA64ISAR2_PAC_frac_MASK      (UL(0xf) << ID_AA64ISAR2_PAC_frac_SHIFT)
 773 #define ID_AA64ISAR2_PAC_frac_VAL(x)    ((x) & ID_AA64ISAR2_PAC_frac_MASK)
 774 #define  ID_AA64ISAR2_PAC_frac_NONE     (UL(0x0) << ID_AA64ISAR2_PAC_frac_SHIFT)
 775 #define  ID_AA64ISAR2_PAC_frac_IMPL     (UL(0x1) << ID_AA64ISAR2_PAC_frac_SHIFT)
 776
 777 /* ID_AA64MMFR0_EL1 */
 778 #define ID_AA64MMFR0_EL1                MRS_REG(ID_AA64MMFR0_EL1)
 779 #define ID_AA64MMFR0_EL1_op0            0x3
 780 #define ID_AA64MMFR0_EL1_op1            0x0
 781 #define ID_AA64MMFR0_EL1_CRn            0x0
 782 #define ID_AA64MMFR0_EL1_CRm            0x7
 783 #define ID_AA64MMFR0_EL1_op2            0x0
 784 #define ID_AA64MMFR0_PARange_SHIFT      0
 785 #define ID_AA64MMFR0_PARange_MASK       (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
 786 #define ID_AA64MMFR0_PARange_VAL(x)     ((x) & ID_AA64MMFR0_PARange_MASK)
 787 #define  ID_AA64MMFR0_PARange_4G        (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT)
 788 #define  ID_AA64MMFR0_PARange_64G       (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT)
 789 #define  ID_AA64MMFR0_PARange_1T        (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT)
 790 #define  ID_AA64MMFR0_PARange_4T        (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT)
 791 #define  ID_AA64MMFR0_PARange_16T       (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT)
 792 #define  ID_AA64MMFR0_PARange_256T      (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT)
 793 #define  ID_AA64MMFR0_PARange_4P        (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT)
 794 #define ID_AA64MMFR0_ASIDBits_SHIFT     4
 795 #define ID_AA64MMFR0_ASIDBits_MASK      (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT)
 796 #define ID_AA64MMFR0_ASIDBits_VAL(x)    ((x) & ID_AA64MMFR0_ASIDBits_MASK)
 797 #define  ID_AA64MMFR0_ASIDBits_8        (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT)
 798 #define  ID_AA64MMFR0_ASIDBits_16       (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT)
 799 #define ID_AA64MMFR0_BigEnd_SHIFT       8
 800 #define ID_AA64MMFR0_BigEnd_MASK        (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT)
 801 #define ID_AA64MMFR0_BigEnd_VAL(x)      ((x) & ID_AA64MMFR0_BigEnd_MASK)
 802 #define  ID_AA64MMFR0_BigEnd_FIXED      (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT)
 803 #define  ID_AA64MMFR0_BigEnd_MIXED      (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT)
 804 #define ID_AA64MMFR0_SNSMem_SHIFT       12
 805 #define ID_AA64MMFR0_SNSMem_MASK        (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT)
 806 #define ID_AA64MMFR0_SNSMem_VAL(x)      ((x) & ID_AA64MMFR0_SNSMem_MASK)
 807 #define  ID_AA64MMFR0_SNSMem_NONE       (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT)
 808 #define  ID_AA64MMFR0_SNSMem_DISTINCT   (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT)
 809 #define ID_AA64MMFR0_BigEndEL0_SHIFT    16
 810 #define ID_AA64MMFR0_BigEndEL0_MASK     (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT)
 811 #define ID_AA64MMFR0_BigEndEL0_VAL(x)   ((x) & ID_AA64MMFR0_BigEndEL0_MASK)
 812 #define  ID_AA64MMFR0_BigEndEL0_FIXED   (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT)
 813 #define  ID_AA64MMFR0_BigEndEL0_MIXED   (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT)
 814 #define ID_AA64MMFR0_TGran16_SHIFT      20
 815 #define ID_AA64MMFR0_TGran16_MASK       (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT)
 816 #define ID_AA64MMFR0_TGran16_VAL(x)     ((x) & ID_AA64MMFR0_TGran16_MASK)
 817 #define  ID_AA64MMFR0_TGran16_NONE      (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT)
 818 #define  ID_AA64MMFR0_TGran16_IMPL      (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT)
 819 #define ID_AA64MMFR0_TGran64_SHIFT      24
 820 #define ID_AA64MMFR0_TGran64_MASK       (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
 821 #define ID_AA64MMFR0_TGran64_VAL(x)     ((x) & ID_AA64MMFR0_TGran64_MASK)
 822 #define  ID_AA64MMFR0_TGran64_IMPL      (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT)
 823 #define  ID_AA64MMFR0_TGran64_NONE      (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
 824 #define ID_AA64MMFR0_TGran4_SHIFT       28
 825 #define ID_AA64MMFR0_TGran4_MASK        (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
 826 #define ID_AA64MMFR0_TGran4_VAL(x)      ((x) & ID_AA64MMFR0_TGran4_MASK)
 827 #define  ID_AA64MMFR0_TGran4_IMPL       (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT)
 828 #define  ID_AA64MMFR0_TGran4_NONE       (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
 829 #define ID_AA64MMFR0_TGran16_2_SHIFT    32
 830 #define ID_AA64MMFR0_TGran16_2_MASK     (UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT)
 831 #define ID_AA64MMFR0_TGran16_2_VAL(x)   ((x) & ID_AA64MMFR0_TGran16_2_MASK)
 832 #define  ID_AA64MMFR0_TGran16_2_TGran16 (UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT)
 833 #define  ID_AA64MMFR0_TGran16_2_NONE    (UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT)
 834 #define  ID_AA64MMFR0_TGran16_2_IMPL    (UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT)
 835 #define ID_AA64MMFR0_TGran64_2_SHIFT    36
 836 #define ID_AA64MMFR0_TGran64_2_MASK     (UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT)
 837 #define ID_AA64MMFR0_TGran64_2_VAL(x)   ((x) & ID_AA64MMFR0_TGran64_2_MASK)
 838 #define  ID_AA64MMFR0_TGran64_2_TGran64 (UL(0x0) << ID_AA64MMFR0_TGran64_2_SHIFT)
 839 #define  ID_AA64MMFR0_TGran64_2_NONE    (UL(0x1) << ID_AA64MMFR0_TGran64_2_SHIFT)
 840 #define  ID_AA64MMFR0_TGran64_2_IMPL    (UL(0x2) << ID_AA64MMFR0_TGran64_2_SHIFT)
 841 #define ID_AA64MMFR0_TGran4_2_SHIFT     40
 842 #define ID_AA64MMFR0_TGran4_2_MASK      (UL(0xf) << ID_AA64MMFR0_TGran4_2_SHIFT)
 843 #define ID_AA64MMFR0_TGran4_2_VAL(x)    ((x) & ID_AA64MMFR0_TGran4_2_MASK)
 844 #define  ID_AA64MMFR0_TGran4_2_TGran4   (UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT)
 845 #define  ID_AA64MMFR0_TGran4_2_NONE     (UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT)
 846 #define  ID_AA64MMFR0_TGran4_2_IMPL     (UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT)
 847 #define ID_AA64MMFR0_ExS_SHIFT          44
 848 #define ID_AA64MMFR0_ExS_MASK           (UL(0xf) << ID_AA64MMFR0_ExS_SHIFT)
 849 #define ID_AA64MMFR0_ExS_VAL(x)         ((x) & ID_AA64MMFR0_ExS_MASK)
 850 #define  ID_AA64MMFR0_ExS_ALL           (UL(0x0) << ID_AA64MMFR0_ExS_SHIFT)
 851 #define  ID_AA64MMFR0_ExS_IMPL          (UL(0x1) << ID_AA64MMFR0_ExS_SHIFT)
 852
 853 /* ID_AA64MMFR1_EL1 */
 854 #define ID_AA64MMFR1_EL1                MRS_REG(ID_AA64MMFR1_EL1)
 855 #define ID_AA64MMFR1_EL1_op0            0x3
 856 #define ID_AA64MMFR1_EL1_op1            0x0
 857 #define ID_AA64MMFR1_EL1_CRn            0x0
 858 #define ID_AA64MMFR1_EL1_CRm            0x7
 859 #define ID_AA64MMFR1_EL1_op2            0x1
 860 #define ID_AA64MMFR1_HAFDBS_SHIFT       0
 861 #define ID_AA64MMFR1_HAFDBS_MASK        (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
 862 #define ID_AA64MMFR1_HAFDBS_VAL(x)      ((x) & ID_AA64MMFR1_HAFDBS_MASK)
 863 #define  ID_AA64MMFR1_HAFDBS_NONE       (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT)
 864 #define  ID_AA64MMFR1_HAFDBS_AF         (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT)
 865 #define  ID_AA64MMFR1_HAFDBS_AF_DBS     (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT)
 866 #define ID_AA64MMFR1_VMIDBits_SHIFT     4
 867 #define ID_AA64MMFR1_VMIDBits_MASK      (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT)
 868 #define ID_AA64MMFR1_VMIDBits_VAL(x)    ((x) & ID_AA64MMFR1_VMIDBits_MASK)
 869 #define  ID_AA64MMFR1_VMIDBits_8        (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT)
 870 #define  ID_AA64MMFR1_VMIDBits_16       (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT)
 871 #define ID_AA64MMFR1_VH_SHIFT           8
 872 #define ID_AA64MMFR1_VH_MASK            (UL(0xf) << ID_AA64MMFR1_VH_SHIFT)
 873 #define ID_AA64MMFR1_VH_VAL(x)          ((x) & ID_AA64MMFR1_VH_MASK)
 874 #define  ID_AA64MMFR1_VH_NONE           (UL(0x0) << ID_AA64MMFR1_VH_SHIFT)
 875 #define  ID_AA64MMFR1_VH_IMPL           (UL(0x1) << ID_AA64MMFR1_VH_SHIFT)
 876 #define ID_AA64MMFR1_HPDS_SHIFT         12
 877 #define ID_AA64MMFR1_HPDS_MASK          (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT)
 878 #define ID_AA64MMFR1_HPDS_VAL(x)        ((x) & ID_AA64MMFR1_HPDS_MASK)
 879 #define  ID_AA64MMFR1_HPDS_NONE         (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT)
 880 #define  ID_AA64MMFR1_HPDS_HPD          (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT)
 881 #define  ID_AA64MMFR1_HPDS_TTPBHA       (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT)
 882 #define ID_AA64MMFR1_LO_SHIFT           16
 883 #define ID_AA64MMFR1_LO_MASK            (UL(0xf) << ID_AA64MMFR1_LO_SHIFT)
 884 #define ID_AA64MMFR1_LO_VAL(x)          ((x) & ID_AA64MMFR1_LO_MASK)
 885 #define  ID_AA64MMFR1_LO_NONE           (UL(0x0) << ID_AA64MMFR1_LO_SHIFT)
 886 #define  ID_AA64MMFR1_LO_IMPL           (UL(0x1) << ID_AA64MMFR1_LO_SHIFT)
 887 #define ID_AA64MMFR1_PAN_SHIFT          20
 888 #define ID_AA64MMFR1_PAN_MASK           (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT)
 889 #define ID_AA64MMFR1_PAN_VAL(x)         ((x) & ID_AA64MMFR1_PAN_MASK)
 890 #define  ID_AA64MMFR1_PAN_NONE          (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT)
 891 #define  ID_AA64MMFR1_PAN_IMPL          (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT)
 892 #define  ID_AA64MMFR1_PAN_ATS1E1        (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT)
 893 #define ID_AA64MMFR1_SpecSEI_SHIFT      24
 894 #define ID_AA64MMFR1_SpecSEI_MASK       (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT)
 895 #define ID_AA64MMFR1_SpecSEI_VAL(x)     ((x) & ID_AA64MMFR1_SpecSEI_MASK)
 896 #define  ID_AA64MMFR1_SpecSEI_NONE      (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT)
 897 #define  ID_AA64MMFR1_SpecSEI_IMPL      (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT)
 898 #define ID_AA64MMFR1_XNX_SHIFT          28
 899 #define ID_AA64MMFR1_XNX_MASK           (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT)
 900 #define ID_AA64MMFR1_XNX_VAL(x)         ((x) & ID_AA64MMFR1_XNX_MASK)
 901 #define  ID_AA64MMFR1_XNX_NONE          (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT)
 902 #define  ID_AA64MMFR1_XNX_IMPL          (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT)
 903
 904 /* ID_AA64MMFR2_EL1 */
 905 #define ID_AA64MMFR2_EL1                MRS_REG(ID_AA64MMFR2_EL1)
 906 #define ID_AA64MMFR2_EL1_op0            0x3
 907 #define ID_AA64MMFR2_EL1_op1            0x0
 908 #define ID_AA64MMFR2_EL1_CRn            0x0
 909 #define ID_AA64MMFR2_EL1_CRm            0x7
 910 #define ID_AA64MMFR2_EL1_op2            0x2
 911 #define ID_AA64MMFR2_CnP_SHIFT          0
 912 #define ID_AA64MMFR2_CnP_MASK           (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT)
 913 #define ID_AA64MMFR2_CnP_VAL(x)         ((x) & ID_AA64MMFR2_CnP_MASK)
 914 #define  ID_AA64MMFR2_CnP_NONE          (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT)
 915 #define  ID_AA64MMFR2_CnP_IMPL          (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT)
 916 #define ID_AA64MMFR2_UAO_SHIFT          4
 917 #define ID_AA64MMFR2_UAO_MASK           (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT)
 918 #define ID_AA64MMFR2_UAO_VAL(x)         ((x) & ID_AA64MMFR2_UAO_MASK)
 919 #define  ID_AA64MMFR2_UAO_NONE          (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT)
 920 #define  ID_AA64MMFR2_UAO_IMPL          (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT)
 921 #define ID_AA64MMFR2_LSM_SHIFT          8
 922 #define ID_AA64MMFR2_LSM_MASK           (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT)
 923 #define ID_AA64MMFR2_LSM_VAL(x)         ((x) & ID_AA64MMFR2_LSM_MASK)
 924 #define  ID_AA64MMFR2_LSM_NONE          (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT)
 925 #define  ID_AA64MMFR2_LSM_IMPL          (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT)
 926 #define ID_AA64MMFR2_IESB_SHIFT         12
 927 #define ID_AA64MMFR2_IESB_MASK          (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT)
 928 #define ID_AA64MMFR2_IESB_VAL(x)        ((x) & ID_AA64MMFR2_IESB_MASK)
 929 #define  ID_AA64MMFR2_IESB_NONE         (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT)
 930 #define  ID_AA64MMFR2_IESB_IMPL         (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT)
 931 #define ID_AA64MMFR2_VARange_SHIFT      16
 932 #define ID_AA64MMFR2_VARange_MASK       (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT)
 933 #define ID_AA64MMFR2_VARange_VAL(x)     ((x) & ID_AA64MMFR2_VARange_MASK)
 934 #define  ID_AA64MMFR2_VARange_48        (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT)
 935 #define  ID_AA64MMFR2_VARange_52        (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT)
 936 #define ID_AA64MMFR2_CCIDX_SHIFT        20
 937 #define ID_AA64MMFR2_CCIDX_MASK         (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT)
 938 #define ID_AA64MMFR2_CCIDX_VAL(x)       ((x) & ID_AA64MMFR2_CCIDX_MASK)
 939 #define  ID_AA64MMFR2_CCIDX_32          (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT)
 940 #define  ID_AA64MMFR2_CCIDX_64          (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT)
 941 #define ID_AA64MMFR2_NV_SHIFT           24
 942 #define ID_AA64MMFR2_NV_MASK            (UL(0xf) << ID_AA64MMFR2_NV_SHIFT)
 943 #define ID_AA64MMFR2_NV_VAL(x)          ((x) & ID_AA64MMFR2_NV_MASK)
 944 #define  ID_AA64MMFR2_NV_NONE           (UL(0x0) << ID_AA64MMFR2_NV_SHIFT)
 945 #define  ID_AA64MMFR2_NV_8_3            (UL(0x1) << ID_AA64MMFR2_NV_SHIFT)
 946 #define  ID_AA64MMFR2_NV_8_4            (UL(0x2) << ID_AA64MMFR2_NV_SHIFT)
 947 #define ID_AA64MMFR2_ST_SHIFT           28
 948 #define ID_AA64MMFR2_ST_MASK            (UL(0xf) << ID_AA64MMFR2_ST_SHIFT)
 949 #define ID_AA64MMFR2_ST_VAL(x)          ((x) & ID_AA64MMFR2_ST_MASK)
 950 #define  ID_AA64MMFR2_ST_NONE           (UL(0x0) << ID_AA64MMFR2_ST_SHIFT)
 951 #define  ID_AA64MMFR2_ST_IMPL           (UL(0x1) << ID_AA64MMFR2_ST_SHIFT)
 952 #define ID_AA64MMFR2_AT_SHIFT           32
 953 #define ID_AA64MMFR2_AT_MASK            (UL(0xf) << ID_AA64MMFR2_AT_SHIFT)
 954 #define ID_AA64MMFR2_AT_VAL(x)          ((x) & ID_AA64MMFR2_AT_MASK)
 955 #define  ID_AA64MMFR2_AT_NONE           (UL(0x0) << ID_AA64MMFR2_AT_SHIFT)
 956 #define  ID_AA64MMFR2_AT_IMPL           (UL(0x1) << ID_AA64MMFR2_AT_SHIFT)
 957 #define ID_AA64MMFR2_IDS_SHIFT          36
 958 #define ID_AA64MMFR2_IDS_MASK           (UL(0xf) << ID_AA64MMFR2_IDS_SHIFT)
 959 #define ID_AA64MMFR2_IDS_VAL(x)         ((x) & ID_AA64MMFR2_IDS_MASK)
 960 #define  ID_AA64MMFR2_IDS_NONE          (UL(0x0) << ID_AA64MMFR2_IDS_SHIFT)
 961 #define  ID_AA64MMFR2_IDS_IMPL          (UL(0x1) << ID_AA64MMFR2_IDS_SHIFT)
 962 #define ID_AA64MMFR2_FWB_SHIFT          40
 963 #define ID_AA64MMFR2_FWB_MASK           (UL(0xf) << ID_AA64MMFR2_FWB_SHIFT)
 964 #define ID_AA64MMFR2_FWB_VAL(x)         ((x) & ID_AA64MMFR2_FWB_MASK)
 965 #define  ID_AA64MMFR2_FWB_NONE          (UL(0x0) << ID_AA64MMFR2_FWB_SHIFT)
 966 #define  ID_AA64MMFR2_FWB_IMPL          (UL(0x1) << ID_AA64MMFR2_FWB_SHIFT)
 967 #define ID_AA64MMFR2_TTL_SHIFT          48
 968 #define ID_AA64MMFR2_TTL_MASK           (UL(0xf) << ID_AA64MMFR2_TTL_SHIFT)
 969 #define ID_AA64MMFR2_TTL_VAL(x)         ((x) & ID_AA64MMFR2_TTL_MASK)
 970 #define  ID_AA64MMFR2_TTL_NONE          (UL(0x0) << ID_AA64MMFR2_TTL_SHIFT)
 971 #define  ID_AA64MMFR2_TTL_IMPL          (UL(0x1) << ID_AA64MMFR2_TTL_SHIFT)
 972 #define ID_AA64MMFR2_BBM_SHIFT          52
 973 #define ID_AA64MMFR2_BBM_MASK           (UL(0xf) << ID_AA64MMFR2_BBM_SHIFT)
 974 #define ID_AA64MMFR2_BBM_VAL(x)         ((x) & ID_AA64MMFR2_BBM_MASK)
 975 #define  ID_AA64MMFR2_BBM_LEVEL0        (UL(0x0) << ID_AA64MMFR2_BBM_SHIFT)
 976 #define  ID_AA64MMFR2_BBM_LEVEL1        (UL(0x1) << ID_AA64MMFR2_BBM_SHIFT)
 977 #define  ID_AA64MMFR2_BBM_LEVEL2        (UL(0x2) << ID_AA64MMFR2_BBM_SHIFT)
 978 #define ID_AA64MMFR2_EVT_SHIFT          56
 979 #define ID_AA64MMFR2_EVT_MASK           (UL(0xf) << ID_AA64MMFR2_EVT_SHIFT)
 980 #define ID_AA64MMFR2_EVT_VAL(x)         ((x) & ID_AA64MMFR2_EVT_MASK)
 981 #define  ID_AA64MMFR2_EVT_NONE          (UL(0x0) << ID_AA64MMFR2_EVT_SHIFT)
 982 #define  ID_AA64MMFR2_EVT_8_2           (UL(0x1) << ID_AA64MMFR2_EVT_SHIFT)
 983 #define  ID_AA64MMFR2_EVT_8_5           (UL(0x2) << ID_AA64MMFR2_EVT_SHIFT)
 984 #define ID_AA64MMFR2_E0PD_SHIFT         60
 985 #define ID_AA64MMFR2_E0PD_MASK          (UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT)
 986 #define ID_AA64MMFR2_E0PD_VAL(x)        ((x) & ID_AA64MMFR2_E0PD_MASK)
 987 #define  ID_AA64MMFR2_E0PD_NONE         (UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT)
 988 #define  ID_AA64MMFR2_E0PD_IMPL         (UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT)
 989
 990 /* ID_AA64PFR0_EL1 */
 991 #define ID_AA64PFR0_EL1                 MRS_REG(ID_AA64PFR0_EL1)
 992 #define ID_AA64PFR0_EL1_op0             0x3
 993 #define ID_AA64PFR0_EL1_op1             0x0
 994 #define ID_AA64PFR0_EL1_CRn             0x0
 995 #define ID_AA64PFR0_EL1_CRm             0x4
 996 #define ID_AA64PFR0_EL1_op2             0x0
 997 #define ID_AA64PFR0_EL0_SHIFT           0
 998 #define ID_AA64PFR0_EL0_MASK            (UL(0xf) << ID_AA64PFR0_EL0_SHIFT)
 999 #define ID_AA64PFR0_EL0_VAL(x)          ((x) & ID_AA64PFR0_EL0_MASK)
1000 #define  ID_AA64PFR0_EL0_64             (UL(0x1) << ID_AA64PFR0_EL0_SHIFT)
1001 #define  ID_AA64PFR0_EL0_64_32          (UL(0x2) << ID_AA64PFR0_EL0_SHIFT)
1002 #define ID_AA64PFR0_EL1_SHIFT           4
1003 #define ID_AA64PFR0_EL1_MASK            (UL(0xf) << ID_AA64PFR0_EL1_SHIFT)
1004 #define ID_AA64PFR0_EL1_VAL(x)          ((x) & ID_AA64PFR0_EL1_MASK)
1005 #define  ID_AA64PFR0_EL1_64             (UL(0x1) << ID_AA64PFR0_EL1_SHIFT)
1006 #define  ID_AA64PFR0_EL1_64_32          (UL(0x2) << ID_AA64PFR0_EL1_SHIFT)
1007 #define ID_AA64PFR0_EL2_SHIFT           8
1008 #define ID_AA64PFR0_EL2_MASK            (UL(0xf) << ID_AA64PFR0_EL2_SHIFT)
1009 #define ID_AA64PFR0_EL2_VAL(x)          ((x) & ID_AA64PFR0_EL2_MASK)
1010 #define  ID_AA64PFR0_EL2_NONE           (UL(0x0) << ID_AA64PFR0_EL2_SHIFT)
1011 #define  ID_AA64PFR0_EL2_64             (UL(0x1) << ID_AA64PFR0_EL2_SHIFT)
1012 #define  ID_AA64PFR0_EL2_64_32          (UL(0x2) << ID_AA64PFR0_EL2_SHIFT)
1013 #define ID_AA64PFR0_EL3_SHIFT           12
1014 #define ID_AA64PFR0_EL3_MASK            (UL(0xf) << ID_AA64PFR0_EL3_SHIFT)
1015 #define ID_AA64PFR0_EL3_VAL(x)          ((x) & ID_AA64PFR0_EL3_MASK)
1016 #define  ID_AA64PFR0_EL3_NONE           (UL(0x0) << ID_AA64PFR0_EL3_SHIFT)
1017 #define  ID_AA64PFR0_EL3_64             (UL(0x1) << ID_AA64PFR0_EL3_SHIFT)
1018 #define  ID_AA64PFR0_EL3_64_32          (UL(0x2) << ID_AA64PFR0_EL3_SHIFT)
1019 #define ID_AA64PFR0_FP_SHIFT            16
1020 #define ID_AA64PFR0_FP_MASK             (UL(0xf) << ID_AA64PFR0_FP_SHIFT)
1021 #define ID_AA64PFR0_FP_VAL(x)           ((x) & ID_AA64PFR0_FP_MASK)
1022 #define  ID_AA64PFR0_FP_IMPL            (UL(0x0) << ID_AA64PFR0_FP_SHIFT)
1023 #define  ID_AA64PFR0_FP_HP              (UL(0x1) << ID_AA64PFR0_FP_SHIFT)
1024 #define  ID_AA64PFR0_FP_NONE            (UL(0xf) << ID_AA64PFR0_FP_SHIFT)
1025 #define ID_AA64PFR0_AdvSIMD_SHIFT       20
1026 #define ID_AA64PFR0_AdvSIMD_MASK        (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
1027 #define ID_AA64PFR0_AdvSIMD_VAL(x)      ((x) & ID_AA64PFR0_AdvSIMD_MASK)
1028 #define  ID_AA64PFR0_AdvSIMD_IMPL       (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT)
1029 #define  ID_AA64PFR0_AdvSIMD_HP         (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT)
1030 #define  ID_AA64PFR0_AdvSIMD_NONE       (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
1031 #define ID_AA64PFR0_GIC_BITS            0x4 /* Number of bits in GIC field */
1032 #define ID_AA64PFR0_GIC_SHIFT           24
1033 #define ID_AA64PFR0_GIC_MASK            (UL(0xf) << ID_AA64PFR0_GIC_SHIFT)
1034 #define ID_AA64PFR0_GIC_VAL(x)          ((x) & ID_AA64PFR0_GIC_MASK)
1035 #define  ID_AA64PFR0_GIC_CPUIF_NONE     (UL(0x0) << ID_AA64PFR0_GIC_SHIFT)
1036 #define  ID_AA64PFR0_GIC_CPUIF_EN       (UL(0x1) << ID_AA64PFR0_GIC_SHIFT)
1037 #define  ID_AA64PFR0_GIC_CPUIF_4_1      (UL(0x3) << ID_AA64PFR0_GIC_SHIFT)
1038 #define ID_AA64PFR0_RAS_SHIFT           28
1039 #define ID_AA64PFR0_RAS_MASK            (UL(0xf) << ID_AA64PFR0_RAS_SHIFT)
1040 #define ID_AA64PFR0_RAS_VAL(x)          ((x) & ID_AA64PFR0_RAS_MASK)
1041 #define  ID_AA64PFR0_RAS_NONE           (UL(0x0) << ID_AA64PFR0_RAS_SHIFT)
1042 #define  ID_AA64PFR0_RAS_IMPL           (UL(0x1) << ID_AA64PFR0_RAS_SHIFT)
1043 #define  ID_AA64PFR0_RAS_8_4            (UL(0x2) << ID_AA64PFR0_RAS_SHIFT)
1044 #define ID_AA64PFR0_SVE_SHIFT           32
1045 #define ID_AA64PFR0_SVE_MASK            (UL(0xf) << ID_AA64PFR0_SVE_SHIFT)
1046 #define ID_AA64PFR0_SVE_VAL(x)          ((x) & ID_AA64PFR0_SVE_MASK)
1047 #define  ID_AA64PFR0_SVE_NONE           (UL(0x0) << ID_AA64PFR0_SVE_SHIFT)
1048 #define  ID_AA64PFR0_SVE_IMPL           (UL(0x1) << ID_AA64PFR0_SVE_SHIFT)
1049 #define ID_AA64PFR0_SEL2_SHIFT          36
1050 #define ID_AA64PFR0_SEL2_MASK           (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT)
1051 #define ID_AA64PFR0_SEL2_VAL(x)         ((x) & ID_AA64PFR0_SEL2_MASK)
1052 #define  ID_AA64PFR0_SEL2_NONE          (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT)
1053 #define  ID_AA64PFR0_SEL2_IMPL          (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT)
1054 #define ID_AA64PFR0_MPAM_SHIFT          40
1055 #define ID_AA64PFR0_MPAM_MASK           (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT)
1056 #define ID_AA64PFR0_MPAM_VAL(x)         ((x) & ID_AA64PFR0_MPAM_MASK)
1057 #define  ID_AA64PFR0_MPAM_NONE          (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT)
1058 #define  ID_AA64PFR0_MPAM_IMPL          (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT)
1059 #define ID_AA64PFR0_AMU_SHIFT           44
1060 #define ID_AA64PFR0_AMU_MASK            (UL(0xf) << ID_AA64PFR0_AMU_SHIFT)
1061 #define ID_AA64PFR0_AMU_VAL(x)          ((x) & ID_AA64PFR0_AMU_MASK)
1062 #define  ID_AA64PFR0_AMU_NONE           (UL(0x0) << ID_AA64PFR0_AMU_SHIFT)
1063 #define  ID_AA64PFR0_AMU_V1             (UL(0x1) << ID_AA64PFR0_AMU_SHIFT)
1064 #define ID_AA64PFR0_DIT_SHIFT           48
1065 #define ID_AA64PFR0_DIT_MASK            (UL(0xf) << ID_AA64PFR0_DIT_SHIFT)
1066 #define ID_AA64PFR0_DIT_VAL(x)          ((x) & ID_AA64PFR0_DIT_MASK)
1067 #define  ID_AA64PFR0_DIT_NONE           (UL(0x0) << ID_AA64PFR0_DIT_SHIFT)
1068 #define  ID_AA64PFR0_DIT_PSTATE         (UL(0x1) << ID_AA64PFR0_DIT_SHIFT)
1069 #define ID_AA64PFR0_CSV2_SHIFT          56
1070 #define ID_AA64PFR0_CSV2_MASK           (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT)
1071 #define ID_AA64PFR0_CSV2_VAL(x)         ((x) & ID_AA64PFR0_CSV2_MASK)
1072 #define  ID_AA64PFR0_CSV2_NONE          (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT)
1073 #define  ID_AA64PFR0_CSV2_ISOLATED      (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT)
1074 #define  ID_AA64PFR0_CSV2_SCXTNUM       (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT)
1075 #define ID_AA64PFR0_CSV3_SHIFT          60
1076 #define ID_AA64PFR0_CSV3_MASK           (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT)
1077 #define ID_AA64PFR0_CSV3_VAL(x)         ((x) & ID_AA64PFR0_CSV3_MASK)
1078 #define  ID_AA64PFR0_CSV3_NONE          (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT)
1079 #define  ID_AA64PFR0_CSV3_ISOLATED      (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT)
1080
1081 /* ID_AA64PFR1_EL1 */
1082 #define ID_AA64PFR1_EL1                 MRS_REG(ID_AA64PFR1_EL1)
1083 #define ID_AA64PFR1_EL1_op0             0x3
1084 #define ID_AA64PFR1_EL1_op1             0x0
1085 #define ID_AA64PFR1_EL1_CRn             0x0
1086 #define ID_AA64PFR1_EL1_CRm             0x4
1087 #define ID_AA64PFR1_EL1_op2             0x1
1088 #define ID_AA64PFR1_BT_SHIFT            0
1089 #define ID_AA64PFR1_BT_MASK             (UL(0xf) << ID_AA64PFR1_BT_SHIFT)
1090 #define ID_AA64PFR1_BT_VAL(x)           ((x) & ID_AA64PFR1_BT_MASK)
1091 #define  ID_AA64PFR1_BT_NONE            (UL(0x0) << ID_AA64PFR1_BT_SHIFT)
1092 #define  ID_AA64PFR1_BT_IMPL            (UL(0x1) << ID_AA64PFR1_BT_SHIFT)
1093 #define ID_AA64PFR1_SSBS_SHIFT          4
1094 #define ID_AA64PFR1_SSBS_MASK           (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT)
1095 #define ID_AA64PFR1_SSBS_VAL(x)         ((x) & ID_AA64PFR1_SSBS_MASK)
1096 #define  ID_AA64PFR1_SSBS_NONE          (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT)
1097 #define  ID_AA64PFR1_SSBS_PSTATE        (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT)
1098 #define  ID_AA64PFR1_SSBS_PSTATE_MSR    (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT)
1099 #define ID_AA64PFR1_MTE_SHIFT           8
1100 #define ID_AA64PFR1_MTE_MASK            (UL(0xf) << ID_AA64PFR1_MTE_SHIFT)
1101 #define ID_AA64PFR1_MTE_VAL(x)          ((x) & ID_AA64PFR1_MTE_MASK)
1102 #define  ID_AA64PFR1_MTE_NONE           (UL(0x0) << ID_AA64PFR1_MTE_SHIFT)
1103 #define  ID_AA64PFR1_MTE_IMPL_EL0       (UL(0x1) << ID_AA64PFR1_MTE_SHIFT)
1104 #define  ID_AA64PFR1_MTE_IMPL           (UL(0x2) << ID_AA64PFR1_MTE_SHIFT)
1105 #define ID_AA64PFR1_RAS_frac_SHIFT      12
1106 #define ID_AA64PFR1_RAS_frac_MASK       (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT)
1107 #define ID_AA64PFR1_RAS_frac_VAL(x)     ((x) & ID_AA64PFR1_RAS_frac_MASK)
1108 #define  ID_AA64PFR1_RAS_frac_V1        (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT)
1109 #define  ID_AA64PFR1_RAS_frac_V2        (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT)
1110
1111 /* ID_AA64ZFR0_EL1 */
1112 #define ID_AA64ZFR0_EL1                 MRS_REG(ID_AA64ZFR0_EL1)
1113 #define ID_AA64ZFR0_EL1_REG             MRS_REG_ALT_NAME(ID_AA64ZFR0_EL1)
1114 #define ID_AA64ZFR0_EL1_op0             3
1115 #define ID_AA64ZFR0_EL1_op1             0
1116 #define ID_AA64ZFR0_EL1_CRn             0
1117 #define ID_AA64ZFR0_EL1_CRm             4
1118 #define ID_AA64ZFR0_EL1_op2             4
1119 #define ID_AA64ZFR0_SVEver_SHIFT        0
1120 #define ID_AA64ZFR0_SVEver_MASK         (UL(0xf) << ID_AA64ZFR0_SVEver_SHIFT)
1121 #define ID_AA64ZFR0_SVEver_VAL(x)       ((x) & ID_AA64ZFR0_SVEver_MASK
1122 #define ID_AA64ZFR0_SVEver_SVE1         (UL(0x0) << ID_AA64ZFR0_SVEver_SHIFT)
1123 #define ID_AA64ZFR0_SVEver_SVE2         (UL(0x1) << ID_AA64ZFR0_SVEver_SHIFT)
1124 #define ID_AA64ZFR0_AES_SHIFT           4
1125 #define ID_AA64ZFR0_AES_MASK            (UL(0xf) << ID_AA64ZFR0_AES_SHIFT)
1126 #define ID_AA64ZFR0_AES_VAL(x)          ((x) & ID_AA64ZFR0_AES_MASK
1127 #define ID_AA64ZFR0_AES_NONE            (UL(0x0) << ID_AA64ZFR0_AES_SHIFT)
1128 #define ID_AA64ZFR0_AES_BASE            (UL(0x1) << ID_AA64ZFR0_AES_SHIFT)
1129 #define ID_AA64ZFR0_AES_PMULL           (UL(0x2) << ID_AA64ZFR0_AES_SHIFT)
1130 #define ID_AA64ZFR0_BitPerm_SHIFT       16
1131 #define ID_AA64ZFR0_BitPerm_MASK        (UL(0xf) << ID_AA64ZFR0_BitPerm_SHIFT)
1132 #define ID_AA64ZFR0_BitPerm_VAL(x)      ((x) & ID_AA64ZFR0_BitPerm_MASK
1133 #define ID_AA64ZFR0_BitPerm_NONE        (UL(0x0) << ID_AA64ZFR0_BitPerm_SHIFT)
1134 #define ID_AA64ZFR0_BitPerm_IMPL        (UL(0x1) << ID_AA64ZFR0_BitPerm_SHIFT)
1135 #define ID_AA64ZFR0_BF16_SHIFT          20
1136 #define ID_AA64ZFR0_BF16_MASK           (UL(0xf) << ID_AA64ZFR0_BF16_SHIFT)
1137 #define ID_AA64ZFR0_BF16_VAL(x)         ((x) & ID_AA64ZFR0_BF16_MASK
1138 #define ID_AA64ZFR0_BF16_NONE           (UL(0x0) << ID_AA64ZFR0_BF16_SHIFT)
1139 #define ID_AA64ZFR0_BF16_BASE           (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT)
1140 #define ID_AA64ZFR0_BF16_EBF            (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT)
1141 #define ID_AA64ZFR0_SHA3_SHIFT          32
1142 #define ID_AA64ZFR0_SHA3_MASK           (UL(0xf) << ID_AA64ZFR0_SHA3_SHIFT)
1143 #define ID_AA64ZFR0_SHA3_VAL(x)         ((x) & ID_AA64ZFR0_SHA3_MASK
1144 #define ID_AA64ZFR0_SHA3_NONE           (UL(0x0) << ID_AA64ZFR0_SHA3_SHIFT)
1145 #define ID_AA64ZFR0_SHA3_IMPL           (UL(0x1) << ID_AA64ZFR0_SHA3_SHIFT)
1146 #define ID_AA64ZFR0_SM4_SHIFT           40
1147 #define ID_AA64ZFR0_SM4_MASK            (UL(0xf) << ID_AA64ZFR0_SM4_SHIFT)
1148 #define ID_AA64ZFR0_SM4_VAL(x)          ((x) & ID_AA64ZFR0_SM4_MASK
1149 #define ID_AA64ZFR0_SM4_NONE            (UL(0x0) << ID_AA64ZFR0_SM4_SHIFT)
1150 #define ID_AA64ZFR0_SM4_IMPL            (UL(0x1) << ID_AA64ZFR0_SM4_SHIFT)
1151 #define ID_AA64ZFR0_I8MM_SHIFT          44
1152 #define ID_AA64ZFR0_I8MM_MASK           (UL(0xf) << ID_AA64ZFR0_I8MM_SHIFT)
1153 #define ID_AA64ZFR0_I8MM_VAL(x)         ((x) & ID_AA64ZFR0_I8MM_MASK
1154 #define ID_AA64ZFR0_I8MM_NONE           (UL(0x0) << ID_AA64ZFR0_I8MM_SHIFT)
1155 #define ID_AA64ZFR0_I8MM_IMPL           (UL(0x1) << ID_AA64ZFR0_I8MM_SHIFT)
1156 #define ID_AA64ZFR0_F32MM_SHIFT         52
1157 #define ID_AA64ZFR0_F32MM_MASK          (UL(0xf) << ID_AA64ZFR0_F32MM_SHIFT)
1158 #define ID_AA64ZFR0_F32MM_VAL(x)        ((x) & ID_AA64ZFR0_F32MM_MASK
1159 #define ID_AA64ZFR0_F32MM_NONE          (UL(0x0) << ID_AA64ZFR0_F32MM_SHIFT)
1160 #define ID_AA64ZFR0_F32MM_IMPL          (UL(0x1) << ID_AA64ZFR0_F32MM_SHIFT)
1161 #define ID_AA64ZFR0_F64MM_SHIFT         56
1162 #define ID_AA64ZFR0_F64MM_MASK          (UL(0xf) << ID_AA64ZFR0_F64MM_SHIFT)
1163 #define ID_AA64ZFR0_F64MM_VAL(x)        ((x) & ID_AA64ZFR0_F64MM_MASK
1164 #define ID_AA64ZFR0_F64MM_NONE          (UL(0x0) << ID_AA64ZFR0_F64MM_SHIFT)
1165 #define ID_AA64ZFR0_F64MM_IMPL          (UL(0x1) << ID_AA64ZFR0_F64MM_SHIFT)
1166
1167 /* ID_ISAR5_EL1 */
1168 #define ID_ISAR5_EL1                    MRS_REG(ID_ISAR5_EL1)
1169 #define ID_ISAR5_EL1_op0                0x3
1170 #define ID_ISAR5_EL1_op1                0x0
1171 #define ID_ISAR5_EL1_CRn                0x0
1172 #define ID_ISAR5_EL1_CRm                0x2
1173 #define ID_ISAR5_EL1_op2                0x5
1174 #define ID_ISAR5_SEVL_SHIFT             0
1175 #define ID_ISAR5_SEVL_MASK              (UL(0xf) << ID_ISAR5_SEVL_SHIFT)
1176 #define ID_ISAR5_SEVL_VAL(x)            ((x) & ID_ISAR5_SEVL_MASK)
1177 #define  ID_ISAR5_SEVL_NOP              (UL(0x0) << ID_ISAR5_SEVL_SHIFT)
1178 #define  ID_ISAR5_SEVL_IMPL             (UL(0x1) << ID_ISAR5_SEVL_SHIFT)
1179 #define ID_ISAR5_AES_SHIFT              4
1180 #define ID_ISAR5_AES_MASK               (UL(0xf) << ID_ISAR5_AES_SHIFT)
1181 #define ID_ISAR5_AES_VAL(x)             ((x) & ID_ISAR5_AES_MASK)
1182 #define  ID_ISAR5_AES_NONE              (UL(0x0) << ID_ISAR5_AES_SHIFT)
1183 #define  ID_ISAR5_AES_BASE              (UL(0x1) << ID_ISAR5_AES_SHIFT)
1184 #define  ID_ISAR5_AES_VMULL             (UL(0x2) << ID_ISAR5_AES_SHIFT)
1185 #define ID_ISAR5_SHA1_SHIFT             8
1186 #define ID_ISAR5_SHA1_MASK              (UL(0xf) << ID_ISAR5_SHA1_SHIFT)
1187 #define ID_ISAR5_SHA1_VAL(x)            ((x) & ID_ISAR5_SHA1_MASK)
1188 #define  ID_ISAR5_SHA1_NONE             (UL(0x0) << ID_ISAR5_SHA1_SHIFT)
1189 #define  ID_ISAR5_SHA1_IMPL             (UL(0x1) << ID_ISAR5_SHA1_SHIFT)
1190 #define ID_ISAR5_SHA2_SHIFT             12
1191 #define ID_ISAR5_SHA2_MASK              (UL(0xf) << ID_ISAR5_SHA2_SHIFT)
1192 #define ID_ISAR5_SHA2_VAL(x)            ((x) & ID_ISAR5_SHA2_MASK)
1193 #define  ID_ISAR5_SHA2_NONE             (UL(0x0) << ID_ISAR5_SHA2_SHIFT)
1194 #define  ID_ISAR5_SHA2_IMPL             (UL(0x1) << ID_ISAR5_SHA2_SHIFT)
1195 #define ID_ISAR5_CRC32_SHIFT            16
1196 #define ID_ISAR5_CRC32_MASK             (UL(0xf) << ID_ISAR5_CRC32_SHIFT)
1197 #define ID_ISAR5_CRC32_VAL(x)           ((x) & ID_ISAR5_CRC32_MASK)
1198 #define  ID_ISAR5_CRC32_NONE            (UL(0x0) << ID_ISAR5_CRC32_SHIFT)
1199 #define  ID_ISAR5_CRC32_IMPL            (UL(0x1) << ID_ISAR5_CRC32_SHIFT)
1200 #define ID_ISAR5_RDM_SHIFT              24
1201 #define ID_ISAR5_RDM_MASK               (UL(0xf) << ID_ISAR5_RDM_SHIFT)
1202 #define ID_ISAR5_RDM_VAL(x)             ((x) & ID_ISAR5_RDM_MASK)
1203 #define  ID_ISAR5_RDM_NONE              (UL(0x0) << ID_ISAR5_RDM_SHIFT)
1204 #define  ID_ISAR5_RDM_IMPL              (UL(0x1) << ID_ISAR5_RDM_SHIFT)
1205 #define ID_ISAR5_VCMA_SHIFT             28
1206 #define ID_ISAR5_VCMA_MASK              (UL(0xf) << ID_ISAR5_VCMA_SHIFT)
1207 #define ID_ISAR5_VCMA_VAL(x)            ((x) & ID_ISAR5_VCMA_MASK)
1208 #define  ID_ISAR5_VCMA_NONE             (UL(0x0) << ID_ISAR5_VCMA_SHIFT)
1209 #define  ID_ISAR5_VCMA_IMPL             (UL(0x1) << ID_ISAR5_VCMA_SHIFT)
1210
1211 /* MAIR_EL1 - Memory Attribute Indirection Register */
1212 #define MAIR_ATTR_MASK(idx)     (UL(0xff) << ((n)* 8))
1213 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
1214 #define  MAIR_DEVICE_nGnRnE     UL(0x00)
1215 #define  MAIR_DEVICE_nGnRE      UL(0x04)
1216 #define  MAIR_NORMAL_NC         UL(0x44)
1217 #define  MAIR_NORMAL_WT         UL(0xbb)
1218 #define  MAIR_NORMAL_WB         UL(0xff)
1219
1220 /* MDCCINT_EL1 */
1221 #define MDCCINT_EL1                     MRS_REG(MDCCINT_EL1)
1222 #define MDCCINT_EL1_op0                 2
1223 #define MDCCINT_EL1_op1                 0
1224 #define MDCCINT_EL1_CRn                 0
1225 #define MDCCINT_EL1_CRm                 2
1226 #define MDCCINT_EL1_op2                 0
1227
1228 /* MDCCSR_EL0 */
1229 #define MDCCSR_EL0                      MRS_REG(MDCCSR_EL0)
1230 #define MDCCSR_EL0_op0                  2
1231 #define MDCCSR_EL0_op1                  3
1232 #define MDCCSR_EL0_CRn                  0
1233 #define MDCCSR_EL0_CRm                  1
1234 #define MDCCSR_EL0_op2                  0
1235
1236 /* MDSCR_EL1 - Monitor Debug System Control Register */
1237 #define MDSCR_EL1                       MRS_REG(MDSCR_EL1)
1238 #define MDSCR_EL1_op0                   2
1239 #define MDSCR_EL1_op1                   0
1240 #define MDSCR_EL1_CRn                   0
1241 #define MDSCR_EL1_CRm                   2
1242 #define MDSCR_EL1_op2                   2
1243 #define MDSCR_SS_SHIFT                  0
1244 #define MDSCR_SS                        (UL(0x1) << MDSCR_SS_SHIFT)
1245 #define MDSCR_KDE_SHIFT                 13
1246 #define MDSCR_KDE                       (UL(0x1) << MDSCR_KDE_SHIFT)
1247 #define MDSCR_MDE_SHIFT                 15
1248 #define MDSCR_MDE                       (UL(0x1) << MDSCR_MDE_SHIFT)
1249
1250 /* MIDR_EL1 - Main ID Register */
1251 #define MIDR_EL1                        MRS_REG(MIDR_EL1)
1252 #define MIDR_EL1_op0                    3
1253 #define MIDR_EL1_op1                    0
1254 #define MIDR_EL1_CRn                    0
1255 #define MIDR_EL1_CRm                    0
1256 #define MIDR_EL1_op2                    0
1257
1258 /* MPIDR_EL1 - Multiprocessor Affinity Register */
1259 #define MPIDR_EL1                       MRS_REG(MPIDR_EL1)
1260 #define MPIDR_EL1_op0                   3
1261 #define MPIDR_EL1_op1                   0
1262 #define MPIDR_EL1_CRn                   0
1263 #define MPIDR_EL1_CRm                   0
1264 #define MPIDR_EL1_op2                   5
1265 #define MPIDR_AFF0_SHIFT                0
1266 #define MPIDR_AFF0_MASK                 (UL(0xff) << MPIDR_AFF0_SHIFT)
1267 #define MPIDR_AFF0_VAL(x)               ((x) & MPIDR_AFF0_MASK)
1268 #define MPIDR_AFF1_SHIFT                8
1269 #define MPIDR_AFF1_MASK                 (UL(0xff) << MPIDR_AFF1_SHIFT)
1270 #define MPIDR_AFF1_VAL(x)               ((x) & MPIDR_AFF1_MASK)
1271 #define MPIDR_AFF2_SHIFT                16
1272 #define MPIDR_AFF2_MASK                 (UL(0xff) << MPIDR_AFF2_SHIFT)
1273 #define MPIDR_AFF2_VAL(x)               ((x) & MPIDR_AFF2_MASK)
1274 #define MPIDR_MT_SHIFT                  24
1275 #define MPIDR_MT_MASK                   (UL(0x1) << MPIDR_MT_SHIFT)
1276 #define MPIDR_U_SHIFT                   30
1277 #define MPIDR_U_MASK                    (UL(0x1) << MPIDR_U_SHIFT)
1278 #define MPIDR_AFF3_SHIFT                32
1279 #define MPIDR_AFF3_MASK                 (UL(0xff) << MPIDR_AFF3_SHIFT)
1280 #define MPIDR_AFF3_VAL(x)               ((x) & MPIDR_AFF3_MASK)
1281
1282 /* MVFR0_EL1 */
1283 #define MVFR0_EL1                       MRS_REG(MVFR0_EL1)
1284 #define MVFR0_EL1_op0                   0x3
1285 #define MVFR0_EL1_op1                   0x0
1286 #define MVFR0_EL1_CRn                   0x0
1287 #define MVFR0_EL1_CRm                   0x3
1288 #define MVFR0_EL1_op2                   0x0
1289 #define MVFR0_SIMDReg_SHIFT             0
1290 #define MVFR0_SIMDReg_MASK              (UL(0xf) << MVFR0_SIMDReg_SHIFT)
1291 #define MVFR0_SIMDReg_VAL(x)            ((x) & MVFR0_SIMDReg_MASK)
1292 #define  MVFR0_SIMDReg_NONE             (UL(0x0) << MVFR0_SIMDReg_SHIFT)
1293 #define  MVFR0_SIMDReg_FP               (UL(0x1) << MVFR0_SIMDReg_SHIFT)
1294 #define  MVFR0_SIMDReg_AdvSIMD          (UL(0x2) << MVFR0_SIMDReg_SHIFT)
1295 #define MVFR0_FPSP_SHIFT                4
1296 #define MVFR0_FPSP_MASK                 (UL(0xf) << MVFR0_FPSP_SHIFT)
1297 #define MVFR0_FPSP_VAL(x)               ((x) & MVFR0_FPSP_MASK)
1298 #define  MVFR0_FPSP_NONE                (UL(0x0) << MVFR0_FPSP_SHIFT)
1299 #define  MVFR0_FPSP_VFP_v2              (UL(0x1) << MVFR0_FPSP_SHIFT)
1300 #define  MVFR0_FPSP_VFP_v3_v4           (UL(0x2) << MVFR0_FPSP_SHIFT)
1301 #define MVFR0_FPDP_SHIFT                8
1302 #define MVFR0_FPDP_MASK                 (UL(0xf) << MVFR0_FPDP_SHIFT)
1303 #define MVFR0_FPDP_VAL(x)               ((x) & MVFR0_FPDP_MASK)
1304 #define  MVFR0_FPDP_NONE                (UL(0x0) << MVFR0_FPDP_SHIFT)
1305 #define  MVFR0_FPDP_VFP_v2              (UL(0x1) << MVFR0_FPDP_SHIFT)
1306 #define  MVFR0_FPDP_VFP_v3_v4           (UL(0x2) << MVFR0_FPDP_SHIFT)
1307 #define MVFR0_FPTrap_SHIFT              12
1308 #define MVFR0_FPTrap_MASK               (UL(0xf) << MVFR0_FPTrap_SHIFT)
1309 #define MVFR0_FPTrap_VAL(x)             ((x) & MVFR0_FPTrap_MASK)
1310 #define  MVFR0_FPTrap_NONE              (UL(0x0) << MVFR0_FPTrap_SHIFT)
1311 #define  MVFR0_FPTrap_IMPL              (UL(0x1) << MVFR0_FPTrap_SHIFT)
1312 #define MVFR0_FPDivide_SHIFT            16
1313 #define MVFR0_FPDivide_MASK             (UL(0xf) << MVFR0_FPDivide_SHIFT)
1314 #define MVFR0_FPDivide_VAL(x)           ((x) & MVFR0_FPDivide_MASK)
1315 #define  MVFR0_FPDivide_NONE            (UL(0x0) << MVFR0_FPDivide_SHIFT)
1316 #define  MVFR0_FPDivide_IMPL            (UL(0x1) << MVFR0_FPDivide_SHIFT)
1317 #define MVFR0_FPSqrt_SHIFT              20
1318 #define MVFR0_FPSqrt_MASK               (UL(0xf) << MVFR0_FPSqrt_SHIFT)
1319 #define MVFR0_FPSqrt_VAL(x)             ((x) & MVFR0_FPSqrt_MASK)
1320 #define  MVFR0_FPSqrt_NONE              (UL(0x0) << MVFR0_FPSqrt_SHIFT)
1321 #define  MVFR0_FPSqrt_IMPL              (UL(0x1) << MVFR0_FPSqrt_SHIFT)
1322 #define MVFR0_FPShVec_SHIFT             24
1323 #define MVFR0_FPShVec_MASK              (UL(0xf) << MVFR0_FPShVec_SHIFT)
1324 #define MVFR0_FPShVec_VAL(x)            ((x) & MVFR0_FPShVec_MASK)
1325 #define  MVFR0_FPShVec_NONE             (UL(0x0) << MVFR0_FPShVec_SHIFT)
1326 #define  MVFR0_FPShVec_IMPL             (UL(0x1) << MVFR0_FPShVec_SHIFT)
1327 #define MVFR0_FPRound_SHIFT             28
1328 #define MVFR0_FPRound_MASK              (UL(0xf) << MVFR0_FPRound_SHIFT)
1329 #define MVFR0_FPRound_VAL(x)            ((x) & MVFR0_FPRound_MASK)
1330 #define  MVFR0_FPRound_NONE             (UL(0x0) << MVFR0_FPRound_SHIFT)
1331 #define  MVFR0_FPRound_IMPL             (UL(0x1) << MVFR0_FPRound_SHIFT)
1332
1333 /* MVFR1_EL1 */
1334 #define MVFR1_EL1                       MRS_REG(MVFR1_EL1)
1335 #define MVFR1_EL1_op0                   0x3
1336 #define MVFR1_EL1_op1                   0x0
1337 #define MVFR1_EL1_CRn                   0x0
1338 #define MVFR1_EL1_CRm                   0x3
1339 #define MVFR1_EL1_op2                   0x1
1340 #define MVFR1_FPFtZ_SHIFT               0
1341 #define MVFR1_FPFtZ_MASK                (UL(0xf) << MVFR1_FPFtZ_SHIFT)
1342 #define MVFR1_FPFtZ_VAL(x)              ((x) & MVFR1_FPFtZ_MASK)
1343 #define  MVFR1_FPFtZ_NONE               (UL(0x0) << MVFR1_FPFtZ_SHIFT)
1344 #define  MVFR1_FPFtZ_IMPL               (UL(0x1) << MVFR1_FPFtZ_SHIFT)
1345 #define MVFR1_FPDNaN_SHIFT              4
1346 #define MVFR1_FPDNaN_MASK               (UL(0xf) << MVFR1_FPDNaN_SHIFT)
1347 #define MVFR1_FPDNaN_VAL(x)             ((x) & MVFR1_FPDNaN_MASK)
1348 #define  MVFR1_FPDNaN_NONE              (UL(0x0) << MVFR1_FPDNaN_SHIFT)
1349 #define  MVFR1_FPDNaN_IMPL              (UL(0x1) << MVFR1_FPDNaN_SHIFT)
1350 #define MVFR1_SIMDLS_SHIFT              8
1351 #define MVFR1_SIMDLS_MASK               (UL(0xf) << MVFR1_SIMDLS_SHIFT)
1352 #define MVFR1_SIMDLS_VAL(x)             ((x) & MVFR1_SIMDLS_MASK)
1353 #define  MVFR1_SIMDLS_NONE              (UL(0x0) << MVFR1_SIMDLS_SHIFT)
1354 #define  MVFR1_SIMDLS_IMPL              (UL(0x1) << MVFR1_SIMDLS_SHIFT)
1355 #define MVFR1_SIMDInt_SHIFT             12
1356 #define MVFR1_SIMDInt_MASK              (UL(0xf) << MVFR1_SIMDInt_SHIFT)
1357 #define MVFR1_SIMDInt_VAL(x)            ((x) & MVFR1_SIMDInt_MASK)
1358 #define  MVFR1_SIMDInt_NONE             (UL(0x0) << MVFR1_SIMDInt_SHIFT)
1359 #define  MVFR1_SIMDInt_IMPL             (UL(0x1) << MVFR1_SIMDInt_SHIFT)
1360 #define MVFR1_SIMDSP_SHIFT              16
1361 #define MVFR1_SIMDSP_MASK               (UL(0xf) << MVFR1_SIMDSP_SHIFT)
1362 #define MVFR1_SIMDSP_VAL(x)             ((x) & MVFR1_SIMDSP_MASK)
1363 #define  MVFR1_SIMDSP_NONE              (UL(0x0) << MVFR1_SIMDSP_SHIFT)
1364 #define  MVFR1_SIMDSP_IMPL              (UL(0x1) << MVFR1_SIMDSP_SHIFT)
1365 #define MVFR1_SIMDHP_SHIFT              20
1366 #define MVFR1_SIMDHP_MASK               (UL(0xf) << MVFR1_SIMDHP_SHIFT)
1367 #define MVFR1_SIMDHP_VAL(x)             ((x) & MVFR1_SIMDHP_MASK)
1368 #define  MVFR1_SIMDHP_NONE              (UL(0x0) << MVFR1_SIMDHP_SHIFT)
1369 #define  MVFR1_SIMDHP_CONV_SP           (UL(0x1) << MVFR1_SIMDHP_SHIFT)
1370 #define  MVFR1_SIMDHP_ARITH             (UL(0x2) << MVFR1_SIMDHP_SHIFT)
1371 #define MVFR1_FPHP_SHIFT                24
1372 #define MVFR1_FPHP_MASK                 (UL(0xf) << MVFR1_FPHP_SHIFT)
1373 #define MVFR1_FPHP_VAL(x)               ((x) & MVFR1_FPHP_MASK)
1374 #define  MVFR1_FPHP_NONE                (UL(0x0) << MVFR1_FPHP_SHIFT)
1375 #define  MVFR1_FPHP_CONV_SP             (UL(0x1) << MVFR1_FPHP_SHIFT)
1376 #define  MVFR1_FPHP_CONV_DP             (UL(0x2) << MVFR1_FPHP_SHIFT)
1377 #define  MVFR1_FPHP_ARITH               (UL(0x3) << MVFR1_FPHP_SHIFT)
1378 #define MVFR1_SIMDFMAC_SHIFT            28
1379 #define MVFR1_SIMDFMAC_MASK             (UL(0xf) << MVFR1_SIMDFMAC_SHIFT)
1380 #define MVFR1_SIMDFMAC_VAL(x)           ((x) & MVFR1_SIMDFMAC_MASK)
1381 #define  MVFR1_SIMDFMAC_NONE            (UL(0x0) << MVFR1_SIMDFMAC_SHIFT)
1382 #define  MVFR1_SIMDFMAC_IMPL            (UL(0x1) << MVFR1_SIMDFMAC_SHIFT)
1383
1384 /* OSDLR_EL1 */
1385 #define OSDLR_EL1                       MRS_REG(OSDLR_EL1)
1386 #define OSDLR_EL1_op0                   2
1387 #define OSDLR_EL1_op1                   0
1388 #define OSDLR_EL1_CRn                   1
1389 #define OSDLR_EL1_CRm                   3
1390 #define OSDLR_EL1_op2                   4
1391
1392 /* OSLAR_EL1 */
1393 #define OSLAR_EL1                       MRS_REG(OSLAR_EL1)
1394 #define OSLAR_EL1_op0                   2
1395 #define OSLAR_EL1_op1                   0
1396 #define OSLAR_EL1_CRn                   1
1397 #define OSLAR_EL1_CRm                   0
1398 #define OSLAR_EL1_op2                   4
1399
1400 /* OSLSR_EL1 */
1401 #define OSLSR_EL1                       MRS_REG(OSLSR_EL1)
1402 #define OSLSR_EL1_op0                   2
1403 #define OSLSR_EL1_op1                   0
1404 #define OSLSR_EL1_CRn                   1
1405 #define OSLSR_EL1_CRm                   1
1406 #define OSLSR_EL1_op2                   4
1407
1408 /* PAR_EL1 - Physical Address Register */
1409 #define PAR_F_SHIFT             0
1410 #define PAR_F                   (0x1 << PAR_F_SHIFT)
1411 #define PAR_SUCCESS(x)          (((x) & PAR_F) == 0)
1412 /* When PAR_F == 0 (success) */
1413 #define PAR_LOW_MASK            0xfff
1414 #define PAR_SH_SHIFT            7
1415 #define PAR_SH_MASK             (0x3 << PAR_SH_SHIFT)
1416 #define PAR_NS_SHIFT            9
1417 #define PAR_NS_MASK             (0x3 << PAR_NS_SHIFT)
1418 #define PAR_PA_SHIFT            12
1419 #define PAR_PA_MASK             0x0000fffffffff000
1420 #define PAR_ATTR_SHIFT          56
1421 #define PAR_ATTR_MASK           (0xff << PAR_ATTR_SHIFT)
1422 /* When PAR_F == 1 (aborted) */
1423 #define PAR_FST_SHIFT           1
1424 #define PAR_FST_MASK            (0x3f << PAR_FST_SHIFT)
1425 #define PAR_PTW_SHIFT           8
1426 #define PAR_PTW_MASK            (0x1 << PAR_PTW_SHIFT)
1427 #define PAR_S_SHIFT             9
1428 #define PAR_S_MASK              (0x1 << PAR_S_SHIFT)
1429
1430 /* PMBIDR_EL1 */
1431 #define PMBIDR_EL1                      MRS_REG(PMBIDR_EL1)
1432 #define PMBIDR_EL1_op0                  0x3
1433 #define PMBIDR_EL1_op1                  0x0
1434 #define PMBIDR_EL1_CRn                  0x9
1435 #define PMBIDR_EL1_CRm                  0xa
1436 #define PMBIDR_EL1_op2                  0x7
1437 #define PMBIDR_Align_SHIFT              0
1438 #define PMBIDR_Align_MASK               (UL(0xf) << PMBIDR_Align_SHIFT)
1439 #define PMBIDR_P_SHIFT                  4
1440 #define PMBIDR_P                        (UL(0x1) << PMBIDR_P_SHIFT)
1441 #define PMBIDR_F_SHIFT                  5
1442 #define PMBIDR_F                        (UL(0x1) << PMBIDR_F_SHIFT)
1443
1444 /* PMBLIMITR_EL1 */
1445 #define PMBLIMITR_EL1                   MRS_REG(PMBLIMITR_EL1)
1446 #define PMBLIMITR_EL1_op0               0x3
1447 #define PMBLIMITR_EL1_op1               0x0
1448 #define PMBLIMITR_EL1_CRn               0x9
1449 #define PMBLIMITR_EL1_CRm               0xa
1450 #define PMBLIMITR_EL1_op2               0x0
1451 #define PMBLIMITR_E_SHIFT               0
1452 #define PMBLIMITR_E                     (UL(0x1) << PMBLIMITR_E_SHIFT)
1453 #define PMBLIMITR_FM_SHIFT              1
1454 #define PMBLIMITR_FM_MASK               (UL(0x3) << PMBLIMITR_FM_SHIFT)
1455 #define PMBLIMITR_PMFZ_SHIFT            5
1456 #define PMBLIMITR_PMFZ                  (UL(0x1) << PMBLIMITR_PMFZ_SHIFT)
1457 #define PMBLIMITR_LIMIT_SHIFT           12
1458 #define PMBLIMITR_LIMIT_MASK            \
1459     (UL(0xfffffffffffff) << PMBLIMITR_LIMIT_SHIFT)
1460
1461 /* PMBPTR_EL1 */
1462 #define PMBPTR_EL1                      MRS_REG(PMBPTR_EL1)
1463 #define PMBPTR_EL1_op0                  0x3
1464 #define PMBPTR_EL1_op1                  0x0
1465 #define PMBPTR_EL1_CRn                  0x9
1466 #define PMBPTR_EL1_CRm                  0xa
1467 #define PMBPTR_EL1_op2                  0x1
1468 #define PMBPTR_PTR_SHIFT                0
1469 #define PMBPTR_PTR_MASK                 \
1470     (UL(0xffffffffffffffff) << PMBPTR_PTR_SHIFT)
1471
1472 /* PMBSR_EL1 */
1473 #define PMBSR_EL1                       MRS_REG(PMBSR_EL1)
1474 #define PMBSR_EL1_op0                   0x3
1475 #define PMBSR_EL1_op1                   0x0
1476 #define PMBSR_EL1_CRn                   0x9
1477 #define PMBSR_EL1_CRm                   0xa
1478 #define PMBSR_EL1_op2                   0x3
1479 #define PMBSR_MSS_SHIFT                 0
1480 #define PMBSR_MSS_MASK                  (UL(0xffff) << PMBSR_MSS_SHIFT)
1481 #define PMBSR_COLL_SHIFT                16
1482 #define PMBSR_COLL                      (UL(0x1) << PMBSR_COLL_SHIFT)
1483 #define PMBSR_S_SHIFT                   17
1484 #define PMBSR_S                         (UL(0x1) << PMBSR_S_SHIFT)
1485 #define PMBSR_EA_SHIFT                  18
1486 #define PMBSR_EA                        (UL(0x1) << PMBSR_EA_SHIFT)
1487 #define PMBSR_DL_SHIFT                  19
1488 #define PMBSR_DL                        (UL(0x1) << PMBSR_DL_SHIFT)
1489 #define PMBSR_EC_SHIFT                  26
1490 #define PMBSR_EC_MASK                   (UL(0x3f) << PMBSR_EC_SHIFT)
1491
1492 /* PMCCFILTR_EL0 */
1493 #define PMCCFILTR_EL0                   MRS_REG(PMCCFILTR_EL0)
1494 #define PMCCFILTR_EL0_op0               3
1495 #define PMCCFILTR_EL0_op1               3
1496 #define PMCCFILTR_EL0_CRn               14
1497 #define PMCCFILTR_EL0_CRm               15
1498 #define PMCCFILTR_EL0_op2               7
1499
1500 /* PMCCNTR_EL0 */
1501 #define PMCCNTR_EL0                     MRS_REG(PMCCNTR_EL0)
1502 #define PMCCNTR_EL0_op0                 3
1503 #define PMCCNTR_EL0_op1                 3
1504 #define PMCCNTR_EL0_CRn                 9
1505 #define PMCCNTR_EL0_CRm                 13
1506 #define PMCCNTR_EL0_op2                 0
1507
1508 /* PMCEID0_EL0 */
1509 #define PMCEID0_EL0                     MRS_REG(PMCEID0_EL0)
1510 #define PMCEID0_EL0_op0                 3
1511 #define PMCEID0_EL0_op1                 3
1512 #define PMCEID0_EL0_CRn                 9
1513 #define PMCEID0_EL0_CRm                 12
1514 #define PMCEID0_EL0_op2                 6
1515
1516 /* PMCEID1_EL0 */
1517 #define PMCEID1_EL0                     MRS_REG(PMCEID1_EL0)
1518 #define PMCEID1_EL0_op0                 3
1519 #define PMCEID1_EL0_op1                 3
1520 #define PMCEID1_EL0_CRn                 9
1521 #define PMCEID1_EL0_CRm                 12
1522 #define PMCEID1_EL0_op2                 7
1523
1524 /* PMCNTENCLR_EL0 */
1525 #define PMCNTENCLR_EL0                  MRS_REG(PMCNTENCLR_EL0)
1526 #define PMCNTENCLR_EL0_op0              3
1527 #define PMCNTENCLR_EL0_op1              3
1528 #define PMCNTENCLR_EL0_CRn              9
1529 #define PMCNTENCLR_EL0_CRm              12
1530 #define PMCNTENCLR_EL0_op2              2
1531
1532 /* PMCNTENSET_EL0 */
1533 #define PMCNTENSET_EL0                  MRS_REG(PMCNTENSET_EL0)
1534 #define PMCNTENSET_EL0_op0              3
1535 #define PMCNTENSET_EL0_op1              3
1536 #define PMCNTENSET_EL0_CRn              9
1537 #define PMCNTENSET_EL0_CRm              12
1538 #define PMCNTENSET_EL0_op2              1
1539
1540 /* PMCR_EL0 - Perfomance Monitoring Counters */
1541 #define PMCR_EL0                        MRS_REG(PMCR_EL0)
1542 #define PMCR_EL0_op0                    3
1543 #define PMCR_EL0_op1                    3
1544 #define PMCR_EL0_CRn                    9
1545 #define PMCR_EL0_CRm                    12
1546 #define PMCR_EL0_op2                    0
1547 #define PMCR_E                          (1 << 0) /* Enable all counters */
1548 #define PMCR_P                          (1 << 1) /* Reset all counters */
1549 #define PMCR_C                          (1 << 2) /* Clock counter reset */
1550 #define PMCR_D                          (1 << 3) /* CNTR counts every 64 clk cycles */
1551 #define PMCR_X                          (1 << 4) /* Export to ext. monitoring (ETM) */
1552 #define PMCR_DP                         (1 << 5) /* Disable CCNT if non-invasive debug*/
1553 #define PMCR_LC                         (1 << 6) /* Long cycle count enable */
1554 #define PMCR_IMP_SHIFT                  24      /* Implementer code */
1555 #define PMCR_IMP_MASK                   (0xff << PMCR_IMP_SHIFT)
1556 #define  PMCR_IMP_ARM                   0x41
1557 #define PMCR_IDCODE_SHIFT               16      /* Identification code */
1558 #define PMCR_IDCODE_MASK                (0xff << PMCR_IDCODE_SHIFT)
1559 #define  PMCR_IDCODE_CORTEX_A57         0x01
1560 #define  PMCR_IDCODE_CORTEX_A72         0x02
1561 #define  PMCR_IDCODE_CORTEX_A53         0x03
1562 #define  PMCR_IDCODE_CORTEX_A73         0x04
1563 #define  PMCR_IDCODE_CORTEX_A35         0x0a
1564 #define  PMCR_IDCODE_CORTEX_A76         0x0b
1565 #define  PMCR_IDCODE_NEOVERSE_N1        0x0c
1566 #define  PMCR_IDCODE_CORTEX_A77         0x10
1567 #define  PMCR_IDCODE_CORTEX_A55         0x45
1568 #define  PMCR_IDCODE_NEOVERSE_E1        0x46
1569 #define  PMCR_IDCODE_CORTEX_A75         0x4a
1570 #define PMCR_N_SHIFT                    11  /* Number of counters implemented */
1571 #define PMCR_N_MASK                     (0x1f << PMCR_N_SHIFT)
1572
1573 /* PMEVCNTR<n>_EL0 */
1574 #define PMEVCNTR_EL0_op0                3
1575 #define PMEVCNTR_EL0_op1                3
1576 #define PMEVCNTR_EL0_CRn                14
1577 #define PMEVCNTR_EL0_CRm                8
1578 /*
1579  * PMEVCNTRn_EL0_CRm[1:0] holds the upper 2 bits of 'n'
1580  * PMEVCNTRn_EL0_op2 holds the lower 3 bits of 'n'
1581  */
1582
1583 /* PMEVTYPER<n>_EL0 - Performance Monitoring Event Type */
1584 #define PMEVTYPER_EL0_op0               3
1585 #define PMEVTYPER_EL0_op1               3
1586 #define PMEVTYPER_EL0_CRn               14
1587 #define PMEVTYPER_EL0_CRm               12
1588 /*
1589  * PMEVTYPERn_EL0_CRm[1:0] holds the upper 2 bits of 'n'
1590  * PMEVTYPERn_EL0_op2 holds the lower 3 bits of 'n'
1591  */
1592 #define PMEVTYPER_EVTCOUNT_MASK         0x000003ff /* ARMv8.0 */
1593 #define PMEVTYPER_EVTCOUNT_8_1_MASK     0x0000ffff /* ARMv8.1+ */
1594 #define PMEVTYPER_MT                    (1 << 25) /* Multithreading */
1595 #define PMEVTYPER_M                     (1 << 26) /* Secure EL3 filtering */
1596 #define PMEVTYPER_NSH                   (1 << 27) /* Non-secure hypervisor filtering */
1597 #define PMEVTYPER_NSU                   (1 << 28) /* Non-secure user filtering */
1598 #define PMEVTYPER_NSK                   (1 << 29) /* Non-secure kernel filtering */
1599 #define PMEVTYPER_U                     (1 << 30) /* User filtering */
1600 #define PMEVTYPER_P                     (1 << 31) /* Privileged filtering */
1601
1602 /* PMINTENCLR_EL1 */
1603 #define PMINTENCLR_EL1                  MRS_REG(PMINTENCLR_EL1)
1604 #define PMINTENCLR_EL1_op0              3
1605 #define PMINTENCLR_EL1_op1              0
1606 #define PMINTENCLR_EL1_CRn              9
1607 #define PMINTENCLR_EL1_CRm              14
1608 #define PMINTENCLR_EL1_op2              2
1609
1610 /* PMINTENSET_EL1 */
1611 #define PMINTENSET_EL1                  MRS_REG(PMINTENSET_EL1)
1612 #define PMINTENSET_EL1_op0              3
1613 #define PMINTENSET_EL1_op1              0
1614 #define PMINTENSET_EL1_CRn              9
1615 #define PMINTENSET_EL1_CRm              14
1616 #define PMINTENSET_EL1_op2              1
1617
1618 /* PMMIR_EL1 */
1619 #define PMMIR_EL1                       MRS_REG(PMMIR_EL1)
1620 #define PMMIR_EL1_op0                   3
1621 #define PMMIR_EL1_op1                   0
1622 #define PMMIR_EL1_CRn                   9
1623 #define PMMIR_EL1_CRm                   14
1624 #define PMMIR_EL1_op2                   6
1625
1626 /* PMOVSCLR_EL0 */
1627 #define PMOVSCLR_EL0                    MRS_REG(PMOVSCLR_EL0)
1628 #define PMOVSCLR_EL0_op0                3
1629 #define PMOVSCLR_EL0_op1                3
1630 #define PMOVSCLR_EL0_CRn                9
1631 #define PMOVSCLR_EL0_CRm                12
1632 #define PMOVSCLR_EL0_op2                3
1633
1634 /* PMOVSSET_EL0 */
1635 #define PMOVSSET_EL0                    MRS_REG(PMOVSSET_EL0)
1636 #define PMOVSSET_EL0_op0                3
1637 #define PMOVSSET_EL0_op1                3
1638 #define PMOVSSET_EL0_CRn                9
1639 #define PMOVSSET_EL0_CRm                14
1640 #define PMOVSSET_EL0_op2                3
1641
1642 /* PMSCR_EL1 */
1643 #define PMSCR_EL1                       MRS_REG(PMSCR_EL1)
1644 #define PMSCR_EL1_op0                   0x3
1645 #define PMSCR_EL1_op1                   0x0
1646 #define PMSCR_EL1_CRn                   0x9
1647 #define PMSCR_EL1_CRm                   0x9
1648 #define PMSCR_EL1_op2                   0x0
1649 #define PMSCR_E0SPE_SHIFT               0
1650 #define PMSCR_E0SPE                     (UL(0x1) << PMSCR_E0SPE_SHIFT)
1651 #define PMSCR_E1SPE_SHIFT               1
1652 #define PMSCR_E1SPE                     (UL(0x1) << PMSCR_E1SPE_SHIFT)
1653 #define PMSCR_CX_SHIFT                  3
1654 #define PMSCR_CX                        (UL(0x1) << PMSCR_CX_SHIFT)
1655 #define PMSCR_PA_SHIFT                  4
1656 #define PMSCR_PA                        (UL(0x1) << PMSCR_PA_SHIFT)
1657 #define PMSCR_TS_SHIFT                  5
1658 #define PMSCR_TS                        (UL(0x1) << PMSCR_TS_SHIFT)
1659 #define PMSCR_PCT_SHIFT                 6
1660 #define PMSCR_PCT_MASK                  (UL(0x3) << PMSCR_PCT_SHIFT)
1661
1662 /* PMSELR_EL0 */
1663 #define PMSELR_EL0                      MRS_REG(PMSELR_EL0)
1664 #define PMSELR_EL0_op0                  3
1665 #define PMSELR_EL0_op1                  3
1666 #define PMSELR_EL0_CRn                  9
1667 #define PMSELR_EL0_CRm                  12
1668 #define PMSELR_EL0_op2                  5
1669 #define PMSELR_SEL_MASK                 0x1f
1670
1671 /* PMSEVFR_EL1 */
1672 #define PMSEVFR_EL1                     MRS_REG(PMSEVFR_EL1)
1673 #define PMSEVFR_EL1_op0                 0x3
1674 #define PMSEVFR_EL1_op1                 0x0
1675 #define PMSEVFR_EL1_CRn                 0x9
1676 #define PMSEVFR_EL1_CRm                 0x9
1677 #define PMSEVFR_EL1_op2                 0x5
1678
1679 /* PMSFCR_EL1 */
1680 #define PMSFCR_EL1                      MRS_REG(PMSFCR_EL1)
1681 #define PMSFCR_EL1_op0                  0x3
1682 #define PMSFCR_EL1_op1                  0x0
1683 #define PMSFCR_EL1_CRn                  0x9
1684 #define PMSFCR_EL1_CRm                  0x9
1685 #define PMSFCR_EL1_op2                  0x4
1686 #define PMSFCR_FE_SHIFT                 0
1687 #define PMSFCR_FE                       (UL(0x1) << PMSFCR_FE_SHIFT)
1688 #define PMSFCR_FT_SHIFT                 1
1689 #define PMSFCR_FT                       (UL(0x1) << PMSFCR_FT_SHIFT)
1690 #define PMSFCR_FL_SHIFT                 2
1691 #define PMSFCR_FL                       (UL(0x1) << PMSFCR_FL_SHIFT)
1692 #define PMSFCR_FnE_SHIFT                3
1693 #define PMSFCR_FnE                      (UL(0x1) << PMSFCR_FnE_SHIFT)
1694 #define PMSFCR_B_SHIFT                  16
1695 #define PMSFCR_B                        (UL(0x1) << PMSFCR_B_SHIFT)
1696 #define PMSFCR_LD_SHIFT                 17
1697 #define PMSFCR_LD                       (UL(0x1) << PMSFCR_LD_SHIFT)
1698 #define PMSFCR_ST_SHIFT                 18
1699 #define PMSFCR_ST                       (UL(0x1) << PMSFCR_ST_SHIFT)
1700
1701 /* PMSICR_EL1 */
1702 #define PMSICR_EL1                      MRS_REG(PMSICR_EL1)
1703 #define PMSICR_EL1_op0                  0x3
1704 #define PMSICR_EL1_op1                  0x0
1705 #define PMSICR_EL1_CRn                  0x9
1706 #define PMSICR_EL1_CRm                  0x9
1707 #define PMSICR_EL1_op2                  0x2
1708 #define PMSICR_COUNT_SHIFT              0
1709 #define PMSICR_COUNT_MASK               (UL(0xffffffff) << PMSICR_COUNT_SHIFT)
1710 #define PMSICR_ECOUNT_SHIFT             56
1711 #define PMSICR_ECOUNT_MASK              (UL(0xff) << PMSICR_ECOUNT_SHIFT)
1712
1713 /* PMSIDR_EL1 */
1714 #define PMSIDR_EL1                      MRS_REG(PMSIDR_EL1)
1715 #define PMSIDR_EL1_op0                  0x3
1716 #define PMSIDR_EL1_op1                  0x0
1717 #define PMSIDR_EL1_CRn                  0x9
1718 #define PMSIDR_EL1_CRm                  0x9
1719 #define PMSIDR_EL1_op2                  0x7
1720 #define PMSIDR_FE_SHIFT                 0
1721 #define PMSIDR_FE                       (UL(0x1) << PMSIDR_FE_SHIFT)
1722 #define PMSIDR_FT_SHIFT                 1
1723 #define PMSIDR_FT                       (UL(0x1) << PMSIDR_FT_SHIFT)
1724 #define PMSIDR_FL_SHIFT                 2
1725 #define PMSIDR_FL                       (UL(0x1) << PMSIDR_FL_SHIFT)
1726 #define PMSIDR_ArchInst_SHIFT           3
1727 #define PMSIDR_ArchInst                 (UL(0x1) << PMSIDR_ArchInst_SHIFT)
1728 #define PMSIDR_LDS_SHIFT                4
1729 #define PMSIDR_LDS                      (UL(0x1) << PMSIDR_LDS_SHIFT)
1730 #define PMSIDR_ERnd_SHIFT               5
1731 #define PMSIDR_ERnd                     (UL(0x1) << PMSIDR_ERnd_SHIFT)
1732 #define PMSIDR_FnE_SHIFT                6
1733 #define PMSIDR_FnE                      (UL(0x1) << PMSIDR_FnE_SHIFT)
1734 #define PMSIDR_Interval_SHIFT           8
1735 #define PMSIDR_Interval_MASK            (UL(0xf) << PMSIDR_Interval_SHIFT)
1736 #define PMSIDR_MaxSize_SHIFT            12
1737 #define PMSIDR_MaxSize_MASK             (UL(0xf) << PMSIDR_MaxSize_SHIFT)
1738 #define PMSIDR_CountSize_SHIFT          16
1739 #define PMSIDR_CountSize_MASK           (UL(0xf) << PMSIDR_CountSize_SHIFT)
1740 #define PMSIDR_Format_SHIFT             20
1741 #define PMSIDR_Format_MASK              (UL(0xf) << PMSIDR_Format_SHIFT)
1742 #define PMSIDR_PBT_SHIFT                24
1743 #define PMSIDR_PBT                      (UL(0x1) << PMSIDR_PBT_SHIFT)
1744
1745 /* PMSIRR_EL1 */
1746 #define PMSIRR_EL1                      MRS_REG(PMSIRR_EL1)
1747 #define PMSIRR_EL1_op0                  0x3
1748 #define PMSIRR_EL1_op1                  0x0
1749 #define PMSIRR_EL1_CRn                  0x9
1750 #define PMSIRR_EL1_CRm                  0x9
1751 #define PMSIRR_EL1_op2                  0x3
1752 #define PMSIRR_RND_SHIFT                0
1753 #define PMSIRR_RND                      (UL(0x1) << PMSIRR_RND_SHIFT)
1754 #define PMSIRR_INTERVAL_SHIFT           8
1755 #define PMSIRR_INTERVAL_MASK            (UL(0xffffff) << PMSIRR_INTERVAL_SHIFT)
1756
1757 /* PMSLATFR_EL1 */
1758 #define PMSLATFR_EL1                    MRS_REG(PMSLATFR_EL1)
1759 #define PMSLATFR_EL1_op0                0x3
1760 #define PMSLATFR_EL1_op1                0x0
1761 #define PMSLATFR_EL1_CRn                0x9
1762 #define PMSLATFR_EL1_CRm                0x9
1763 #define PMSLATFR_EL1_op2                0x6
1764 #define PMSLATFR_MINLAT_SHIFT           0
1765 #define PMSLATFR_MINLAT_MASK            (UL(0xfff) << PMSLATFR_MINLAT_SHIFT)
1766
1767 /* PMSNEVFR_EL1 */
1768 #define PMSNEVFR_EL1                    MRS_REG(PMSNEVFR_EL1)
1769 #define PMSNEVFR_EL1_op0                0x3
1770 #define PMSNEVFR_EL1_op1                0x0
1771 #define PMSNEVFR_EL1_CRn                0x9
1772 #define PMSNEVFR_EL1_CRm                0x9
1773 #define PMSNEVFR_EL1_op2                0x1
1774
1775 /* PMSWINC_EL0 */
1776 #define PMSWINC_EL0                     MRS_REG(PMSWINC_EL0)
1777 #define PMSWINC_EL0_op0                 3
1778 #define PMSWINC_EL0_op1                 3
1779 #define PMSWINC_EL0_CRn                 9
1780 #define PMSWINC_EL0_CRm                 12
1781 #define PMSWINC_EL0_op2                 4
1782
1783 /* PMUSERENR_EL0 */
1784 #define PMUSERENR_EL0                   MRS_REG(PMUSERENR_EL0)
1785 #define PMUSERENR_EL0_op0               3
1786 #define PMUSERENR_EL0_op1               3
1787 #define PMUSERENR_EL0_CRn               9
1788 #define PMUSERENR_EL0_CRm               14
1789 #define PMUSERENR_EL0_op2               0
1790
1791 /* PMXEVCNTR_EL0 */
1792 #define PMXEVCNTR_EL0                   MRS_REG(PMXEVCNTR_EL0)
1793 #define PMXEVCNTR_EL0_op0               3
1794 #define PMXEVCNTR_EL0_op1               3
1795 #define PMXEVCNTR_EL0_CRn               9
1796 #define PMXEVCNTR_EL0_CRm               13
1797 #define PMXEVCNTR_EL0_op2               2
1798
1799 /* PMXEVTYPER_EL0 */
1800 #define PMXEVTYPER_EL0                  MRS_REG(PMXEVTYPER_EL0)
1801 #define PMXEVTYPER_EL0_op0              3
1802 #define PMXEVTYPER_EL0_op1              3
1803 #define PMXEVTYPER_EL0_CRn              9
1804 #define PMXEVTYPER_EL0_CRm              13
1805 #define PMXEVTYPER_EL0_op2              1
1806
1807 /* SCTLR_EL1 - System Control Register */
1808 #define SCTLR_RES1      0x30d00800      /* Reserved ARMv8.0, write 1 */
1809 #define SCTLR_M                         (UL(0x1) << 0)
1810 #define SCTLR_A                         (UL(0x1) << 1)
1811 #define SCTLR_C                         (UL(0x1) << 2)
1812 #define SCTLR_SA                        (UL(0x1) << 3)
1813 #define SCTLR_SA0                       (UL(0x1) << 4)
1814 #define SCTLR_CP15BEN                   (UL(0x1) << 5)
1815 #define SCTLR_nAA                       (UL(0x1) << 6)
1816 #define SCTLR_ITD                       (UL(0x1) << 7)
1817 #define SCTLR_SED                       (UL(0x1) << 8)
1818 #define SCTLR_UMA                       (UL(0x1) << 9)
1819 #define SCTLR_EnRCTX                    (UL(0x1) << 10)
1820 #define SCTLR_EOS                       (UL(0x1) << 11)
1821 #define SCTLR_I                         (UL(0x1) << 12)
1822 #define SCTLR_EnDB                      (UL(0x1) << 13)
1823 #define SCTLR_DZE                       (UL(0x1) << 14)
1824 #define SCTLR_UCT                       (UL(0x1) << 15)
1825 #define SCTLR_nTWI                      (UL(0x1) << 16)
1826 /* Bit 17 is reserved */
1827 #define SCTLR_nTWE                      (UL(0x1) << 18)
1828 #define SCTLR_WXN                       (UL(0x1) << 19)
1829 #define SCTLR_TSCXT                     (UL(0x1) << 20)
1830 #define SCTLR_IESB                      (UL(0x1) << 21)
1831 #define SCTLR_EIS                       (UL(0x1) << 22)
1832 #define SCTLR_SPAN                      (UL(0x1) << 23)
1833 #define SCTLR_E0E                       (UL(0x1) << 24)
1834 #define SCTLR_EE                        (UL(0x1) << 25)
1835 #define SCTLR_UCI                       (UL(0x1) << 26)
1836 #define SCTLR_EnDA                      (UL(0x1) << 27)
1837 #define SCTLR_nTLSMD                    (UL(0x1) << 28)
1838 #define SCTLR_LSMAOE                    (UL(0x1) << 29)
1839 #define SCTLR_EnIB                      (UL(0x1) << 30)
1840 #define SCTLR_EnIA                      (UL(0x1) << 31)
1841 /* Bits 34:32 are reserved */
1842 #define SCTLR_BT0                       (UL(0x1) << 35)
1843 #define SCTLR_BT1                       (UL(0x1) << 36)
1844 #define SCTLR_ITFSB                     (UL(0x1) << 37)
1845 #define SCTLR_TCF0_MASK                 (UL(0x3) << 38)
1846 #define SCTLR_TCF_MASK                  (UL(0x3) << 40)
1847 #define SCTLR_ATA0                      (UL(0x1) << 42)
1848 #define SCTLR_ATA                       (UL(0x1) << 43)
1849 #define SCTLR_DSSBS                     (UL(0x1) << 44)
1850 #define SCTLR_TWEDEn                    (UL(0x1) << 45)
1851 #define SCTLR_TWEDEL_MASK               (UL(0xf) << 46)
1852 /* Bits 53:50 are reserved */
1853 #define SCTLR_EnASR                     (UL(0x1) << 54)
1854 #define SCTLR_EnAS0                     (UL(0x1) << 55)
1855 #define SCTLR_EnALS                     (UL(0x1) << 56)
1856 #define SCTLR_EPAN                      (UL(0x1) << 57)
1857
1858 /* SPSR_EL1 */
1859 /*
1860  * When the exception is taken in AArch64:
1861  * M[3:2] is the exception level
1862  * M[1]   is unused
1863  * M[0]   is the SP select:
1864  *         0: always SP0
1865  *         1: current ELs SP
1866  */
1867 #define PSR_M_EL0t      0x00000000
1868 #define PSR_M_EL1t      0x00000004
1869 #define PSR_M_EL1h      0x00000005
1870 #define PSR_M_EL2t      0x00000008
1871 #define PSR_M_EL2h      0x00000009
1872 #define PSR_M_64        0x00000000
1873 #define PSR_M_32        0x00000010
1874 #define PSR_M_MASK      0x0000000f
1875
1876 #define PSR_T           0x00000020
1877
1878 #define PSR_AARCH32     0x00000010
1879 #define PSR_F           0x00000040
1880 #define PSR_I           0x00000080
1881 #define PSR_A           0x00000100
1882 #define PSR_D           0x00000200
1883 #define PSR_DAIF        (PSR_D | PSR_A | PSR_I | PSR_F)
1884 /* The default DAIF mask. These bits are valid in spsr_el1 and daif */
1885 #define PSR_DAIF_DEFAULT (PSR_F)
1886 #define PSR_IL          0x00100000
1887 #define PSR_SS          0x00200000
1888 #define PSR_V           0x10000000
1889 #define PSR_C           0x20000000
1890 #define PSR_Z           0x40000000
1891 #define PSR_N           0x80000000
1892 #define PSR_FLAGS       0xf0000000
1893 /* PSR fields that can be set from 32-bit and 64-bit processes */
1894 #define PSR_SETTABLE_32 PSR_FLAGS
1895 #define PSR_SETTABLE_64 (PSR_FLAGS | PSR_SS)
1896
1897 /* REVIDR_EL1 - Revision ID Register */
1898 #define REVIDR_EL1                      MRS_REG(REVIDR_EL1)
1899 #define REVIDR_EL1_op0                  3
1900 #define REVIDR_EL1_op1                  0
1901 #define REVIDR_EL1_CRn                  0
1902 #define REVIDR_EL1_CRm                  0
1903 #define REVIDR_EL1_op2                  6
1904
1905 /* TCR_EL1 - Translation Control Register */
1906 /* Bits 63:59 are reserved */
1907 #define TCR_TCMA1_SHIFT         58
1908 #define TCR_TCMA1               (1UL << TCR_TCMA1_SHIFT)
1909 #define TCR_TCMA0_SHIFT         57
1910 #define TCR_TCMA0               (1UL << TCR_TCMA0_SHIFT)
1911 #define TCR_E0PD1_SHIFT         56
1912 #define TCR_E0PD1               (1UL << TCR_E0PD1_SHIFT)
1913 #define TCR_E0PD0_SHIFT         55
1914 #define TCR_E0PD0               (1UL << TCR_E0PD0_SHIFT)
1915 #define TCR_NFD1_SHIFT          54
1916 #define TCR_NFD1                (1UL << TCR_NFD1_SHIFT)
1917 #define TCR_NFD0_SHIFT          53
1918 #define TCR_NFD0                (1UL << TCR_NFD0_SHIFT)
1919 #define TCR_TBID1_SHIFT         52
1920 #define TCR_TBID1               (1UL << TCR_TBID1_SHIFT)
1921 #define TCR_TBID0_SHIFT         51
1922 #define TCR_TBID0               (1UL << TCR_TBID0_SHIFT)
1923 #define TCR_HWU162_SHIFT        50
1924 #define TCR_HWU162              (1UL << TCR_HWU162_SHIFT)
1925 #define TCR_HWU161_SHIFT        49
1926 #define TCR_HWU161              (1UL << TCR_HWU161_SHIFT)
1927 #define TCR_HWU160_SHIFT        48
1928 #define TCR_HWU160              (1UL << TCR_HWU160_SHIFT)
1929 #define TCR_HWU159_SHIFT        47
1930 #define TCR_HWU159              (1UL << TCR_HWU159_SHIFT)
1931 #define TCR_HWU1                \
1932     (TCR_HWU159 | TCR_HWU160 | TCR_HWU161 | TCR_HWU162)
1933 #define TCR_HWU062_SHIFT        46
1934 #define TCR_HWU062              (1UL << TCR_HWU062_SHIFT)
1935 #define TCR_HWU061_SHIFT        45
1936 #define TCR_HWU061              (1UL << TCR_HWU061_SHIFT)
1937 #define TCR_HWU060_SHIFT        44
1938 #define TCR_HWU060              (1UL << TCR_HWU060_SHIFT)
1939 #define TCR_HWU059_SHIFT        43
1940 #define TCR_HWU059              (1UL << TCR_HWU059_SHIFT)
1941 #define TCR_HWU0                \
1942     (TCR_HWU059 | TCR_HWU060 | TCR_HWU061 | TCR_HWU062)
1943 #define TCR_HPD1_SHIFT          42
1944 #define TCR_HPD1                (1UL << TCR_HPD1_SHIFT)
1945 #define TCR_HPD0_SHIFT          41
1946 #define TCR_HPD0                (1UL << TCR_HPD0_SHIFT)
1947 #define TCR_HD_SHIFT            40
1948 #define TCR_HD                  (1UL << TCR_HD_SHIFT)
1949 #define TCR_HA_SHIFT            39
1950 #define TCR_HA                  (1UL << TCR_HA_SHIFT)
1951 #define TCR_TBI1_SHIFT          38
1952 #define TCR_TBI1                (1UL << TCR_TBI1_SHIFT)
1953 #define TCR_TBI0_SHIFT          37
1954 #define TCR_TBI0                (1U << TCR_TBI0_SHIFT)
1955 #define TCR_ASID_SHIFT          36
1956 #define TCR_ASID_WIDTH          1
1957 #define TCR_ASID_16             (1UL << TCR_ASID_SHIFT)
1958 /* Bit 35 is reserved */
1959 #define TCR_IPS_SHIFT           32
1960 #define TCR_IPS_WIDTH           3
1961 #define TCR_IPS_32BIT           (0UL << TCR_IPS_SHIFT)
1962 #define TCR_IPS_36BIT           (1UL << TCR_IPS_SHIFT)
1963 #define TCR_IPS_40BIT           (2UL << TCR_IPS_SHIFT)
1964 #define TCR_IPS_42BIT           (3UL << TCR_IPS_SHIFT)
1965 #define TCR_IPS_44BIT           (4UL << TCR_IPS_SHIFT)
1966 #define TCR_IPS_48BIT           (5UL << TCR_IPS_SHIFT)
1967 #define TCR_TG1_SHIFT           30
1968 #define TCR_TG1_16K             (1UL << TCR_TG1_SHIFT)
1969 #define TCR_TG1_4K              (2UL << TCR_TG1_SHIFT)
1970 #define TCR_TG1_64K             (3UL << TCR_TG1_SHIFT)
1971 #define TCR_SH1_SHIFT           28
1972 #define TCR_SH1_IS              (3UL << TCR_SH1_SHIFT)
1973 #define TCR_ORGN1_SHIFT         26
1974 #define TCR_ORGN1_WBWA          (1UL << TCR_ORGN1_SHIFT)
1975 #define TCR_IRGN1_SHIFT         24
1976 #define TCR_IRGN1_WBWA          (1UL << TCR_IRGN1_SHIFT)
1977 #define TCR_EPD1_SHIFT          23
1978 #define TCR_EPD1                (1UL << TCR_EPD1_SHIFT)
1979 #define TCR_A1_SHIFT            22
1980 #define TCR_A1                  (0x1UL << TCR_A1_SHIFT)
1981 #define TCR_T1SZ_SHIFT          16
1982 #define TCR_T1SZ(x)             ((x) << TCR_T1SZ_SHIFT)
1983 #define TCR_TG0_SHIFT           14
1984 #define TCR_TG0_4K              (0UL << TCR_TG0_SHIFT)
1985 #define TCR_TG0_64K             (1UL << TCR_TG0_SHIFT)
1986 #define TCR_TG0_16K             (2UL << TCR_TG0_SHIFT)
1987 #define TCR_SH0_SHIFT           12
1988 #define TCR_SH0_IS              (3UL << TCR_SH0_SHIFT)
1989 #define TCR_ORGN0_SHIFT         10
1990 #define TCR_ORGN0_WBWA          (1UL << TCR_ORGN0_SHIFT)
1991 #define TCR_IRGN0_SHIFT         8
1992 #define TCR_IRGN0_WBWA          (1UL << TCR_IRGN0_SHIFT)
1993 #define TCR_EPD0_SHIFT          7
1994 #define TCR_EPD0                (1UL << TCR_EPD1_SHIFT)
1995 /* Bit 6 is reserved */
1996 #define TCR_T0SZ_SHIFT          0
1997 #define TCR_T0SZ_MASK           0x3f
1998 #define TCR_T0SZ(x)             ((x) << TCR_T0SZ_SHIFT)
1999 #define TCR_TxSZ(x)             (TCR_T1SZ(x) | TCR_T0SZ(x))
2000
2001 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
2002                                 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
2003 #ifdef SMP
2004 #define TCR_SMP_ATTRS   (TCR_SH0_IS | TCR_SH1_IS)
2005 #else
2006 #define TCR_SMP_ATTRS   0
2007 #endif
2008
2009 /* TTBR0_EL1 & TTBR1_EL1 - Translation Table Base Register 0 & 1 */
2010 #define TTBR_ASID_SHIFT         48
2011 #define TTBR_ASID_MASK          (0xfffful << TTBR_ASID_SHIFT)
2012 #define TTBR_BADDR              0x0000fffffffffffeul
2013 #define TTBR_CnP_SHIFT          0
2014 #define TTBR_CnP                (1ul << TTBR_CnP_SHIFT)
2015
2016 /* ZCR_EL1 - SVE Control Register */
2017 #define ZCR_LEN_SHIFT           0
2018 #define ZCR_LEN_MASK            (0xf << ZCR_LEN_SHIFT)
2019 #define ZCR_LEN_BYTES(x)        ((((x) & ZCR_LEN_MASK) + 1) * 16)
2020
2021 #endif /* !_MACHINE_ARMREG_H_ */