sys/arm64/include/armreg.h

   1 /*-
   2  * Copyright (c) 2013, 2014 Andrew Turner
   3  * Copyright (c) 2015 The FreeBSD Foundation
   4  * All rights reserved.
   5  *
   6  * This software was developed by Andrew Turner under
   7  * sponsorship from the FreeBSD Foundation.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * $FreeBSD$
  31  */
  32
  33 #ifndef _MACHINE_ARMREG_H_
  34 #define _MACHINE_ARMREG_H_
  35
  36 #define INSN_SIZE               4
  37
  38 #define READ_SPECIALREG(reg)                                            \
  39 ({      uint64_t _val;                                                  \
  40         __asm __volatile("mrs   %0, " __STRING(reg) : "=&r" (_val));    \
  41         _val;                                                           \
  42 })
  43 #define WRITE_SPECIALREG(reg, _val)                                     \
  44         __asm __volatile("msr   " __STRING(reg) ", %0" : : "r"((uint64_t)_val))
  45
  46 #define UL(x)   UINT64_C(x)
  47
  48 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
  49 #define CNTHCTL_EVNTI_MASK      (0xf << 4) /* Bit to trigger event stream */
  50 #define CNTHCTL_EVNTDIR         (1 << 3) /* Control transition trigger bit */
  51 #define CNTHCTL_EVNTEN          (1 << 2) /* Enable event stream */
  52 #define CNTHCTL_EL1PCEN         (1 << 1) /* Allow EL0/1 physical timer access */
  53 #define CNTHCTL_EL1PCTEN        (1 << 0) /*Allow EL0/1 physical counter access*/
  54
  55 /* CPACR_EL1 */
  56 #define CPACR_FPEN_MASK         (0x3 << 20)
  57 #define  CPACR_FPEN_TRAP_ALL1   (0x0 << 20) /* Traps from EL0 and EL1 */
  58 #define  CPACR_FPEN_TRAP_EL0    (0x1 << 20) /* Traps from EL0 */
  59 #define  CPACR_FPEN_TRAP_ALL2   (0x2 << 20) /* Traps from EL0 and EL1 */
  60 #define  CPACR_FPEN_TRAP_NONE   (0x3 << 20) /* No traps */
  61 #define CPACR_TTA               (0x1 << 28)
  62
  63 /* CTR_EL0 - Cache Type Register */
  64 #define CTR_DLINE_SHIFT         16
  65 #define CTR_DLINE_MASK          (0xf << CTR_DLINE_SHIFT)
  66 #define CTR_DLINE_SIZE(reg)     (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
  67 #define CTR_ILINE_SHIFT         0
  68 #define CTR_ILINE_MASK          (0xf << CTR_ILINE_SHIFT)
  69 #define CTR_ILINE_SIZE(reg)     (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
  70
  71 /* DAIF - Interrupt Mask Bits */
  72 #define DAIF_D_MASKED           (1 << 9)
  73 #define DAIF_A_MASKED           (1 << 8)
  74 #define DAIF_I_MASKED           (1 << 7)
  75 #define DAIF_F_MASKED           (1 << 6)
  76
  77 /* DCZID_EL0 - Data Cache Zero ID register */
  78 #define DCZID_DZP               (1 << 4) /* DC ZVA prohibited if non-0 */
  79 #define DCZID_BS_SHIFT          0
  80 #define DCZID_BS_MASK           (0xf << DCZID_BS_SHIFT)
  81 #define DCZID_BS_SIZE(reg)      (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
  82
  83 /* ESR_ELx */
  84 #define ESR_ELx_ISS_MASK        0x00ffffff
  85 #define  ISS_INSN_FnV           (0x01 << 10)
  86 #define  ISS_INSN_EA            (0x01 << 9)
  87 #define  ISS_INSN_S1PTW         (0x01 << 7)
  88 #define  ISS_INSN_IFSC_MASK     (0x1f << 0)
  89 #define  ISS_DATA_ISV           (0x01 << 24)
  90 #define  ISS_DATA_SAS_MASK      (0x03 << 22)
  91 #define  ISS_DATA_SSE           (0x01 << 21)
  92 #define  ISS_DATA_SRT_MASK      (0x1f << 16)
  93 #define  ISS_DATA_SF            (0x01 << 15)
  94 #define  ISS_DATA_AR            (0x01 << 14)
  95 #define  ISS_DATA_FnV           (0x01 << 10)
  96 #define  ISS_DATA_EA            (0x01 << 9)
  97 #define  ISS_DATA_CM            (0x01 << 8)
  98 #define  ISS_DATA_S1PTW         (0x01 << 7)
  99 #define  ISS_DATA_WnR           (0x01 << 6)
 100 #define  ISS_DATA_DFSC_MASK     (0x3f << 0)
 101 #define  ISS_DATA_DFSC_ASF_L0   (0x00 << 0)
 102 #define  ISS_DATA_DFSC_ASF_L1   (0x01 << 0)
 103 #define  ISS_DATA_DFSC_ASF_L2   (0x02 << 0)
 104 #define  ISS_DATA_DFSC_ASF_L3   (0x03 << 0)
 105 #define  ISS_DATA_DFSC_TF_L0    (0x04 << 0)
 106 #define  ISS_DATA_DFSC_TF_L1    (0x05 << 0)
 107 #define  ISS_DATA_DFSC_TF_L2    (0x06 << 0)
 108 #define  ISS_DATA_DFSC_TF_L3    (0x07 << 0)
 109 #define  ISS_DATA_DFSC_AFF_L1   (0x09 << 0)
 110 #define  ISS_DATA_DFSC_AFF_L2   (0x0a << 0)
 111 #define  ISS_DATA_DFSC_AFF_L3   (0x0b << 0)
 112 #define  ISS_DATA_DFSC_PF_L1    (0x0d << 0)
 113 #define  ISS_DATA_DFSC_PF_L2    (0x0e << 0)
 114 #define  ISS_DATA_DFSC_PF_L3    (0x0f << 0)
 115 #define  ISS_DATA_DFSC_EXT      (0x10 << 0)
 116 #define  ISS_DATA_DFSC_EXT_L0   (0x14 << 0)
 117 #define  ISS_DATA_DFSC_EXT_L1   (0x15 << 0)
 118 #define  ISS_DATA_DFSC_EXT_L2   (0x16 << 0)
 119 #define  ISS_DATA_DFSC_EXT_L3   (0x17 << 0)
 120 #define  ISS_DATA_DFSC_ECC      (0x18 << 0)
 121 #define  ISS_DATA_DFSC_ECC_L0   (0x1c << 0)
 122 #define  ISS_DATA_DFSC_ECC_L1   (0x1d << 0)
 123 #define  ISS_DATA_DFSC_ECC_L2   (0x1e << 0)
 124 #define  ISS_DATA_DFSC_ECC_L3   (0x1f << 0)
 125 #define  ISS_DATA_DFSC_ALIGN    (0x21 << 0)
 126 #define  ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0)
 127 #define ESR_ELx_IL              (0x01 << 25)
 128 #define ESR_ELx_EC_SHIFT        26
 129 #define ESR_ELx_EC_MASK         (0x3f << 26)
 130 #define ESR_ELx_EXCEPTION(esr)  (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
 131 #define  EXCP_UNKNOWN           0x00    /* Unkwn exception */
 132 #define  EXCP_FP_SIMD           0x07    /* VFP/SIMD trap */
 133 #define  EXCP_ILL_STATE         0x0e    /* Illegal execution state */
 134 #define  EXCP_SVC32             0x11    /* SVC trap for AArch32 */
 135 #define  EXCP_SVC64             0x15    /* SVC trap for AArch64 */
 136 #define  EXCP_MSR               0x18    /* MSR/MRS trap */
 137 #define  EXCP_INSN_ABORT_L      0x20    /* Instruction abort, from lower EL */
 138 #define  EXCP_INSN_ABORT        0x21    /* Instruction abort, from same EL */
 139 #define  EXCP_PC_ALIGN          0x22    /* PC alignment fault */
 140 #define  EXCP_DATA_ABORT_L      0x24    /* Data abort, from lower EL */
 141 #define  EXCP_DATA_ABORT        0x25    /* Data abort, from same EL */
 142 #define  EXCP_SP_ALIGN          0x26    /* SP slignment fault */
 143 #define  EXCP_TRAP_FP           0x2c    /* Trapped FP exception */
 144 #define  EXCP_SERROR            0x2f    /* SError interrupt */
 145 #define  EXCP_SOFTSTP_EL0       0x32    /* Software Step, from lower EL */
 146 #define  EXCP_SOFTSTP_EL1       0x33    /* Software Step, from same EL */
 147 #define  EXCP_WATCHPT_EL1       0x35    /* Watchpoint, from same EL */
 148 #define  EXCP_BRK               0x3c    /* Breakpoint */
 149
 150 /* ICC_CTLR_EL1 */
 151 #define ICC_CTLR_EL1_EOIMODE    (1U << 1)
 152
 153 /* ICC_IAR1_EL1 */
 154 #define ICC_IAR1_EL1_SPUR       (0x03ff)
 155
 156 /* ICC_IGRPEN0_EL1 */
 157 #define ICC_IGRPEN0_EL1_EN      (1U << 0)
 158
 159 /* ICC_PMR_EL1 */
 160 #define ICC_PMR_EL1_PRIO_MASK   (0xFFUL)
 161
 162 /* ICC_SGI1R_EL1 */
 163 #define ICC_SGI1R_EL1_TL_MASK           0xffffUL
 164 #define ICC_SGI1R_EL1_AFF1_SHIFT        16
 165 #define ICC_SGI1R_EL1_SGIID_SHIFT       24
 166 #define ICC_SGI1R_EL1_AFF2_SHIFT        32
 167 #define ICC_SGI1R_EL1_AFF3_SHIFT        48
 168 #define ICC_SGI1R_EL1_SGIID_MASK        0xfUL
 169 #define ICC_SGI1R_EL1_IRM               (0x1UL << 40)
 170
 171 /* ICC_SRE_EL1 */
 172 #define ICC_SRE_EL1_SRE         (1U << 0)
 173
 174 /* ICC_SRE_EL2 */
 175 #define ICC_SRE_EL2_SRE         (1U << 0)
 176 #define ICC_SRE_EL2_EN          (1U << 3)
 177
 178 /* ID_AA64DFR0_EL1 */
 179 #define ID_AA64DFR0_MASK                UL(0x0000000ff0f0ffff)
 180 #define ID_AA64DFR0_DebugVer_SHIFT      0
 181 #define ID_AA64DFR0_DebugVer_MASK       (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)
 182 #define ID_AA64DFR0_DebugVer(x)         ((x) & ID_AA64DFR0_DebugVer_MASK)
 183 #define  ID_AA64DFR0_DebugVer_8         (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT)
 184 #define  ID_AA64DFR0_DebugVer_8_VHE     (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT)
 185 #define  ID_AA64DFR0_DebugVer_8_2       (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT)
 186 #define ID_AA64DFR0_TraceVer_SHIFT      4
 187 #define ID_AA64DFR0_TraceVer_MASK       (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT)
 188 #define ID_AA64DFR0_TraceVer(x)         ((x) & ID_AA64DFR0_TraceVer_MASK)
 189 #define  ID_AA64DFR0_TraceVer_NONE      (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT)
 190 #define  ID_AA64DFR0_TraceVer_IMPL      (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT)
 191 #define ID_AA64DFR0_PMUVer_SHIFT        8
 192 #define ID_AA64DFR0_PMUVer_MASK         (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
 193 #define ID_AA64DFR0_PMUVer(x)           ((x) & ID_AA64DFR0_PMUVer_MASK)
 194 #define  ID_AA64DFR0_PMUVer_NONE        (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT)
 195 #define  ID_AA64DFR0_PMUVer_3           (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT)
 196 #define  ID_AA64DFR0_PMUVer_3_1         (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT)
 197 #define  ID_AA64DFR0_PMUVer_IMPL        (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
 198 #define ID_AA64DFR0_BRPs_SHIFT          12
 199 #define ID_AA64DFR0_BRPs_MASK           (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT)
 200 #define ID_AA64DFR0_BRPs(x)             \
 201     ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1)
 202 #define ID_AA64DFR0_WRPs_SHIFT          20
 203 #define ID_AA64DFR0_WRPs_MASK           (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT)
 204 #define ID_AA64DFR0_WRPs(x)             \
 205     ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1)
 206 #define ID_AA64DFR0_CTX_CMPs_SHIFT      28
 207 #define ID_AA64DFR0_CTX_CMPs_MASK       (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT)
 208 #define ID_AA64DFR0_CTX_CMPs(x)         \
 209     ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1)
 210 #define ID_AA64DFR0_PMSVer_SHIFT        32
 211 #define ID_AA64DFR0_PMSVer_MASK         (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT)
 212 #define ID_AA64DFR0_PMSVer(x)           ((x) & ID_AA64DFR0_PMSVer_MASK)
 213 #define  ID_AA64DFR0_PMSVer_NONE        (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT)
 214 #define  ID_AA64DFR0_PMSVer_V1          (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT)
 215
 216 /* ID_AA64ISAR0_EL1 */
 217 #define ID_AA64ISAR0_MASK               UL(0x0000fffff0fffff0)
 218 #define ID_AA64ISAR0_AES_SHIFT          4
 219 #define ID_AA64ISAR0_AES_MASK           (UL(0xf) << ID_AA64ISAR0_AES_SHIFT)
 220 #define ID_AA64ISAR0_AES(x)             ((x) & ID_AA64ISAR0_AES_MASK)
 221 #define  ID_AA64ISAR0_AES_NONE          (UL(0x0) << ID_AA64ISAR0_AES_SHIFT)
 222 #define  ID_AA64ISAR0_AES_BASE          (UL(0x1) << ID_AA64ISAR0_AES_SHIFT)
 223 #define  ID_AA64ISAR0_AES_PMULL         (UL(0x2) << ID_AA64ISAR0_AES_SHIFT)
 224 #define ID_AA64ISAR0_SHA1_SHIFT         8
 225 #define ID_AA64ISAR0_SHA1_MASK          (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT)
 226 #define ID_AA64ISAR0_SHA1(x)            ((x) & ID_AA64ISAR0_SHA1_MASK)
 227 #define  ID_AA64ISAR0_SHA1_NONE         (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT)
 228 #define  ID_AA64ISAR0_SHA1_BASE         (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT)
 229 #define ID_AA64ISAR0_SHA2_SHIFT         12
 230 #define ID_AA64ISAR0_SHA2_MASK          (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT)
 231 #define ID_AA64ISAR0_SHA2(x)            ((x) & ID_AA64ISAR0_SHA2_MASK)
 232 #define  ID_AA64ISAR0_SHA2_NONE         (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT)
 233 #define  ID_AA64ISAR0_SHA2_BASE         (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT)
 234 #define  ID_AA64ISAR0_SHA2_512          (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT)
 235 #define ID_AA64ISAR0_CRC32_SHIFT        16
 236 #define ID_AA64ISAR0_CRC32_MASK         (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT)
 237 #define ID_AA64ISAR0_CRC32(x)           ((x) & ID_AA64ISAR0_CRC32_MASK)
 238 #define  ID_AA64ISAR0_CRC32_NONE        (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT)
 239 #define  ID_AA64ISAR0_CRC32_BASE        (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT)
 240 #define ID_AA64ISAR0_Atomic_SHIFT       20
 241 #define ID_AA64ISAR0_Atomic_MASK        (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT)
 242 #define ID_AA64ISAR0_Atomic(x)          ((x) & ID_AA64ISAR0_Atomic_MASK)
 243 #define  ID_AA64ISAR0_Atomic_NONE       (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT)
 244 #define  ID_AA64ISAR0_Atomic_IMPL       (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT)
 245 #define ID_AA64ISAR0_RDM_SHIFT          28
 246 #define ID_AA64ISAR0_RDM_MASK           (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT)
 247 #define ID_AA64ISAR0_RDM(x)             ((x) & ID_AA64ISAR0_RDM_MASK)
 248 #define  ID_AA64ISAR0_RDM_NONE          (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT)
 249 #define  ID_AA64ISAR0_RDM_IMPL          (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT)
 250 #define ID_AA64ISAR0_SHA3_SHIFT         32
 251 #define ID_AA64ISAR0_SHA3_MASK          (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT)
 252 #define ID_AA64ISAR0_SHA3(x)            ((x) & ID_AA64ISAR0_SHA3_MASK)
 253 #define  ID_AA64ISAR0_SHA3_NONE         (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT)
 254 #define  ID_AA64ISAR0_SHA3_IMPL         (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT)
 255 #define ID_AA64ISAR0_SM3_SHIFT          36
 256 #define ID_AA64ISAR0_SM3_MASK           (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT)
 257 #define ID_AA64ISAR0_SM3(x)             ((x) & ID_AA64ISAR0_SM3_MASK)
 258 #define  ID_AA64ISAR0_SM3_NONE          (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT)
 259 #define  ID_AA64ISAR0_SM3_IMPL          (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT)
 260 #define ID_AA64ISAR0_SM4_SHIFT          40
 261 #define ID_AA64ISAR0_SM4_MASK           (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT)
 262 #define ID_AA64ISAR0_SM4(x)             ((x) & ID_AA64ISAR0_SM4_MASK)
 263 #define  ID_AA64ISAR0_SM4_NONE          (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT)
 264 #define  ID_AA64ISAR0_SM4_IMPL          (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT)
 265 #define ID_AA64ISAR0_DP_SHIFT           44
 266 #define ID_AA64ISAR0_DP_MASK            (UL(0xf) << ID_AA64ISAR0_DP_SHIFT)
 267 #define ID_AA64ISAR0_DP(x)              ((x) & ID_AA64ISAR0_DP_MASK)
 268 #define  ID_AA64ISAR0_DP_NONE           (UL(0x0) << ID_AA64ISAR0_DP_SHIFT)
 269 #define  ID_AA64ISAR0_DP_IMPL           (UL(0x1) << ID_AA64ISAR0_DP_SHIFT)
 270
 271 /* ID_AA64ISAR1_EL1 */
 272 #define ID_AA64ISAR1_MASK               UL(0x00000000ffffffff)
 273 #define ID_AA64ISAR1_DPB_SHIFT          0
 274 #define ID_AA64ISAR1_DPB_MASK           (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
 275 #define ID_AA64ISAR1_DPB(x)             ((x) & ID_AA64ISAR1_DPB_MASK)
 276 #define  ID_AA64ISAR1_DPB_NONE          (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT)
 277 #define  ID_AA64ISAR1_DPB_IMPL          (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT)
 278 #define ID_AA64ISAR1_APA_SHIFT          4
 279 #define ID_AA64ISAR1_APA_MASK           (UL(0xf) << ID_AA64ISAR1_APA_SHIFT)
 280 #define ID_AA64ISAR1_APA(x)             ((x) & ID_AA64ISAR1_APA_MASK)
 281 #define  ID_AA64ISAR1_APA_NONE          (UL(0x0) << ID_AA64ISAR1_APA_SHIFT)
 282 #define  ID_AA64ISAR1_APA_IMPL          (UL(0x1) << ID_AA64ISAR1_APA_SHIFT)
 283 #define ID_AA64ISAR1_API_SHIFT          8
 284 #define ID_AA64ISAR1_API_MASK           (UL(0xf) << ID_AA64ISAR1_API_SHIFT)
 285 #define ID_AA64ISAR1_API(x)             ((x) & ID_AA64ISAR1_API_MASK)
 286 #define  ID_AA64ISAR1_API_NONE          (UL(0x0) << ID_AA64ISAR1_API_SHIFT)
 287 #define  ID_AA64ISAR1_API_IMPL          (UL(0x1) << ID_AA64ISAR1_API_SHIFT)
 288 #define ID_AA64ISAR1_JSCVT_SHIFT        12
 289 #define ID_AA64ISAR1_JSCVT_MASK         (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT)
 290 #define ID_AA64ISAR1_JSCVT(x)           ((x) & ID_AA64ISAR1_JSCVT_MASK)
 291 #define  ID_AA64ISAR1_JSCVT_NONE        (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT)
 292 #define  ID_AA64ISAR1_JSCVT_IMPL        (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT)
 293 #define ID_AA64ISAR1_FCMA_SHIFT         16
 294 #define ID_AA64ISAR1_FCMA_MASK          (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT)
 295 #define ID_AA64ISAR1_FCMA(x)            ((x) & ID_AA64ISAR1_FCMA_MASK)
 296 #define  ID_AA64ISAR1_FCMA_NONE         (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT)
 297 #define  ID_AA64ISAR1_FCMA_IMPL         (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT)
 298 #define ID_AA64ISAR1_LRCPC_SHIFT        20
 299 #define ID_AA64ISAR1_LRCPC_MASK         (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT)
 300 #define ID_AA64ISAR1_LRCPC(x)           ((x) & ID_AA64ISAR1_LRCPC_MASK)
 301 #define  ID_AA64ISAR1_LRCPC_NONE        (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT)
 302 #define  ID_AA64ISAR1_LRCPC_IMPL        (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT)
 303 #define ID_AA64ISAR1_GPA_SHIFT          24
 304 #define ID_AA64ISAR1_GPA_MASK           (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT)
 305 #define ID_AA64ISAR1_GPA(x)             ((x) & ID_AA64ISAR1_GPA_MASK)
 306 #define  ID_AA64ISAR1_GPA_NONE          (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT)
 307 #define  ID_AA64ISAR1_GPA_IMPL          (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT)
 308 #define ID_AA64ISAR1_GPI_SHIFT          28
 309 #define ID_AA64ISAR1_GPI_MASK           (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT)
 310 #define ID_AA64ISAR1_GPI(x)             ((x) & ID_AA64ISAR1_GPI_MASK)
 311 #define  ID_AA64ISAR1_GPI_NONE          (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT)
 312 #define  ID_AA64ISAR1_GPI_IMPL          (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT)
 313
 314 /* ID_AA64MMFR0_EL1 */
 315 #define ID_AA64MMFR0_MASK               UL(0x00000000ffffffff)
 316 #define ID_AA64MMFR0_PARange_SHIFT      0
 317 #define ID_AA64MMFR0_PARange_MASK       (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
 318 #define ID_AA64MMFR0_PARange(x)         ((x) & ID_AA64MMFR0_PARange_MASK)
 319 #define  ID_AA64MMFR0_PARange_4G        (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT)
 320 #define  ID_AA64MMFR0_PARange_64G       (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT)
 321 #define  ID_AA64MMFR0_PARange_1T        (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT)
 322 #define  ID_AA64MMFR0_PARange_4T        (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT)
 323 #define  ID_AA64MMFR0_PARange_16T       (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT)
 324 #define  ID_AA64MMFR0_PARange_256T      (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT)
 325 #define  ID_AA64MMFR0_PARange_4P        (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT)
 326 #define ID_AA64MMFR0_ASIDBits_SHIFT     4
 327 #define ID_AA64MMFR0_ASIDBits_MASK      (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT)
 328 #define ID_AA64MMFR0_ASIDBits(x)        ((x) & ID_AA64MMFR0_ASIDBits_MASK)
 329 #define  ID_AA64MMFR0_ASIDBits_8        (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT)
 330 #define  ID_AA64MMFR0_ASIDBits_16       (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT)
 331 #define ID_AA64MMFR0_BigEnd_SHIFT       8
 332 #define ID_AA64MMFR0_BigEnd_MASK        (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT)
 333 #define ID_AA64MMFR0_BigEnd(x)          ((x) & ID_AA64MMFR0_BigEnd_MASK)
 334 #define  ID_AA64MMFR0_BigEnd_FIXED      (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT)
 335 #define  ID_AA64MMFR0_BigEnd_MIXED      (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT)
 336 #define ID_AA64MMFR0_SNSMem_SHIFT       12
 337 #define ID_AA64MMFR0_SNSMem_MASK        (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT)
 338 #define ID_AA64MMFR0_SNSMem(x)          ((x) & ID_AA64MMFR0_SNSMem_MASK)
 339 #define  ID_AA64MMFR0_SNSMem_NONE       (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT)
 340 #define  ID_AA64MMFR0_SNSMem_DISTINCT   (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT)
 341 #define ID_AA64MMFR0_BigEndEL0_SHIFT    16
 342 #define ID_AA64MMFR0_BigEndEL0_MASK     (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT)
 343 #define ID_AA64MMFR0_BigEndEL0(x)       ((x) & ID_AA64MMFR0_BigEndEL0_MASK)
 344 #define  ID_AA64MMFR0_BigEndEL0_FIXED   (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT)
 345 #define  ID_AA64MMFR0_BigEndEL0_MIXED   (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT)
 346 #define ID_AA64MMFR0_TGran16_SHIFT      20
 347 #define ID_AA64MMFR0_TGran16_MASK       (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT)
 348 #define ID_AA64MMFR0_TGran16(x)         ((x) & ID_AA64MMFR0_TGran16_MASK)
 349 #define  ID_AA64MMFR0_TGran16_NONE      (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT)
 350 #define  ID_AA64MMFR0_TGran16_IMPL      (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT)
 351 #define ID_AA64MMFR0_TGran64_SHIFT      24
 352 #define ID_AA64MMFR0_TGran64_MASK       (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
 353 #define ID_AA64MMFR0_TGran64(x)         ((x) & ID_AA64MMFR0_TGran64_MASK)
 354 #define  ID_AA64MMFR0_TGran64_IMPL      (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT)
 355 #define  ID_AA64MMFR0_TGran64_NONE      (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
 356 #define ID_AA64MMFR0_TGran4_SHIFT       28
 357 #define ID_AA64MMFR0_TGran4_MASK        (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
 358 #define ID_AA64MMFR0_TGran4(x)          ((x) & ID_AA64MMFR0_TGran4_MASK)
 359 #define  ID_AA64MMFR0_TGran4_IMPL       (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT)
 360 #define  ID_AA64MMFR0_TGran4_NONE       (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
 361
 362 /* ID_AA64MMFR1_EL1 */
 363 #define ID_AA64MMFR1_MASK               UL(0x00000000ffffffff)
 364 #define ID_AA64MMFR1_HAFDBS_SHIFT       0
 365 #define ID_AA64MMFR1_HAFDBS_MASK        (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
 366 #define ID_AA64MMFR1_HAFDBS(x)          ((x) & ID_AA64MMFR1_HAFDBS_MASK)
 367 #define  ID_AA64MMFR1_HAFDBS_NONE       (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT)
 368 #define  ID_AA64MMFR1_HAFDBS_AF         (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT)
 369 #define  ID_AA64MMFR1_HAFDBS_AF_DBS     (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT)
 370 #define ID_AA64MMFR1_VMIDBits_SHIFT     4
 371 #define ID_AA64MMFR1_VMIDBits_MASK      (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT)
 372 #define ID_AA64MMFR1_VMIDBits(x)        ((x) & ID_AA64MMFR1_VMIDBits_MASK)
 373 #define  ID_AA64MMFR1_VMIDBits_8        (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT)
 374 #define  ID_AA64MMFR1_VMIDBits_16       (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT)
 375 #define ID_AA64MMFR1_VH_SHIFT           8
 376 #define ID_AA64MMFR1_VH_MASK            (UL(0xf) << ID_AA64MMFR1_VH_SHIFT)
 377 #define ID_AA64MMFR1_VH(x)              ((x) & ID_AA64MMFR1_VH_MASK)
 378 #define  ID_AA64MMFR1_VH_NONE           (UL(0x0) << ID_AA64MMFR1_VH_SHIFT)
 379 #define  ID_AA64MMFR1_VH_IMPL           (UL(0x1) << ID_AA64MMFR1_VH_SHIFT)
 380 #define ID_AA64MMFR1_HPDS_SHIFT         12
 381 #define ID_AA64MMFR1_HPDS_MASK          (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT)
 382 #define ID_AA64MMFR1_HPDS(x)            ((x) & ID_AA64MMFR1_HPDS_MASK)
 383 #define  ID_AA64MMFR1_HPDS_NONE         (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT)
 384 #define  ID_AA64MMFR1_HPDS_HPD          (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT)
 385 #define  ID_AA64MMFR1_HPDS_TTPBHA       (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT)
 386 #define ID_AA64MMFR1_LO_SHIFT           16
 387 #define ID_AA64MMFR1_LO_MASK            (UL(0xf) << ID_AA64MMFR1_LO_SHIFT)
 388 #define ID_AA64MMFR1_LO(x)              ((x) & ID_AA64MMFR1_LO_MASK)
 389 #define  ID_AA64MMFR1_LO_NONE           (UL(0x0) << ID_AA64MMFR1_LO_SHIFT)
 390 #define  ID_AA64MMFR1_LO_IMPL           (UL(0x1) << ID_AA64MMFR1_LO_SHIFT)
 391 #define ID_AA64MMFR1_PAN_SHIFT          20
 392 #define ID_AA64MMFR1_PAN_MASK           (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT)
 393 #define ID_AA64MMFR1_PAN(x)             ((x) & ID_AA64MMFR1_PAN_MASK)
 394 #define  ID_AA64MMFR1_PAN_NONE          (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT)
 395 #define  ID_AA64MMFR1_PAN_IMPL          (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT)
 396 #define  ID_AA64MMFR1_PAN_ATS1E1        (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT)
 397 #define ID_AA64MMFR1_SpecSEI_SHIFT      24
 398 #define ID_AA64MMFR1_SpecSEI_MASK       (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT)
 399 #define ID_AA64MMFR1_SpecSEI(x)         ((x) & ID_AA64MMFR1_SpecSEI_MASK)
 400 #define  ID_AA64MMFR1_SpecSEI_NONE      (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT)
 401 #define  ID_AA64MMFR1_SpecSEI_IMPL      (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT)
 402 #define ID_AA64MMFR1_XNX_SHIFT          28
 403 #define ID_AA64MMFR1_XNX_MASK           (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT)
 404 #define ID_AA64MMFR1_XNX(x)             ((x) & ID_AA64MMFR1_XNX_MASK)
 405 #define  ID_AA64MMFR1_XNX_NONE          (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT)
 406 #define  ID_AA64MMFR1_XNX_IMPL          (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT)
 407
 408 /* ID_AA64MMFR2_EL1 */
 409 #define ID_AA64MMFR2_EL1                S3_0_C0_C7_2
 410 #define ID_AA64MMFR2_MASK               UL(0x000000000fffffff)
 411 #define ID_AA64MMFR2_CnP_SHIFT          0
 412 #define ID_AA64MMFR2_CnP_MASK           (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT)
 413 #define ID_AA64MMFR2_CnP(x)             ((x) & ID_AA64MMFR2_CnP_MASK)
 414 #define  ID_AA64MMFR2_CnP_NONE          (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT)
 415 #define  ID_AA64MMFR2_CnP_IMPL          (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT)
 416 #define ID_AA64MMFR2_UAO_SHIFT          4
 417 #define ID_AA64MMFR2_UAO_MASK           (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT)
 418 #define ID_AA64MMFR2_UAO(x)             ((x) & ID_AA64MMFR2_UAO_MASK)
 419 #define  ID_AA64MMFR2_UAO_NONE          (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT)
 420 #define  ID_AA64MMFR2_UAO_IMPL          (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT)
 421 #define ID_AA64MMFR2_LSM_SHIFT          8
 422 #define ID_AA64MMFR2_LSM_MASK           (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT)
 423 #define ID_AA64MMFR2_LSM(x)             ((x) & ID_AA64MMFR2_LSM_MASK)
 424 #define  ID_AA64MMFR2_LSM_NONE          (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT)
 425 #define  ID_AA64MMFR2_LSM_IMPL          (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT)
 426 #define ID_AA64MMFR2_IESB_SHIFT         12
 427 #define ID_AA64MMFR2_IESB_MASK          (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT)
 428 #define ID_AA64MMFR2_IESB(x)            ((x) & ID_AA64MMFR2_IESB_MASK)
 429 #define  ID_AA64MMFR2_IESB_NONE         (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT)
 430 #define  ID_AA64MMFR2_IESB_IMPL         (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT)
 431 #define ID_AA64MMFR2_VARange_SHIFT      16
 432 #define ID_AA64MMFR2_VARange_MASK       (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT)
 433 #define ID_AA64MMFR2_VARange(x)         ((x) & ID_AA64MMFR2_VARange_MASK)
 434 #define  ID_AA64MMFR2_VARange_48        (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT)
 435 #define  ID_AA64MMFR2_VARange_52        (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT)
 436 #define ID_AA64MMFR2_CCIDX_SHIFT        20
 437 #define ID_AA64MMFR2_CCIDX_MASK         (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT)
 438 #define ID_AA64MMFR2_CCIDX(x)           ((x) & ID_AA64MMFR2_CCIDX_MASK)
 439 #define  ID_AA64MMFR2_CCIDX_32          (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT)
 440 #define  ID_AA64MMFR2_CCIDX_64          (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT)
 441 #define ID_AA64MMFR2_NV_SHIFT           24
 442 #define ID_AA64MMFR2_NV_MASK            (UL(0xf) << ID_AA64MMFR2_NV_SHIFT)
 443 #define ID_AA64MMFR2_NV(x)              ((x) & ID_AA64MMFR2_NV_MASK)
 444 #define  ID_AA64MMFR2_NV_NONE           (UL(0x0) << ID_AA64MMFR2_NV_SHIFT)
 445 #define  ID_AA64MMFR2_NV_IMPL           (UL(0x1) << ID_AA64MMFR2_NV_SHIFT)
 446
 447 /* ID_AA64PFR0_EL1 */
 448 #define ID_AA64PFR0_MASK                UL(0x0000000fffffffff)
 449 #define ID_AA64PFR0_EL0_SHIFT           0
 450 #define ID_AA64PFR0_EL0_MASK            (UL(0xf) << ID_AA64PFR0_EL0_SHIFT)
 451 #define ID_AA64PFR0_EL0(x)              ((x) & ID_AA64PFR0_EL0_MASK)
 452 #define  ID_AA64PFR0_EL0_64             (UL(0x1) << ID_AA64PFR0_EL0_SHIFT)
 453 #define  ID_AA64PFR0_EL0_64_32          (UL(0x2) << ID_AA64PFR0_EL0_SHIFT)
 454 #define ID_AA64PFR0_EL1_SHIFT           4
 455 #define ID_AA64PFR0_EL1_MASK            (UL(0xf) << ID_AA64PFR0_EL1_SHIFT)
 456 #define ID_AA64PFR0_EL1(x)              ((x) & ID_AA64PFR0_EL1_MASK)
 457 #define  ID_AA64PFR0_EL1_64             (UL(0x1) << ID_AA64PFR0_EL1_SHIFT)
 458 #define  ID_AA64PFR0_EL1_64_32          (UL(0x2) << ID_AA64PFR0_EL1_SHIFT)
 459 #define ID_AA64PFR0_EL2_SHIFT           8
 460 #define ID_AA64PFR0_EL2_MASK            (UL(0xf) << ID_AA64PFR0_EL2_SHIFT)
 461 #define ID_AA64PFR0_EL2(x)              ((x) & ID_AA64PFR0_EL2_MASK)
 462 #define  ID_AA64PFR0_EL2_NONE           (UL(0x0) << ID_AA64PFR0_EL2_SHIFT)
 463 #define  ID_AA64PFR0_EL2_64             (UL(0x1) << ID_AA64PFR0_EL2_SHIFT)
 464 #define  ID_AA64PFR0_EL2_64_32          (UL(0x2) << ID_AA64PFR0_EL2_SHIFT)
 465 #define ID_AA64PFR0_EL3_SHIFT           12
 466 #define ID_AA64PFR0_EL3_MASK            (UL(0xf) << ID_AA64PFR0_EL3_SHIFT)
 467 #define ID_AA64PFR0_EL3(x)              ((x) & ID_AA64PFR0_EL3_MASK)
 468 #define  ID_AA64PFR0_EL3_NONE           (UL(0x0) << ID_AA64PFR0_EL3_SHIFT)
 469 #define  ID_AA64PFR0_EL3_64             (UL(0x1) << ID_AA64PFR0_EL3_SHIFT)
 470 #define  ID_AA64PFR0_EL3_64_32          (UL(0x2) << ID_AA64PFR0_EL3_SHIFT)
 471 #define ID_AA64PFR0_FP_SHIFT            16
 472 #define ID_AA64PFR0_FP_MASK             (UL(0xf) << ID_AA64PFR0_FP_SHIFT)
 473 #define ID_AA64PFR0_FP(x)               ((x) & ID_AA64PFR0_FP_MASK)
 474 #define  ID_AA64PFR0_FP_IMPL            (UL(0x0) << ID_AA64PFR0_FP_SHIFT)
 475 #define  ID_AA64PFR0_FP_HP              (UL(0x1) << ID_AA64PFR0_FP_SHIFT)
 476 #define  ID_AA64PFR0_FP_NONE            (UL(0xf) << ID_AA64PFR0_FP_SHIFT)
 477 #define ID_AA64PFR0_AdvSIMD_SHIFT       20
 478 #define ID_AA64PFR0_AdvSIMD_MASK        (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
 479 #define ID_AA64PFR0_AdvSIMD(x)          ((x) & ID_AA64PFR0_AdvSIMD_MASK)
 480 #define  ID_AA64PFR0_AdvSIMD_IMPL       (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT)
 481 #define  ID_AA64PFR0_AdvSIMD_HP         (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT)
 482 #define  ID_AA64PFR0_AdvSIMD_NONE       (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
 483 #define ID_AA64PFR0_GIC_BITS            0x4 /* Number of bits in GIC field */
 484 #define ID_AA64PFR0_GIC_SHIFT           24
 485 #define ID_AA64PFR0_GIC_MASK            (UL(0xf) << ID_AA64PFR0_GIC_SHIFT)
 486 #define ID_AA64PFR0_GIC(x)              ((x) & ID_AA64PFR0_GIC_MASK)
 487 #define  ID_AA64PFR0_GIC_CPUIF_NONE     (UL(0x0) << ID_AA64PFR0_GIC_SHIFT)
 488 #define  ID_AA64PFR0_GIC_CPUIF_EN       (UL(0x1) << ID_AA64PFR0_GIC_SHIFT)
 489 #define ID_AA64PFR0_RAS_SHIFT           28
 490 #define ID_AA64PFR0_RAS_MASK            (UL(0xf) << ID_AA64PFR0_RAS_SHIFT)
 491 #define ID_AA64PFR0_RAS(x)              ((x) & ID_AA64PFR0_RAS_MASK)
 492 #define  ID_AA64PFR0_RAS_NONE           (UL(0x0) << ID_AA64PFR0_RAS_SHIFT)
 493 #define  ID_AA64PFR0_RAS_V1             (UL(0x1) << ID_AA64PFR0_RAS_SHIFT)
 494 #define ID_AA64PFR0_SVE_SHIFT           32
 495 #define ID_AA64PFR0_SVE_MASK            (UL(0xf) << ID_AA64PFR0_SVE_SHIFT)
 496 #define ID_AA64PFR0_SVE(x)              ((x) & ID_AA64PFR0_SVE_MASK)
 497 #define  ID_AA64PFR0_SVE_NONE           (UL(0x0) << ID_AA64PFR0_SVE_SHIFT)
 498 #define  ID_AA64PFR0_SVE_IMPL           (UL(0x1) << ID_AA64PFR0_SVE_SHIFT)
 499
 500 /* MAIR_EL1 - Memory Attribute Indirection Register */
 501 #define MAIR_ATTR_MASK(idx)     (0xff << ((n)* 8))
 502 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
 503 #define  MAIR_DEVICE_nGnRnE     0x00
 504 #define  MAIR_NORMAL_NC         0x44
 505 #define  MAIR_NORMAL_WT         0xbb
 506 #define  MAIR_NORMAL_WB         0xff
 507
 508 /* PAR_EL1 - Physical Address Register */
 509 #define PAR_F_SHIFT             0
 510 #define PAR_F                   (0x1 << PAR_F_SHIFT)
 511 #define PAR_SUCCESS(x)          (((x) & PAR_F) == 0)
 512 /* When PAR_F == 0 (success) */
 513 #define PAR_SH_SHIFT            7
 514 #define PAR_SH_MASK             (0x3 << PAR_SH_SHIFT)
 515 #define PAR_NS_SHIFT            9
 516 #define PAR_NS_MASK             (0x3 << PAR_NS_SHIFT)
 517 #define PAR_PA_SHIFT            12
 518 #define PAR_PA_MASK             0x0000fffffffff000
 519 #define PAR_ATTR_SHIFT          56
 520 #define PAR_ATTR_MASK           (0xff << PAR_ATTR_SHIFT)
 521 /* When PAR_F == 1 (aborted) */
 522 #define PAR_FST_SHIFT           1
 523 #define PAR_FST_MASK            (0x3f << PAR_FST_SHIFT)
 524 #define PAR_PTW_SHIFT           8
 525 #define PAR_PTW_MASK            (0x1 << PAR_PTW_SHIFT)
 526 #define PAR_S_SHIFT             9
 527 #define PAR_S_MASK              (0x1 << PAR_S_SHIFT)
 528
 529 /* SCTLR_EL1 - System Control Register */
 530 #define SCTLR_RES0      0xc8222440      /* Reserved ARMv8.0, write 0 */
 531 #define SCTLR_RES1      0x30d00800      /* Reserved ARMv8.0, write 1 */
 532
 533 #define SCTLR_M         0x00000001
 534 #define SCTLR_A         0x00000002
 535 #define SCTLR_C         0x00000004
 536 #define SCTLR_SA        0x00000008
 537 #define SCTLR_SA0       0x00000010
 538 #define SCTLR_CP15BEN   0x00000020
 539 /* Bit 6 is reserved */
 540 #define SCTLR_ITD       0x00000080
 541 #define SCTLR_SED       0x00000100
 542 #define SCTLR_UMA       0x00000200
 543 /* Bit 10 is reserved */
 544 /* Bit 11 is reserved */
 545 #define SCTLR_I         0x00001000
 546 #define SCTLR_EnDB      0x00002000 /* ARMv8.3 */
 547 #define SCTLR_DZE       0x00004000
 548 #define SCTLR_UCT       0x00008000
 549 #define SCTLR_nTWI      0x00010000
 550 /* Bit 17 is reserved */
 551 #define SCTLR_nTWE      0x00040000
 552 #define SCTLR_WXN       0x00080000
 553 /* Bit 20 is reserved */
 554 #define SCTLR_IESB      0x00200000 /* ARMv8.2 */
 555 /* Bit 22 is reserved */
 556 #define SCTLR_SPAN      0x00800000 /* ARMv8.1 */
 557 #define SCTLR_EOE       0x01000000
 558 #define SCTLR_EE        0x02000000
 559 #define SCTLR_UCI       0x04000000
 560 #define SCTLR_EnDA      0x08000000 /* ARMv8.3 */
 561 #define SCTLR_nTLSMD    0x10000000 /* ARMv8.2 */
 562 #define SCTLR_LSMAOE    0x20000000 /* ARMv8.2 */
 563 #define SCTLR_EnIB      0x40000000 /* ARMv8.3 */
 564 #define SCTLR_EnIA      0x80000000 /* ARMv8.3 */
 565
 566 /* SPSR_EL1 */
 567 /*
 568  * When the exception is taken in AArch64:
 569  * M[3:2] is the exception level
 570  * M[1]   is unused
 571  * M[0]   is the SP select:
 572  *         0: always SP0
 573  *         1: current ELs SP
 574  */
 575 #define PSR_M_EL0t      0x00000000
 576 #define PSR_M_EL1t      0x00000004
 577 #define PSR_M_EL1h      0x00000005
 578 #define PSR_M_EL2t      0x00000008
 579 #define PSR_M_EL2h      0x00000009
 580 #define PSR_M_64        0x00000000
 581 #define PSR_M_32        0x00000010
 582 #define PSR_M_MASK      0x0000000f
 583
 584 #define PSR_T           0x00000020
 585
 586 #define PSR_AARCH32     0x00000010
 587 #define PSR_F           0x00000040
 588 #define PSR_I           0x00000080
 589 #define PSR_A           0x00000100
 590 #define PSR_D           0x00000200
 591 #define PSR_IL          0x00100000
 592 #define PSR_SS          0x00200000
 593 #define PSR_V           0x10000000
 594 #define PSR_C           0x20000000
 595 #define PSR_Z           0x40000000
 596 #define PSR_N           0x80000000
 597 #define PSR_FLAGS       0xf0000000
 598
 599 /* TCR_EL1 - Translation Control Register */
 600 #define TCR_ASID_16     (1 << 36)
 601
 602 #define TCR_IPS_SHIFT   32
 603 #define TCR_IPS_32BIT   (0 << TCR_IPS_SHIFT)
 604 #define TCR_IPS_36BIT   (1 << TCR_IPS_SHIFT)
 605 #define TCR_IPS_40BIT   (2 << TCR_IPS_SHIFT)
 606 #define TCR_IPS_42BIT   (3 << TCR_IPS_SHIFT)
 607 #define TCR_IPS_44BIT   (4 << TCR_IPS_SHIFT)
 608 #define TCR_IPS_48BIT   (5 << TCR_IPS_SHIFT)
 609
 610 #define TCR_TG1_SHIFT   30
 611 #define TCR_TG1_16K     (1 << TCR_TG1_SHIFT)
 612 #define TCR_TG1_4K      (2 << TCR_TG1_SHIFT)
 613 #define TCR_TG1_64K     (3 << TCR_TG1_SHIFT)
 614
 615 #define TCR_SH1_SHIFT   28
 616 #define TCR_SH1_IS      (0x3UL << TCR_SH1_SHIFT)
 617 #define TCR_ORGN1_SHIFT 26
 618 #define TCR_ORGN1_WBWA  (0x1UL << TCR_ORGN1_SHIFT)
 619 #define TCR_IRGN1_SHIFT 24
 620 #define TCR_IRGN1_WBWA  (0x1UL << TCR_IRGN1_SHIFT)
 621 #define TCR_SH0_SHIFT   12
 622 #define TCR_SH0_IS      (0x3UL << TCR_SH0_SHIFT)
 623 #define TCR_ORGN0_SHIFT 10
 624 #define TCR_ORGN0_WBWA  (0x1UL << TCR_ORGN0_SHIFT)
 625 #define TCR_IRGN0_SHIFT 8
 626 #define TCR_IRGN0_WBWA  (0x1UL << TCR_IRGN0_SHIFT)
 627
 628 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
 629                                 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
 630
 631 #ifdef SMP
 632 #define TCR_SMP_ATTRS   (TCR_SH0_IS | TCR_SH1_IS)
 633 #else
 634 #define TCR_SMP_ATTRS   0
 635 #endif
 636
 637 #define TCR_T1SZ_SHIFT  16
 638 #define TCR_T0SZ_SHIFT  0
 639 #define TCR_T1SZ(x)     ((x) << TCR_T1SZ_SHIFT)
 640 #define TCR_T0SZ(x)     ((x) << TCR_T0SZ_SHIFT)
 641 #define TCR_TxSZ(x)     (TCR_T1SZ(x) | TCR_T0SZ(x))
 642
 643 /* Saved Program Status Register */
 644 #define DBG_SPSR_SS     (0x1 << 21)
 645
 646 /* Monitor Debug System Control Register */
 647 #define DBG_MDSCR_SS    (0x1 << 0)
 648 #define DBG_MDSCR_KDE   (0x1 << 13)
 649 #define DBG_MDSCR_MDE   (0x1 << 15)
 650
 651 /* Perfomance Monitoring Counters */
 652 #define PMCR_E          (1 << 0) /* Enable all counters */
 653 #define PMCR_P          (1 << 1) /* Reset all counters */
 654 #define PMCR_C          (1 << 2) /* Clock counter reset */
 655 #define PMCR_D          (1 << 3) /* CNTR counts every 64 clk cycles */
 656 #define PMCR_X          (1 << 4) /* Export to ext. monitoring (ETM) */
 657 #define PMCR_DP         (1 << 5) /* Disable CCNT if non-invasive debug*/
 658 #define PMCR_LC         (1 << 6) /* Long cycle count enable */
 659 #define PMCR_IMP_SHIFT  24 /* Implementer code */
 660 #define PMCR_IMP_MASK   (0xff << PMCR_IMP_SHIFT)
 661 #define PMCR_IDCODE_SHIFT       16 /* Identification code */
 662 #define PMCR_IDCODE_MASK        (0xff << PMCR_IDCODE_SHIFT)
 663 #define  PMCR_IDCODE_CORTEX_A57 0x01
 664 #define  PMCR_IDCODE_CORTEX_A72 0x02
 665 #define  PMCR_IDCODE_CORTEX_A53 0x03
 666 #define PMCR_N_SHIFT    11       /* Number of counters implemented */
 667 #define PMCR_N_MASK     (0x1f << PMCR_N_SHIFT)
 668
 669 #endif /* !_MACHINE_ARMREG_H_ */