2 * Copyright (c) 2013, 2014 Andrew Turner
3 * Copyright (c) 2015 The FreeBSD Foundation
6 * This software was developed by Andrew Turner under
7 * sponsorship from the FreeBSD Foundation.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef _MACHINE_ARMREG_H_
34 #define _MACHINE_ARMREG_H_
38 #define READ_SPECIALREG(reg) \
40 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \
43 #define WRITE_SPECIALREG(reg, val) \
44 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val))
46 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
47 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */
48 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */
49 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */
50 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */
51 #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/
54 #define CPACR_FPEN_MASK (0x3 << 20)
55 #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */
56 #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */
57 #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */
58 #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */
59 #define CPACR_TTA (0x1 << 28)
61 /* CTR_EL0 - Cache Type Register */
62 #define CTR_DLINE_SHIFT 16
63 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT)
64 #define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
65 #define CTR_ILINE_SHIFT 0
66 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT)
67 #define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
69 /* DAIF - Interrupt Mask Bits */
70 #define DAIF_D_MASKED (1 << 9)
71 #define DAIF_A_MASKED (1 << 8)
72 #define DAIF_I_MASKED (1 << 7)
73 #define DAIF_F_MASKED (1 << 6)
75 /* DCZID_EL0 - Data Cache Zero ID register */
76 #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */
77 #define DCZID_BS_SHIFT 0
78 #define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT)
79 #define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
82 #define ESR_ELx_ISS_MASK 0x00ffffff
83 #define ISS_INSN_FnV (0x01 << 10)
84 #define ISS_INSN_EA (0x01 << 9)
85 #define ISS_INSN_S1PTW (0x01 << 7)
86 #define ISS_INSN_IFSC_MASK (0x1f << 0)
87 #define ISS_DATA_ISV (0x01 << 24)
88 #define ISS_DATA_SAS_MASK (0x03 << 22)
89 #define ISS_DATA_SSE (0x01 << 21)
90 #define ISS_DATA_SRT_MASK (0x1f << 16)
91 #define ISS_DATA_SF (0x01 << 15)
92 #define ISS_DATA_AR (0x01 << 14)
93 #define ISS_DATA_FnV (0x01 << 10)
94 #define ISS_DATa_EA (0x01 << 9)
95 #define ISS_DATa_CM (0x01 << 8)
96 #define ISS_INSN_S1PTW (0x01 << 7)
97 #define ISS_DATa_WnR (0x01 << 6)
98 #define ISS_DATA_DFSC_MASK (0x3f << 0)
99 #define ISS_DATA_DFSC_ASF_L0 (0x00 << 0)
100 #define ISS_DATA_DFSC_ASF_L1 (0x01 << 0)
101 #define ISS_DATA_DFSC_ASF_L2 (0x02 << 0)
102 #define ISS_DATA_DFSC_ASF_L3 (0x03 << 0)
103 #define ISS_DATA_DFSC_TF_L0 (0x04 << 0)
104 #define ISS_DATA_DFSC_TF_L1 (0x05 << 0)
105 #define ISS_DATA_DFSC_TF_L2 (0x06 << 0)
106 #define ISS_DATA_DFSC_TF_L3 (0x07 << 0)
107 #define ISS_DATA_DFSC_AFF_L1 (0x09 << 0)
108 #define ISS_DATA_DFSC_AFF_L2 (0x0a << 0)
109 #define ISS_DATA_DFSC_AFF_L3 (0x0b << 0)
110 #define ISS_DATA_DFSC_PF_L1 (0x0d << 0)
111 #define ISS_DATA_DFSC_PF_L2 (0x0e << 0)
112 #define ISS_DATA_DFSC_PF_L3 (0x0f << 0)
113 #define ISS_DATA_DFSC_EXT (0x10 << 0)
114 #define ISS_DATA_DFSC_EXT_L0 (0x14 << 0)
115 #define ISS_DATA_DFSC_EXT_L1 (0x15 << 0)
116 #define ISS_DATA_DFSC_EXT_L2 (0x16 << 0)
117 #define ISS_DATA_DFSC_EXT_L3 (0x17 << 0)
118 #define ISS_DATA_DFSC_ECC (0x18 << 0)
119 #define ISS_DATA_DFSC_ECC_L0 (0x1c << 0)
120 #define ISS_DATA_DFSC_ECC_L1 (0x1d << 0)
121 #define ISS_DATA_DFSC_ECC_L2 (0x1e << 0)
122 #define ISS_DATA_DFSC_ECC_L3 (0x1f << 0)
123 #define ISS_DATA_DFSC_ALIGN (0x21 << 0)
124 #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0)
125 #define ESR_ELx_IL (0x01 << 25)
126 #define ESR_ELx_EC_SHIFT 26
127 #define ESR_ELx_EC_MASK (0x3f << 26)
128 #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
129 #define EXCP_UNKNOWN 0x00 /* Unkwn exception */
130 #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */
131 #define EXCP_ILL_STATE 0x0e /* Illegal execution state */
132 #define EXCP_SVC32 0x11 /* SVC trap for AArch32 */
133 #define EXCP_SVC64 0x15 /* SVC trap for AArch64 */
134 #define EXCP_MSR 0x18 /* MSR/MRS trap */
135 #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */
136 #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */
137 #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */
138 #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */
139 #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */
140 #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */
141 #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */
142 #define EXCP_SERROR 0x2f /* SError interrupt */
143 #define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */
144 #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */
145 #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */
146 #define EXCP_BRK 0x3c /* Breakpoint */
149 #define ICC_CTLR_EL1_EOIMODE (1U << 1)
152 #define ICC_IAR1_EL1_SPUR (0x03ff)
154 /* ICC_IGRPEN0_EL1 */
155 #define ICC_IGRPEN0_EL1_EN (1U << 0)
158 #define ICC_PMR_EL1_PRIO_MASK (0xFFUL)
161 #define ICC_SGI1R_EL1_TL_MASK 0xffffUL
162 #define ICC_SGI1R_EL1_AFF1_SHIFT 16
163 #define ICC_SGI1R_EL1_SGIID_SHIFT 24
164 #define ICC_SGI1R_EL1_AFF2_SHIFT 32
165 #define ICC_SGI1R_EL1_AFF3_SHIFT 48
166 #define ICC_SGI1R_EL1_SGIID_MASK 0xfUL
167 #define ICC_SGI1R_EL1_IRM (0x1UL << 40)
170 #define ICC_SRE_EL1_SRE (1U << 0)
173 #define ICC_SRE_EL2_SRE (1U << 0)
174 #define ICC_SRE_EL2_EN (1U << 3)
176 /* ID_AA64DFR0_EL1 */
177 #define ID_AA64DFR0_MASK 0x0000000ff0f0fffful
178 #define ID_AA64DFR0_DEBUG_VER_SHIFT 0
179 #define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT)
180 #define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK)
181 #define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT)
182 #define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT)
183 #define ID_AA64DFR0_DEBUG_VER_8_2 (0x8 << ID_AA64DFR0_DEBUG_VER_SHIFT)
184 #define ID_AA64DFR0_TRACE_VER_SHIFT 4
185 #define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT)
186 #define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK)
187 #define ID_AA64DFR0_TRACE_VER_NONE (0x0 << ID_AA64DFR0_TRACE_VER_SHIFT)
188 #define ID_AA64DFR0_TRACE_VER_IMPL (0x1 << ID_AA64DFR0_TRACE_VER_SHIFT)
189 #define ID_AA64DFR0_PMU_VER_SHIFT 8
190 #define ID_AA64DFR0_PMU_VER_MASK (0xf << ID_AA64DFR0_PMU_VER_SHIFT)
191 #define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK)
192 #define ID_AA64DFR0_PMU_VER_NONE (0x0 << ID_AA64DFR0_PMU_VER_SHIFT)
193 #define ID_AA64DFR0_PMU_VER_3 (0x1 << ID_AA64DFR0_PMU_VER_SHIFT)
194 #define ID_AA64DFR0_PMU_VER_3_1 (0x4 << ID_AA64DFR0_PMU_VER_SHIFT)
195 #define ID_AA64DFR0_PMU_VER_IMPL (0xf << ID_AA64DFR0_PMU_VER_SHIFT)
196 #define ID_AA64DFR0_BRPS_SHIFT 12
197 #define ID_AA64DFR0_BRPS_MASK (0xf << ID_AA64DFR0_BRPS_SHIFT)
198 #define ID_AA64DFR0_BRPS(x) \
199 ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1)
200 #define ID_AA64DFR0_WRPS_SHIFT 20
201 #define ID_AA64DFR0_WRPS_MASK (0xf << ID_AA64DFR0_WRPS_SHIFT)
202 #define ID_AA64DFR0_WRPS(x) \
203 ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1)
204 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
205 #define ID_AA64DFR0_CTX_CMPS_MASK (0xf << ID_AA64DFR0_CTX_CMPS_SHIFT)
206 #define ID_AA64DFR0_CTX_CMPS(x) \
207 ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1)
208 #define ID_AA64DFR0_PMS_VER_SHIFT 32
209 #define ID_AA64DFR0_PMS_VER_MASK (0xful << ID_AA64DFR0_PMS_VER_SHIFT)
210 #define ID_AA64DFR0_PMS_VER(x) ((x) & ID_AA64DFR0_PMS_VER_MASK)
211 #define ID_AA64DFR0_PMS_VER_NONE (0x0ul << ID_AA64DFR0_PMS_VER_SHIFT)
212 #define ID_AA64DFR0_PMS_VER_V1 (0x1ul << ID_AA64DFR0_PMS_VER_SHIFT)
214 /* ID_AA64ISAR0_EL1 */
215 #define ID_AA64ISAR0_MASK 0x0000fffff0fffff0ul
216 #define ID_AA64ISAR0_AES_SHIFT 4
217 #define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT)
218 #define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK)
219 #define ID_AA64ISAR0_AES_NONE (0x0 << ID_AA64ISAR0_AES_SHIFT)
220 #define ID_AA64ISAR0_AES_BASE (0x1 << ID_AA64ISAR0_AES_SHIFT)
221 #define ID_AA64ISAR0_AES_PMULL (0x2 << ID_AA64ISAR0_AES_SHIFT)
222 #define ID_AA64ISAR0_SHA1_SHIFT 8
223 #define ID_AA64ISAR0_SHA1_MASK (0xf << ID_AA64ISAR0_SHA1_SHIFT)
224 #define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK)
225 #define ID_AA64ISAR0_SHA1_NONE (0x0 << ID_AA64ISAR0_SHA1_SHIFT)
226 #define ID_AA64ISAR0_SHA1_BASE (0x1 << ID_AA64ISAR0_SHA1_SHIFT)
227 #define ID_AA64ISAR0_SHA2_SHIFT 12
228 #define ID_AA64ISAR0_SHA2_MASK (0xf << ID_AA64ISAR0_SHA2_SHIFT)
229 #define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK)
230 #define ID_AA64ISAR0_SHA2_NONE (0x0 << ID_AA64ISAR0_SHA2_SHIFT)
231 #define ID_AA64ISAR0_SHA2_BASE (0x1 << ID_AA64ISAR0_SHA2_SHIFT)
232 #define ID_AA64ISAR0_SHA2_512 (0x2 << ID_AA64ISAR0_SHA2_SHIFT)
233 #define ID_AA64ISAR0_CRC32_SHIFT 16
234 #define ID_AA64ISAR0_CRC32_MASK (0xf << ID_AA64ISAR0_CRC32_SHIFT)
235 #define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK)
236 #define ID_AA64ISAR0_CRC32_NONE (0x0 << ID_AA64ISAR0_CRC32_SHIFT)
237 #define ID_AA64ISAR0_CRC32_BASE (0x1 << ID_AA64ISAR0_CRC32_SHIFT)
238 #define ID_AA64ISAR0_ATOMIC_SHIFT 20
239 #define ID_AA64ISAR0_ATOMIC_MASK (0xf << ID_AA64ISAR0_ATOMIC_SHIFT)
240 #define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK)
241 #define ID_AA64ISAR0_ATOMIC_NONE (0x0 << ID_AA64ISAR0_ATOMIC_SHIFT)
242 #define ID_AA64ISAR0_ATOMIC_IMPL (0x2 << ID_AA64ISAR0_ATOMIC_SHIFT)
243 #define ID_AA64ISAR0_RDM_SHIFT 28
244 #define ID_AA64ISAR0_RDM_MASK (0xf << ID_AA64ISAR0_RDM_SHIFT)
245 #define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK)
246 #define ID_AA64ISAR0_RDM_NONE (0x0 << ID_AA64ISAR0_RDM_SHIFT)
247 #define ID_AA64ISAR0_RDM_IMPL (0x1 << ID_AA64ISAR0_RDM_SHIFT)
248 #define ID_AA64ISAR0_SHA3_SHIFT 32
249 #define ID_AA64ISAR0_SHA3_MASK (0xful << ID_AA64ISAR0_SHA3_SHIFT)
250 #define ID_AA64ISAR0_SHA3(x) ((x) & ID_AA64ISAR0_SHA3_MASK)
251 #define ID_AA64ISAR0_SHA3_NONE (0x0ul << ID_AA64ISAR0_SHA3_SHIFT)
252 #define ID_AA64ISAR0_SHA3_IMPL (0x1ul << ID_AA64ISAR0_SHA3_SHIFT)
253 #define ID_AA64ISAR0_SM3_SHIFT 36
254 #define ID_AA64ISAR0_SM3_MASK (0xful << ID_AA64ISAR0_SM3_SHIFT)
255 #define ID_AA64ISAR0_SM3(x) ((x) & ID_AA64ISAR0_SM3_MASK)
256 #define ID_AA64ISAR0_SM3_NONE (0x0ul << ID_AA64ISAR0_SM3_SHIFT)
257 #define ID_AA64ISAR0_SM3_IMPL (0x1ul << ID_AA64ISAR0_SM3_SHIFT)
258 #define ID_AA64ISAR0_SM4_SHIFT 40
259 #define ID_AA64ISAR0_SM4_MASK (0xful << ID_AA64ISAR0_SM4_SHIFT)
260 #define ID_AA64ISAR0_SM4(x) ((x) & ID_AA64ISAR0_SM4_MASK)
261 #define ID_AA64ISAR0_SM4_NONE (0x0ul << ID_AA64ISAR0_SM4_SHIFT)
262 #define ID_AA64ISAR0_SM4_IMPL (0x1ul << ID_AA64ISAR0_SM4_SHIFT)
263 #define ID_AA64ISAR0_DP_SHIFT 44
264 #define ID_AA64ISAR0_DP_MASK (0xful << ID_AA64ISAR0_DP_SHIFT)
265 #define ID_AA64ISAR0_DP(x) ((x) & ID_AA64ISAR0_DP_MASK)
266 #define ID_AA64ISAR0_DP_NONE (0x0ul << ID_AA64ISAR0_DP_SHIFT)
267 #define ID_AA64ISAR0_DP_IMPL (0x1ul << ID_AA64ISAR0_DP_SHIFT)
269 /* ID_AA64ISAR1_EL1 */
270 #define ID_AA64ISAR1_MASK 0xffffffff
271 #define ID_AA64ISAR1_DPB_SHIFT 0
272 #define ID_AA64ISAR1_DPB_MASK (0xf << ID_AA64ISAR1_DPB_SHIFT)
273 #define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK)
274 #define ID_AA64ISAR1_DPB_NONE (0x0 << ID_AA64ISAR1_DPB_SHIFT)
275 #define ID_AA64ISAR1_DPB_IMPL (0x1 << ID_AA64ISAR1_DPB_SHIFT)
276 #define ID_AA64ISAR1_APA_SHIFT 4
277 #define ID_AA64ISAR1_APA_MASK (0xf << ID_AA64ISAR1_APA_SHIFT)
278 #define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK)
279 #define ID_AA64ISAR1_APA_NONE (0x0 << ID_AA64ISAR1_APA_SHIFT)
280 #define ID_AA64ISAR1_APA_IMPL (0x1 << ID_AA64ISAR1_APA_SHIFT)
281 #define ID_AA64ISAR1_API_SHIFT 8
282 #define ID_AA64ISAR1_API_MASK (0xf << ID_AA64ISAR1_API_SHIFT)
283 #define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK)
284 #define ID_AA64ISAR1_API_NONE (0x0 << ID_AA64ISAR1_API_SHIFT)
285 #define ID_AA64ISAR1_API_IMPL (0x1 << ID_AA64ISAR1_API_SHIFT)
286 #define ID_AA64ISAR1_JSCVT_SHIFT 12
287 #define ID_AA64ISAR1_JSCVT_MASK (0xf << ID_AA64ISAR1_JSCVT_SHIFT)
288 #define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK)
289 #define ID_AA64ISAR1_JSCVT_NONE (0x0 << ID_AA64ISAR1_JSCVT_SHIFT)
290 #define ID_AA64ISAR1_JSCVT_IMPL (0x1 << ID_AA64ISAR1_JSCVT_SHIFT)
291 #define ID_AA64ISAR1_FCMA_SHIFT 16
292 #define ID_AA64ISAR1_FCMA_MASK (0xf << ID_AA64ISAR1_FCMA_SHIFT)
293 #define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK)
294 #define ID_AA64ISAR1_FCMA_NONE (0x0 << ID_AA64ISAR1_FCMA_SHIFT)
295 #define ID_AA64ISAR1_FCMA_IMPL (0x1 << ID_AA64ISAR1_FCMA_SHIFT)
296 #define ID_AA64ISAR1_LRCPC_SHIFT 20
297 #define ID_AA64ISAR1_LRCPC_MASK (0xf << ID_AA64ISAR1_LRCPC_SHIFT)
298 #define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK)
299 #define ID_AA64ISAR1_LRCPC_NONE (0x0 << ID_AA64ISAR1_LRCPC_SHIFT)
300 #define ID_AA64ISAR1_LRCPC_IMPL (0x1 << ID_AA64ISAR1_LRCPC_SHIFT)
301 #define ID_AA64ISAR1_GPA_SHIFT 24
302 #define ID_AA64ISAR1_GPA_MASK (0xf << ID_AA64ISAR1_GPA_SHIFT)
303 #define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK)
304 #define ID_AA64ISAR1_GPA_NONE (0x0 << ID_AA64ISAR1_GPA_SHIFT)
305 #define ID_AA64ISAR1_GPA_IMPL (0x1 << ID_AA64ISAR1_GPA_SHIFT)
306 #define ID_AA64ISAR1_GPI_SHIFT 28
307 #define ID_AA64ISAR1_GPI_MASK (0xf << ID_AA64ISAR1_GPI_SHIFT)
308 #define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK)
309 #define ID_AA64ISAR1_GPI_NONE (0x0 << ID_AA64ISAR1_GPI_SHIFT)
310 #define ID_AA64ISAR1_GPI_IMPL (0x1 << ID_AA64ISAR1_GPI_SHIFT)
312 /* ID_AA64MMFR0_EL1 */
313 #define ID_AA64MMFR0_MASK 0xffffffff
314 #define ID_AA64MMFR0_PA_RANGE_SHIFT 0
315 #define ID_AA64MMFR0_PA_RANGE_MASK (0xf << ID_AA64MMFR0_PA_RANGE_SHIFT)
316 #define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK)
317 #define ID_AA64MMFR0_PA_RANGE_4G (0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT)
318 #define ID_AA64MMFR0_PA_RANGE_64G (0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT)
319 #define ID_AA64MMFR0_PA_RANGE_1T (0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT)
320 #define ID_AA64MMFR0_PA_RANGE_4T (0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT)
321 #define ID_AA64MMFR0_PA_RANGE_16T (0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT)
322 #define ID_AA64MMFR0_PA_RANGE_256T (0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT)
323 #define ID_AA64MMFR0_PA_RANGE_4P (0x6 << ID_AA64MMFR0_PA_RANGE_SHIFT)
324 #define ID_AA64MMFR0_ASID_BITS_SHIFT 4
325 #define ID_AA64MMFR0_ASID_BITS_MASK (0xf << ID_AA64MMFR0_ASID_BITS_SHIFT)
326 #define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK)
327 #define ID_AA64MMFR0_ASID_BITS_8 (0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT)
328 #define ID_AA64MMFR0_ASID_BITS_16 (0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT)
329 #define ID_AA64MMFR0_BIGEND_SHIFT 8
330 #define ID_AA64MMFR0_BIGEND_MASK (0xf << ID_AA64MMFR0_BIGEND_SHIFT)
331 #define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK)
332 #define ID_AA64MMFR0_BIGEND_FIXED (0x0 << ID_AA64MMFR0_BIGEND_SHIFT)
333 #define ID_AA64MMFR0_BIGEND_MIXED (0x1 << ID_AA64MMFR0_BIGEND_SHIFT)
334 #define ID_AA64MMFR0_S_NS_MEM_SHIFT 12
335 #define ID_AA64MMFR0_S_NS_MEM_MASK (0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT)
336 #define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK)
337 #define ID_AA64MMFR0_S_NS_MEM_NONE (0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT)
338 #define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT)
339 #define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16
340 #define ID_AA64MMFR0_BIGEND_EL0_MASK (0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
341 #define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK)
342 #define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
343 #define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
344 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
345 #define ID_AA64MMFR0_TGRAN16_MASK (0xf << ID_AA64MMFR0_TGRAN16_SHIFT)
346 #define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK)
347 #define ID_AA64MMFR0_TGRAN16_NONE (0x0 << ID_AA64MMFR0_TGRAN16_SHIFT)
348 #define ID_AA64MMFR0_TGRAN16_IMPL (0x1 << ID_AA64MMFR0_TGRAN16_SHIFT)
349 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
350 #define ID_AA64MMFR0_TGRAN64_MASK (0xf << ID_AA64MMFR0_TGRAN64_SHIFT)
351 #define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK)
352 #define ID_AA64MMFR0_TGRAN64_IMPL (0x0 << ID_AA64MMFR0_TGRAN64_SHIFT)
353 #define ID_AA64MMFR0_TGRAN64_NONE (0xf << ID_AA64MMFR0_TGRAN64_SHIFT)
354 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
355 #define ID_AA64MMFR0_TGRAN4_MASK (0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
356 #define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK)
357 #define ID_AA64MMFR0_TGRAN4_IMPL (0x0 << ID_AA64MMFR0_TGRAN4_SHIFT)
358 #define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
360 /* ID_AA64MMFR1_EL1 */
361 #define ID_AA64MMFR1_MASK 0xffffffff
362 #define ID_AA64MMFR1_HAFDBS_SHIFT 0
363 #define ID_AA64MMFR1_HAFDBS_MASK (0xf << ID_AA64MMFR1_HAFDBS_SHIFT)
364 #define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK)
365 #define ID_AA64MMFR1_HAFDBS_NONE (0x0 << ID_AA64MMFR1_HAFDBS_SHIFT)
366 #define ID_AA64MMFR1_HAFDBS_AF (0x1 << ID_AA64MMFR1_HAFDBS_SHIFT)
367 #define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2 << ID_AA64MMFR1_HAFDBS_SHIFT)
368 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4
369 #define ID_AA64MMFR1_VMIDBITS_MASK (0xf << ID_AA64MMFR1_VMIDBITS_SHIFT)
370 #define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK)
371 #define ID_AA64MMFR1_VMIDBITS_8 (0x0 << ID_AA64MMFR1_VMIDBITS_SHIFT)
372 #define ID_AA64MMFR1_VMIDBITS_16 (0x2 << ID_AA64MMFR1_VMIDBITS_SHIFT)
373 #define ID_AA64MMFR1_VH_SHIFT 8
374 #define ID_AA64MMFR1_VH_MASK (0xf << ID_AA64MMFR1_VH_SHIFT)
375 #define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK)
376 #define ID_AA64MMFR1_VH_NONE (0x0 << ID_AA64MMFR1_VH_SHIFT)
377 #define ID_AA64MMFR1_VH_IMPL (0x1 << ID_AA64MMFR1_VH_SHIFT)
378 #define ID_AA64MMFR1_HPDS_SHIFT 12
379 #define ID_AA64MMFR1_HPDS_MASK (0xf << ID_AA64MMFR1_HPDS_SHIFT)
380 #define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK)
381 #define ID_AA64MMFR1_HPDS_NONE (0x0 << ID_AA64MMFR1_HPDS_SHIFT)
382 #define ID_AA64MMFR1_HPDS_HPD (0x1 << ID_AA64MMFR1_HPDS_SHIFT)
383 #define ID_AA64MMFR1_HPDS_TTPBHA (0x2 << ID_AA64MMFR1_HPDS_SHIFT)
384 #define ID_AA64MMFR1_LO_SHIFT 16
385 #define ID_AA64MMFR1_LO_MASK (0xf << ID_AA64MMFR1_LO_SHIFT)
386 #define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK)
387 #define ID_AA64MMFR1_LO_NONE (0x0 << ID_AA64MMFR1_LO_SHIFT)
388 #define ID_AA64MMFR1_LO_IMPL (0x1 << ID_AA64MMFR1_LO_SHIFT)
389 #define ID_AA64MMFR1_PAN_SHIFT 20
390 #define ID_AA64MMFR1_PAN_MASK (0xf << ID_AA64MMFR1_PAN_SHIFT)
391 #define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK)
392 #define ID_AA64MMFR1_PAN_NONE (0x0 << ID_AA64MMFR1_PAN_SHIFT)
393 #define ID_AA64MMFR1_PAN_IMPL (0x1 << ID_AA64MMFR1_PAN_SHIFT)
394 #define ID_AA64MMFR1_PAN_ATS1E1 (0x2 << ID_AA64MMFR1_PAN_SHIFT)
395 #define ID_AA64MMFR1_SPEC_SEI_SHIFT 24
396 #define ID_AA64MMFR1_SPEC_SEI_MASK (0xf << ID_AA64MMFR1_SPEC_SEI_SHIFT)
397 #define ID_AA64MMFR1_SPEC_SEI(x) ((x) & ID_AA64MMFR1_SPEC_SEI_MASK)
398 #define ID_AA64MMFR1_SPEC_SEI_NONE (0x0 << ID_AA64MMFR1_SPEC_SEI_SHIFT)
399 #define ID_AA64MMFR1_SPEC_SEI_IMPL (0x1 << ID_AA64MMFR1_SPEC_SEI_SHIFT)
400 #define ID_AA64MMFR1_XNX_SHIFT 28
401 #define ID_AA64MMFR1_XNX_MASK (0xf << ID_AA64MMFR1_XNX_SHIFT)
402 #define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK)
403 #define ID_AA64MMFR1_XNX_NONE (0x0 << ID_AA64MMFR1_XNX_SHIFT)
404 #define ID_AA64MMFR1_XNX_IMPL (0x1 << ID_AA64MMFR1_XNX_SHIFT)
406 /* ID_AA64MMFR2_EL1 */
407 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
408 #define ID_AA64MMFR2_MASK 0x0fffffff
409 #define ID_AA64MMFR2_CNP_SHIFT 0
410 #define ID_AA64MMFR2_CNP_MASK (0xf << ID_AA64MMFR2_CNP_SHIFT)
411 #define ID_AA64MMFR2_CNP(x) ((x) & ID_AA64MMFR2_CNP_MASK)
412 #define ID_AA64MMFR2_CNP_NONE (0x0 << ID_AA64MMFR2_CNP_SHIFT)
413 #define ID_AA64MMFR2_CNP_IMPL (0x1 << ID_AA64MMFR2_CNP_SHIFT)
414 #define ID_AA64MMFR2_UAO_SHIFT 4
415 #define ID_AA64MMFR2_UAO_MASK (0xf << ID_AA64MMFR2_UAO_SHIFT)
416 #define ID_AA64MMFR2_UAO(x) ((x) & ID_AA64MMFR2_UAO_MASK)
417 #define ID_AA64MMFR2_UAO_NONE (0x0 << ID_AA64MMFR2_UAO_SHIFT)
418 #define ID_AA64MMFR2_UAO_IMPL (0x1 << ID_AA64MMFR2_UAO_SHIFT)
419 #define ID_AA64MMFR2_LSM_SHIFT 8
420 #define ID_AA64MMFR2_LSM_MASK (0xf << ID_AA64MMFR2_LSM_SHIFT)
421 #define ID_AA64MMFR2_LSM(x) ((x) & ID_AA64MMFR2_LSM_MASK)
422 #define ID_AA64MMFR2_LSM_NONE (0x0 << ID_AA64MMFR2_LSM_SHIFT)
423 #define ID_AA64MMFR2_LSM_IMPL (0x1 << ID_AA64MMFR2_LSM_SHIFT)
424 #define ID_AA64MMFR2_IESB_SHIFT 12
425 #define ID_AA64MMFR2_IESB_MASK (0xf << ID_AA64MMFR2_IESB_SHIFT)
426 #define ID_AA64MMFR2_IESB(x) ((x) & ID_AA64MMFR2_IESB_MASK)
427 #define ID_AA64MMFR2_IESB_NONE (0x0 << ID_AA64MMFR2_IESB_SHIFT)
428 #define ID_AA64MMFR2_IESB_IMPL (0x1 << ID_AA64MMFR2_IESB_SHIFT)
429 #define ID_AA64MMFR2_VA_RANGE_SHIFT 16
430 #define ID_AA64MMFR2_VA_RANGE_MASK (0xf << ID_AA64MMFR2_VA_RANGE_SHIFT)
431 #define ID_AA64MMFR2_VA_RANGE(x) ((x) & ID_AA64MMFR2_VA_RANGE_MASK)
432 #define ID_AA64MMFR2_VA_RANGE_48 (0x0 << ID_AA64MMFR2_VA_RANGE_SHIFT)
433 #define ID_AA64MMFR2_VA_RANGE_52 (0x1 << ID_AA64MMFR2_VA_RANGE_SHIFT)
434 #define ID_AA64MMFR2_CCIDX_SHIFT 20
435 #define ID_AA64MMFR2_CCIDX_MASK (0xf << ID_AA64MMFR2_CCIDX_SHIFT)
436 #define ID_AA64MMFR2_CCIDX(x) ((x) & ID_AA64MMFR2_CCIDX_MASK)
437 #define ID_AA64MMFR2_CCIDX_32 (0x0 << ID_AA64MMFR2_CCIDX_SHIFT)
438 #define ID_AA64MMFR2_CCIDX_64 (0x1 << ID_AA64MMFR2_CCIDX_SHIFT)
439 #define ID_AA64MMFR2_NV_SHIFT 24
440 #define ID_AA64MMFR2_NV_MASK (0xf << ID_AA64MMFR2_NV_SHIFT)
441 #define ID_AA64MMFR2_NV(x) ((x) & ID_AA64MMFR2_NV_MASK)
442 #define ID_AA64MMFR2_NV_NONE (0x0 << ID_AA64MMFR2_NV_SHIFT)
443 #define ID_AA64MMFR2_NV_IMPL (0x1 << ID_AA64MMFR2_NV_SHIFT)
445 /* ID_AA64PFR0_EL1 */
446 #define ID_AA64PFR0_MASK 0x0000000ffffffffful
447 #define ID_AA64PFR0_EL0_SHIFT 0
448 #define ID_AA64PFR0_EL0_MASK (0xf << ID_AA64PFR0_EL0_SHIFT)
449 #define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK)
450 #define ID_AA64PFR0_EL0_64 (1 << ID_AA64PFR0_EL0_SHIFT)
451 #define ID_AA64PFR0_EL0_64_32 (2 << ID_AA64PFR0_EL0_SHIFT)
452 #define ID_AA64PFR0_EL1_SHIFT 4
453 #define ID_AA64PFR0_EL1_MASK (0xf << ID_AA64PFR0_EL1_SHIFT)
454 #define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK)
455 #define ID_AA64PFR0_EL1_64 (1 << ID_AA64PFR0_EL1_SHIFT)
456 #define ID_AA64PFR0_EL1_64_32 (2 << ID_AA64PFR0_EL1_SHIFT)
457 #define ID_AA64PFR0_EL2_SHIFT 8
458 #define ID_AA64PFR0_EL2_MASK (0xf << ID_AA64PFR0_EL2_SHIFT)
459 #define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK)
460 #define ID_AA64PFR0_EL2_NONE (0 << ID_AA64PFR0_EL2_SHIFT)
461 #define ID_AA64PFR0_EL2_64 (1 << ID_AA64PFR0_EL2_SHIFT)
462 #define ID_AA64PFR0_EL2_64_32 (2 << ID_AA64PFR0_EL2_SHIFT)
463 #define ID_AA64PFR0_EL3_SHIFT 12
464 #define ID_AA64PFR0_EL3_MASK (0xf << ID_AA64PFR0_EL3_SHIFT)
465 #define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK)
466 #define ID_AA64PFR0_EL3_NONE (0 << ID_AA64PFR0_EL3_SHIFT)
467 #define ID_AA64PFR0_EL3_64 (1 << ID_AA64PFR0_EL3_SHIFT)
468 #define ID_AA64PFR0_EL3_64_32 (2 << ID_AA64PFR0_EL3_SHIFT)
469 #define ID_AA64PFR0_FP_SHIFT 16
470 #define ID_AA64PFR0_FP_MASK (0xf << ID_AA64PFR0_FP_SHIFT)
471 #define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK)
472 #define ID_AA64PFR0_FP_IMPL (0x0 << ID_AA64PFR0_FP_SHIFT)
473 #define ID_AA64PFR0_FP_HP (0x1 << ID_AA64PFR0_FP_SHIFT)
474 #define ID_AA64PFR0_FP_NONE (0xf << ID_AA64PFR0_FP_SHIFT)
475 #define ID_AA64PFR0_ADV_SIMD_SHIFT 20
476 #define ID_AA64PFR0_ADV_SIMD_MASK (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT)
477 #define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK)
478 #define ID_AA64PFR0_ADV_SIMD_IMPL (0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT)
479 #define ID_AA64PFR0_ADV_SIMD_HP (0x1 << ID_AA64PFR0_ADV_SIMD_SHIFT)
480 #define ID_AA64PFR0_ADV_SIMD_NONE (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT)
481 #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */
482 #define ID_AA64PFR0_GIC_SHIFT 24
483 #define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT)
484 #define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK)
485 #define ID_AA64PFR0_GIC_CPUIF_NONE (0x0 << ID_AA64PFR0_GIC_SHIFT)
486 #define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT)
487 #define ID_AA64PFR0_RAS_SHIFT 28
488 #define ID_AA64PFR0_RAS_MASK (0xf << ID_AA64PFR0_RAS_SHIFT)
489 #define ID_AA64PFR0_RAS(x) ((x) & ID_AA64PFR0_RAS_MASK)
490 #define ID_AA64PFR0_RAS_NONE (0x0 << ID_AA64PFR0_RAS_SHIFT)
491 #define ID_AA64PFR0_RAS_V1 (0x1 << ID_AA64PFR0_RAS_SHIFT)
492 #define ID_AA64PFR0_SVE_SHIFT 32
493 #define ID_AA64PFR0_SVE_MASK (0xful << ID_AA64PFR0_SVE_SHIFT)
494 #define ID_AA64PFR0_SVE(x) ((x) & ID_AA64PFR0_SVE_MASK)
495 #define ID_AA64PFR0_SVE_NONE (0x0ul << ID_AA64PFR0_SVE_SHIFT)
496 #define ID_AA64PFR0_SVE_IMPL (0x1ul << ID_AA64PFR0_SVE_SHIFT)
498 /* MAIR_EL1 - Memory Attribute Indirection Register */
499 #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))
500 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
501 #define MAIR_DEVICE_nGnRnE 0x00
502 #define MAIR_NORMAL_NC 0x44
503 #define MAIR_NORMAL_WT 0xbb
504 #define MAIR_NORMAL_WB 0xff
506 /* PAR_EL1 - Physical Address Register */
507 #define PAR_F_SHIFT 0
508 #define PAR_F (0x1 << PAR_F_SHIFT)
509 #define PAR_SUCCESS(x) (((x) & PAR_F) == 0)
510 /* When PAR_F == 0 (success) */
511 #define PAR_SH_SHIFT 7
512 #define PAR_SH_MASK (0x3 << PAR_SH_SHIFT)
513 #define PAR_NS_SHIFT 9
514 #define PAR_NS_MASK (0x3 << PAR_NS_SHIFT)
515 #define PAR_PA_SHIFT 12
516 #define PAR_PA_MASK 0x0000fffffffff000
517 #define PAR_ATTR_SHIFT 56
518 #define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT)
519 /* When PAR_F == 1 (aborted) */
520 #define PAR_FST_SHIFT 1
521 #define PAR_FST_MASK (0x3f << PAR_FST_SHIFT)
522 #define PAR_PTW_SHIFT 8
523 #define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT)
524 #define PAR_S_SHIFT 9
525 #define PAR_S_MASK (0x1 << PAR_S_SHIFT)
527 /* SCTLR_EL1 - System Control Register */
528 #define SCTLR_RES0 0xc8222440 /* Reserved ARMv8.0, write 0 */
529 #define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */
531 #define SCTLR_M 0x00000001
532 #define SCTLR_A 0x00000002
533 #define SCTLR_C 0x00000004
534 #define SCTLR_SA 0x00000008
535 #define SCTLR_SA0 0x00000010
536 #define SCTLR_CP15BEN 0x00000020
537 /* Bit 6 is reserved */
538 #define SCTLR_ITD 0x00000080
539 #define SCTLR_SED 0x00000100
540 #define SCTLR_UMA 0x00000200
541 /* Bit 10 is reserved */
542 /* Bit 11 is reserved */
543 #define SCTLR_I 0x00001000
544 #define SCTLR_EnDB 0x00002000 /* ARMv8.3 */
545 #define SCTLR_DZE 0x00004000
546 #define SCTLR_UCT 0x00008000
547 #define SCTLR_nTWI 0x00010000
548 /* Bit 17 is reserved */
549 #define SCTLR_nTWE 0x00040000
550 #define SCTLR_WXN 0x00080000
551 /* Bit 20 is reserved */
552 #define SCTLR_IESB 0x00200000 /* ARMv8.2 */
553 /* Bit 22 is reserved */
554 #define SCTLR_SPAN 0x00800000 /* ARMv8.1 */
555 #define SCTLR_EOE 0x01000000
556 #define SCTLR_EE 0x02000000
557 #define SCTLR_UCI 0x04000000
558 #define SCTLR_EnDA 0x08000000 /* ARMv8.3 */
559 #define SCTLR_nTLSMD 0x10000000 /* ARMv8.2 */
560 #define SCTLR_LSMAOE 0x20000000 /* ARMv8.2 */
561 #define SCTLR_EnIB 0x40000000 /* ARMv8.3 */
562 #define SCTLR_EnIA 0x80000000 /* ARMv8.3 */
566 * When the exception is taken in AArch64:
567 * M[3:2] is the exception level
569 * M[0] is the SP select:
573 #define PSR_M_EL0t 0x00000000
574 #define PSR_M_EL1t 0x00000004
575 #define PSR_M_EL1h 0x00000005
576 #define PSR_M_EL2t 0x00000008
577 #define PSR_M_EL2h 0x00000009
578 #define PSR_M_64 0x00000000
579 #define PSR_M_32 0x00000010
580 #define PSR_M_MASK 0x0000000f
582 #define PSR_T 0x00000020
584 #define PSR_AARCH32 0x00000010
585 #define PSR_F 0x00000040
586 #define PSR_I 0x00000080
587 #define PSR_A 0x00000100
588 #define PSR_D 0x00000200
589 #define PSR_IL 0x00100000
590 #define PSR_SS 0x00200000
591 #define PSR_V 0x10000000
592 #define PSR_C 0x20000000
593 #define PSR_Z 0x40000000
594 #define PSR_N 0x80000000
595 #define PSR_FLAGS 0xf0000000
597 /* TCR_EL1 - Translation Control Register */
598 #define TCR_ASID_16 (1 << 36)
600 #define TCR_IPS_SHIFT 32
601 #define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT)
602 #define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT)
603 #define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT)
604 #define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT)
605 #define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT)
606 #define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT)
608 #define TCR_TG1_SHIFT 30
609 #define TCR_TG1_16K (1 << TCR_TG1_SHIFT)
610 #define TCR_TG1_4K (2 << TCR_TG1_SHIFT)
611 #define TCR_TG1_64K (3 << TCR_TG1_SHIFT)
613 #define TCR_SH1_SHIFT 28
614 #define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT)
615 #define TCR_ORGN1_SHIFT 26
616 #define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT)
617 #define TCR_IRGN1_SHIFT 24
618 #define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT)
619 #define TCR_SH0_SHIFT 12
620 #define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT)
621 #define TCR_ORGN0_SHIFT 10
622 #define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT)
623 #define TCR_IRGN0_SHIFT 8
624 #define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT)
626 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
627 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
630 #define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS)
632 #define TCR_SMP_ATTRS 0
635 #define TCR_T1SZ_SHIFT 16
636 #define TCR_T0SZ_SHIFT 0
637 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT)
638 #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT)
639 #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x))
641 /* Saved Program Status Register */
642 #define DBG_SPSR_SS (0x1 << 21)
644 /* Monitor Debug System Control Register */
645 #define DBG_MDSCR_SS (0x1 << 0)
646 #define DBG_MDSCR_KDE (0x1 << 13)
647 #define DBG_MDSCR_MDE (0x1 << 15)
649 /* Perfomance Monitoring Counters */
650 #define PMCR_E (1 << 0) /* Enable all counters */
651 #define PMCR_P (1 << 1) /* Reset all counters */
652 #define PMCR_C (1 << 2) /* Clock counter reset */
653 #define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */
654 #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */
655 #define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
656 #define PMCR_LC (1 << 6) /* Long cycle count enable */
657 #define PMCR_IMP_SHIFT 24 /* Implementer code */
658 #define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT)
659 #define PMCR_IDCODE_SHIFT 16 /* Identification code */
660 #define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT)
661 #define PMCR_IDCODE_CORTEX_A57 0x01
662 #define PMCR_IDCODE_CORTEX_A72 0x02
663 #define PMCR_IDCODE_CORTEX_A53 0x03
664 #define PMCR_N_SHIFT 11 /* Number of counters implemented */
665 #define PMCR_N_MASK (0x1f << PMCR_N_SHIFT)
667 #endif /* !_MACHINE_ARMREG_H_ */