sys/arm64/include/armreg.h

   1 /*-
   2  * Copyright (c) 2013, 2014 Andrew Turner
   3  * Copyright (c) 2015 The FreeBSD Foundation
   4  * All rights reserved.
   5  *
   6  * This software was developed by Andrew Turner under
   7  * sponsorship from the FreeBSD Foundation.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * $FreeBSD$
  31  */
  32
  33 #ifndef _MACHINE_ARMREG_H_
  34 #define _MACHINE_ARMREG_H_
  35
  36 #define INSN_SIZE               4
  37
  38 #define MRS_MASK                        0xfff00000
  39 #define MRS_VALUE                       0xd5300000
  40 #define MRS_SPECIAL(insn)               ((insn) & 0x000fffe0)
  41 #define MRS_REGISTER(insn)              ((insn) & 0x0000001f)
  42 #define  MRS_Op0_SHIFT                  19
  43 #define  MRS_Op0_MASK                   0x00080000
  44 #define  MRS_Op1_SHIFT                  16
  45 #define  MRS_Op1_MASK                   0x00070000
  46 #define  MRS_CRn_SHIFT                  12
  47 #define  MRS_CRn_MASK                   0x0000f000
  48 #define  MRS_CRm_SHIFT                  8
  49 #define  MRS_CRm_MASK                   0x00000f00
  50 #define  MRS_Op2_SHIFT                  5
  51 #define  MRS_Op2_MASK                   0x000000e0
  52 #define  MRS_Rt_SHIFT                   0
  53 #define  MRS_Rt_MASK                    0x0000001f
  54 #define MRS_REG(op0, op1, crn, crm, op2)                                \
  55     (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) |              \
  56      ((crn) << MRS_CRn_SHIFT) | ((crm) << MRS_CRm_SHIFT) |              \
  57      ((op2) << MRS_Op2_SHIFT))
  58
  59 #define READ_SPECIALREG(reg)                                            \
  60 ({      uint64_t _val;                                                  \
  61         __asm __volatile("mrs   %0, " __STRING(reg) : "=&r" (_val));    \
  62         _val;                                                           \
  63 })
  64 #define WRITE_SPECIALREG(reg, _val)                                     \
  65         __asm __volatile("msr   " __STRING(reg) ", %0" : : "r"((uint64_t)_val))
  66
  67 #define UL(x)   UINT64_C(x)
  68
  69 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
  70 #define CNTHCTL_EVNTI_MASK      (0xf << 4) /* Bit to trigger event stream */
  71 #define CNTHCTL_EVNTDIR         (1 << 3) /* Control transition trigger bit */
  72 #define CNTHCTL_EVNTEN          (1 << 2) /* Enable event stream */
  73 #define CNTHCTL_EL1PCEN         (1 << 1) /* Allow EL0/1 physical timer access */
  74 #define CNTHCTL_EL1PCTEN        (1 << 0) /*Allow EL0/1 physical counter access*/
  75
  76 /* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */
  77 #define CNTP_CTL_ENABLE         (1 << 0)
  78 #define CNTP_CTL_IMASK          (1 << 1)
  79 #define CNTP_CTL_ISTATUS        (1 << 2)
  80
  81 /* CPACR_EL1 */
  82 #define CPACR_FPEN_MASK         (0x3 << 20)
  83 #define  CPACR_FPEN_TRAP_ALL1   (0x0 << 20) /* Traps from EL0 and EL1 */
  84 #define  CPACR_FPEN_TRAP_EL0    (0x1 << 20) /* Traps from EL0 */
  85 #define  CPACR_FPEN_TRAP_ALL2   (0x2 << 20) /* Traps from EL0 and EL1 */
  86 #define  CPACR_FPEN_TRAP_NONE   (0x3 << 20) /* No traps */
  87 #define CPACR_TTA               (0x1 << 28)
  88
  89 /* CTR_EL0 - Cache Type Register */
  90 #define CTR_RES1                (1 << 31)
  91 #define CTR_TminLine_SHIFT      32
  92 #define CTR_TminLine_MASK       (UL(0x3f) << CTR_TminLine_SHIFT)
  93 #define CTR_TminLine_VAL(reg)   ((reg) & CTR_TminLine_MASK)
  94 #define CTR_DIC_SHIFT           29
  95 #define CTR_DIC_MASK            (0x1 << CTR_DIC_SHIFT)
  96 #define CTR_DIC_VAL(reg)        ((reg) & CTR_DIC_MASK)
  97 #define CTR_IDC_SHIFT           28
  98 #define CTR_IDC_MASK            (0x1 << CTR_IDC_SHIFT)
  99 #define CTR_IDC_VAL(reg)        ((reg) & CTR_IDC_MASK)
 100 #define CTR_CWG_SHIFT           24
 101 #define CTR_CWG_MASK            (0xf << CTR_CWG_SHIFT)
 102 #define CTR_CWG_VAL(reg)        ((reg) & CTR_CWG_MASK)
 103 #define CTR_CWG_SIZE(reg)       (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT))
 104 #define CTR_ERG_SHIFT           20
 105 #define CTR_ERG_MASK            (0xf << CTR_ERG_SHIFT)
 106 #define CTR_ERG_VAL(reg)        ((reg) & CTR_ERG_MASK)
 107 #define CTR_ERG_SIZE(reg)       (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT))
 108 #define CTR_DLINE_SHIFT         16
 109 #define CTR_DLINE_MASK          (0xf << CTR_DLINE_SHIFT)
 110 #define CTR_DLINE_VAL(reg)      ((reg) & CTR_DLINE_MASK)
 111 #define CTR_DLINE_SIZE(reg)     (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT))
 112 #define CTR_L1IP_SHIFT          14
 113 #define CTR_L1IP_MASK           (0x3 << CTR_L1IP_SHIFT)
 114 #define CTR_L1IP_VAL(reg)       ((reg) & CTR_L1IP_MASK)
 115 #define  CTR_L1IP_VPIPT         (0 << CTR_L1IP_SHIFT)
 116 #define  CTR_L1IP_AIVIVT        (1 << CTR_L1IP_SHIFT)
 117 #define  CTR_L1IP_VIPT          (2 << CTR_L1IP_SHIFT)
 118 #define  CTR_L1IP_PIPT          (3 << CTR_L1IP_SHIFT)
 119 #define CTR_ILINE_SHIFT         0
 120 #define CTR_ILINE_MASK          (0xf << CTR_ILINE_SHIFT)
 121 #define CTR_ILINE_VAL(reg)      ((reg) & CTR_ILINE_MASK)
 122 #define CTR_ILINE_SIZE(reg)     (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT))
 123
 124 /* DAIF - Interrupt Mask Bits */
 125 #define DAIF_D_MASKED           (1 << 9)
 126 #define DAIF_A_MASKED           (1 << 8)
 127 #define DAIF_I_MASKED           (1 << 7)
 128 #define DAIF_F_MASKED           (1 << 6)
 129
 130 /* DCZID_EL0 - Data Cache Zero ID register */
 131 #define DCZID_DZP               (1 << 4) /* DC ZVA prohibited if non-0 */
 132 #define DCZID_BS_SHIFT          0
 133 #define DCZID_BS_MASK           (0xf << DCZID_BS_SHIFT)
 134 #define DCZID_BS_SIZE(reg)      (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
 135
 136 /* ESR_ELx */
 137 #define ESR_ELx_ISS_MASK        0x01ffffff
 138 #define  ISS_INSN_FnV           (0x01 << 10)
 139 #define  ISS_INSN_EA            (0x01 << 9)
 140 #define  ISS_INSN_S1PTW         (0x01 << 7)
 141 #define  ISS_INSN_IFSC_MASK     (0x1f << 0)
 142
 143 #define  ISS_MSR_DIR_SHIFT      0
 144 #define  ISS_MSR_DIR            (0x01 << ISS_MSR_DIR_SHIFT)
 145 #define  ISS_MSR_Rt_SHIFT       5
 146 #define  ISS_MSR_Rt_MASK        (0x1f << ISS_MSR_Rt_SHIFT)
 147 #define  ISS_MSR_Rt(x)          (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT)
 148 #define  ISS_MSR_CRm_SHIFT      1
 149 #define  ISS_MSR_CRm_MASK       (0xf << ISS_MSR_CRm_SHIFT)
 150 #define  ISS_MSR_CRm(x)         (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT)
 151 #define  ISS_MSR_CRn_SHIFT      10
 152 #define  ISS_MSR_CRn_MASK       (0xf << ISS_MSR_CRn_SHIFT)
 153 #define  ISS_MSR_CRn(x)         (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT)
 154 #define  ISS_MSR_OP1_SHIFT      14
 155 #define  ISS_MSR_OP1_MASK       (0x7 << ISS_MSR_OP1_SHIFT)
 156 #define  ISS_MSR_OP1(x)         (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT)
 157 #define  ISS_MSR_OP2_SHIFT      17
 158 #define  ISS_MSR_OP2_MASK       (0x7 << ISS_MSR_OP2_SHIFT)
 159 #define  ISS_MSR_OP2(x)         (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT)
 160 #define  ISS_MSR_OP0_SHIFT      20
 161 #define  ISS_MSR_OP0_MASK       (0x3 << ISS_MSR_OP0_SHIFT)
 162 #define  ISS_MSR_OP0(x)         (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT)
 163 #define  ISS_MSR_REG_MASK       \
 164     (ISS_MSR_OP0_MASK | ISS_MSR_OP2_MASK | ISS_MSR_OP1_MASK |   \
 165      ISS_MSR_CRn_MASK | ISS_MSR_CRm_MASK)
 166
 167
 168 #define  ISS_DATA_ISV_SHIFT     24
 169 #define  ISS_DATA_ISV           (0x01 << ISS_DATA_ISV_SHIFT)
 170 #define  ISS_DATA_SAS_SHIFT     22
 171 #define  ISS_DATA_SAS_MASK      (0x03 << ISS_DATA_SAS_SHIFT)
 172 #define  ISS_DATA_SSE_SHIFT     21
 173 #define  ISS_DATA_SSE           (0x01 << ISS_DATA_SSE_SHIFT)
 174 #define  ISS_DATA_SRT_SHIFT     16
 175 #define  ISS_DATA_SRT_MASK      (0x1f << ISS_DATA_SRT_SHIFT)
 176 #define  ISS_DATA_SF            (0x01 << 15)
 177 #define  ISS_DATA_AR            (0x01 << 14)
 178 #define  ISS_DATA_FnV           (0x01 << 10)
 179 #define  ISS_DATA_EA            (0x01 << 9)
 180 #define  ISS_DATA_CM            (0x01 << 8)
 181 #define  ISS_DATA_S1PTW         (0x01 << 7)
 182 #define  ISS_DATA_WnR_SHIFT     6
 183 #define  ISS_DATA_WnR           (0x01 << ISS_DATA_WnR_SHIFT)
 184 #define  ISS_DATA_DFSC_MASK     (0x3f << 0)
 185 #define  ISS_DATA_DFSC_ASF_L0   (0x00 << 0)
 186 #define  ISS_DATA_DFSC_ASF_L1   (0x01 << 0)
 187 #define  ISS_DATA_DFSC_ASF_L2   (0x02 << 0)
 188 #define  ISS_DATA_DFSC_ASF_L3   (0x03 << 0)
 189 #define  ISS_DATA_DFSC_TF_L0    (0x04 << 0)
 190 #define  ISS_DATA_DFSC_TF_L1    (0x05 << 0)
 191 #define  ISS_DATA_DFSC_TF_L2    (0x06 << 0)
 192 #define  ISS_DATA_DFSC_TF_L3    (0x07 << 0)
 193 #define  ISS_DATA_DFSC_AFF_L1   (0x09 << 0)
 194 #define  ISS_DATA_DFSC_AFF_L2   (0x0a << 0)
 195 #define  ISS_DATA_DFSC_AFF_L3   (0x0b << 0)
 196 #define  ISS_DATA_DFSC_PF_L1    (0x0d << 0)
 197 #define  ISS_DATA_DFSC_PF_L2    (0x0e << 0)
 198 #define  ISS_DATA_DFSC_PF_L3    (0x0f << 0)
 199 #define  ISS_DATA_DFSC_EXT      (0x10 << 0)
 200 #define  ISS_DATA_DFSC_EXT_L0   (0x14 << 0)
 201 #define  ISS_DATA_DFSC_EXT_L1   (0x15 << 0)
 202 #define  ISS_DATA_DFSC_EXT_L2   (0x16 << 0)
 203 #define  ISS_DATA_DFSC_EXT_L3   (0x17 << 0)
 204 #define  ISS_DATA_DFSC_ECC      (0x18 << 0)
 205 #define  ISS_DATA_DFSC_ECC_L0   (0x1c << 0)
 206 #define  ISS_DATA_DFSC_ECC_L1   (0x1d << 0)
 207 #define  ISS_DATA_DFSC_ECC_L2   (0x1e << 0)
 208 #define  ISS_DATA_DFSC_ECC_L3   (0x1f << 0)
 209 #define  ISS_DATA_DFSC_ALIGN    (0x21 << 0)
 210 #define  ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0)
 211 #define ESR_ELx_IL              (0x01 << 25)
 212 #define ESR_ELx_EC_SHIFT        26
 213 #define ESR_ELx_EC_MASK         (0x3f << 26)
 214 #define ESR_ELx_EXCEPTION(esr)  (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
 215 #define  EXCP_UNKNOWN           0x00    /* Unkwn exception */
 216 #define  EXCP_TRAP_WFI_WFE      0x01    /* Trapped WFI or WFE */
 217 #define  EXCP_FP_SIMD           0x07    /* VFP/SIMD trap */
 218 #define  EXCP_ILL_STATE         0x0e    /* Illegal execution state */
 219 #define  EXCP_SVC32             0x11    /* SVC trap for AArch32 */
 220 #define  EXCP_SVC64             0x15    /* SVC trap for AArch64 */
 221 #define  EXCP_HVC               0x16    /* HVC trap */
 222 #define  EXCP_MSR               0x18    /* MSR/MRS trap */
 223 #define  EXCP_INSN_ABORT_L      0x20    /* Instruction abort, from lower EL */
 224 #define  EXCP_INSN_ABORT        0x21    /* Instruction abort, from same EL */
 225 #define  EXCP_PC_ALIGN          0x22    /* PC alignment fault */
 226 #define  EXCP_DATA_ABORT_L      0x24    /* Data abort, from lower EL */
 227 #define  EXCP_DATA_ABORT        0x25    /* Data abort, from same EL */
 228 #define  EXCP_SP_ALIGN          0x26    /* SP slignment fault */
 229 #define  EXCP_TRAP_FP           0x2c    /* Trapped FP exception */
 230 #define  EXCP_SERROR            0x2f    /* SError interrupt */
 231 #define  EXCP_BRKPT_EL0         0x30    /* Hardware breakpoint, from same EL */
 232 #define  EXCP_SOFTSTP_EL0       0x32    /* Software Step, from lower EL */
 233 #define  EXCP_SOFTSTP_EL1       0x33    /* Software Step, from same EL */
 234 #define  EXCP_WATCHPT_EL1       0x35    /* Watchpoint, from same EL */
 235 #define  EXCP_BRK               0x3c    /* Breakpoint */
 236
 237 /* ICC_CTLR_EL1 */
 238 #define ICC_CTLR_EL1_EOIMODE    (1U << 1)
 239
 240 /* ICC_IAR1_EL1 */
 241 #define ICC_IAR1_EL1_SPUR       (0x03ff)
 242
 243 /* ICC_IGRPEN0_EL1 */
 244 #define ICC_IGRPEN0_EL1_EN      (1U << 0)
 245
 246 /* ICC_PMR_EL1 */
 247 #define ICC_PMR_EL1_PRIO_MASK   (0xFFUL)
 248
 249 /* ICC_SGI1R_EL1 */
 250 #define ICC_SGI1R_EL1_TL_MASK           0xffffUL
 251 #define ICC_SGI1R_EL1_AFF1_SHIFT        16
 252 #define ICC_SGI1R_EL1_SGIID_SHIFT       24
 253 #define ICC_SGI1R_EL1_AFF2_SHIFT        32
 254 #define ICC_SGI1R_EL1_AFF3_SHIFT        48
 255 #define ICC_SGI1R_EL1_SGIID_MASK        0xfUL
 256 #define ICC_SGI1R_EL1_IRM               (0x1UL << 40)
 257
 258 /* ICC_SRE_EL1 */
 259 #define ICC_SRE_EL1_SRE         (1U << 0)
 260
 261 /* ID_AA64DFR0_EL1 */
 262 #define ID_AA64DFR0_EL1                 MRS_REG(3, 0, 0, 5, 0)
 263 #define ID_AA64DFR0_DebugVer_SHIFT      0
 264 #define ID_AA64DFR0_DebugVer_MASK       (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)
 265 #define ID_AA64DFR0_DebugVer_VAL(x)     ((x) & ID_AA64DFR0_DebugVer_MASK)
 266 #define  ID_AA64DFR0_DebugVer_8         (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT)
 267 #define  ID_AA64DFR0_DebugVer_8_VHE     (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT)
 268 #define  ID_AA64DFR0_DebugVer_8_2       (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT)
 269 #define ID_AA64DFR0_TraceVer_SHIFT      4
 270 #define ID_AA64DFR0_TraceVer_MASK       (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT)
 271 #define ID_AA64DFR0_TraceVer_VAL(x)     ((x) & ID_AA64DFR0_TraceVer_MASK)
 272 #define  ID_AA64DFR0_TraceVer_NONE      (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT)
 273 #define  ID_AA64DFR0_TraceVer_IMPL      (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT)
 274 #define ID_AA64DFR0_PMUVer_SHIFT        8
 275 #define ID_AA64DFR0_PMUVer_MASK         (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
 276 #define ID_AA64DFR0_PMUVer_VAL(x)       ((x) & ID_AA64DFR0_PMUVer_MASK)
 277 #define  ID_AA64DFR0_PMUVer_NONE        (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT)
 278 #define  ID_AA64DFR0_PMUVer_3           (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT)
 279 #define  ID_AA64DFR0_PMUVer_3_1         (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT)
 280 #define  ID_AA64DFR0_PMUVer_IMPL        (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
 281 #define ID_AA64DFR0_BRPs_SHIFT          12
 282 #define ID_AA64DFR0_BRPs_MASK           (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT)
 283 #define ID_AA64DFR0_BRPs_VAL(x) \
 284     ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1)
 285 #define ID_AA64DFR0_WRPs_SHIFT          20
 286 #define ID_AA64DFR0_WRPs_MASK           (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT)
 287 #define ID_AA64DFR0_WRPs_VAL(x) \
 288     ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1)
 289 #define ID_AA64DFR0_CTX_CMPs_SHIFT      28
 290 #define ID_AA64DFR0_CTX_CMPs_MASK       (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT)
 291 #define ID_AA64DFR0_CTX_CMPs_VAL(x)     \
 292     ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1)
 293 #define ID_AA64DFR0_PMSVer_SHIFT        32
 294 #define ID_AA64DFR0_PMSVer_MASK         (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT)
 295 #define ID_AA64DFR0_PMSVer_VAL(x)       ((x) & ID_AA64DFR0_PMSVer_MASK)
 296 #define  ID_AA64DFR0_PMSVer_NONE        (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT)
 297 #define  ID_AA64DFR0_PMSVer_V1          (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT)
 298
 299 /* ID_AA64ISAR0_EL1 */
 300 #define ID_AA64ISAR0_EL1                MRS_REG(3, 0, 0, 6, 0)
 301 #define ID_AA64ISAR0_AES_SHIFT          4
 302 #define ID_AA64ISAR0_AES_MASK           (UL(0xf) << ID_AA64ISAR0_AES_SHIFT)
 303 #define ID_AA64ISAR0_AES_VAL(x)         ((x) & ID_AA64ISAR0_AES_MASK)
 304 #define  ID_AA64ISAR0_AES_NONE          (UL(0x0) << ID_AA64ISAR0_AES_SHIFT)
 305 #define  ID_AA64ISAR0_AES_BASE          (UL(0x1) << ID_AA64ISAR0_AES_SHIFT)
 306 #define  ID_AA64ISAR0_AES_PMULL         (UL(0x2) << ID_AA64ISAR0_AES_SHIFT)
 307 #define ID_AA64ISAR0_SHA1_SHIFT         8
 308 #define ID_AA64ISAR0_SHA1_MASK          (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT)
 309 #define ID_AA64ISAR0_SHA1_VAL(x)        ((x) & ID_AA64ISAR0_SHA1_MASK)
 310 #define  ID_AA64ISAR0_SHA1_NONE         (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT)
 311 #define  ID_AA64ISAR0_SHA1_BASE         (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT)
 312 #define ID_AA64ISAR0_SHA2_SHIFT         12
 313 #define ID_AA64ISAR0_SHA2_MASK          (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT)
 314 #define ID_AA64ISAR0_SHA2_VAL(x)        ((x) & ID_AA64ISAR0_SHA2_MASK)
 315 #define  ID_AA64ISAR0_SHA2_NONE         (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT)
 316 #define  ID_AA64ISAR0_SHA2_BASE         (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT)
 317 #define  ID_AA64ISAR0_SHA2_512          (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT)
 318 #define ID_AA64ISAR0_CRC32_SHIFT        16
 319 #define ID_AA64ISAR0_CRC32_MASK         (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT)
 320 #define ID_AA64ISAR0_CRC32_VAL(x)       ((x) & ID_AA64ISAR0_CRC32_MASK)
 321 #define  ID_AA64ISAR0_CRC32_NONE        (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT)
 322 #define  ID_AA64ISAR0_CRC32_BASE        (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT)
 323 #define ID_AA64ISAR0_Atomic_SHIFT       20
 324 #define ID_AA64ISAR0_Atomic_MASK        (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT)
 325 #define ID_AA64ISAR0_Atomic_VAL(x)      ((x) & ID_AA64ISAR0_Atomic_MASK)
 326 #define  ID_AA64ISAR0_Atomic_NONE       (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT)
 327 #define  ID_AA64ISAR0_Atomic_IMPL       (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT)
 328 #define ID_AA64ISAR0_RDM_SHIFT          28
 329 #define ID_AA64ISAR0_RDM_MASK           (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT)
 330 #define ID_AA64ISAR0_RDM_VAL(x)         ((x) & ID_AA64ISAR0_RDM_MASK)
 331 #define  ID_AA64ISAR0_RDM_NONE          (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT)
 332 #define  ID_AA64ISAR0_RDM_IMPL          (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT)
 333 #define ID_AA64ISAR0_SHA3_SHIFT         32
 334 #define ID_AA64ISAR0_SHA3_MASK          (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT)
 335 #define ID_AA64ISAR0_SHA3_VAL(x)        ((x) & ID_AA64ISAR0_SHA3_MASK)
 336 #define  ID_AA64ISAR0_SHA3_NONE         (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT)
 337 #define  ID_AA64ISAR0_SHA3_IMPL         (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT)
 338 #define ID_AA64ISAR0_SM3_SHIFT          36
 339 #define ID_AA64ISAR0_SM3_MASK           (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT)
 340 #define ID_AA64ISAR0_SM3_VAL(x)         ((x) & ID_AA64ISAR0_SM3_MASK)
 341 #define  ID_AA64ISAR0_SM3_NONE          (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT)
 342 #define  ID_AA64ISAR0_SM3_IMPL          (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT)
 343 #define ID_AA64ISAR0_SM4_SHIFT          40
 344 #define ID_AA64ISAR0_SM4_MASK           (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT)
 345 #define ID_AA64ISAR0_SM4_VAL(x)         ((x) & ID_AA64ISAR0_SM4_MASK)
 346 #define  ID_AA64ISAR0_SM4_NONE          (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT)
 347 #define  ID_AA64ISAR0_SM4_IMPL          (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT)
 348 #define ID_AA64ISAR0_DP_SHIFT           44
 349 #define ID_AA64ISAR0_DP_MASK            (UL(0xf) << ID_AA64ISAR0_DP_SHIFT)
 350 #define ID_AA64ISAR0_DP_VAL(x)          ((x) & ID_AA64ISAR0_DP_MASK)
 351 #define  ID_AA64ISAR0_DP_NONE           (UL(0x0) << ID_AA64ISAR0_DP_SHIFT)
 352 #define  ID_AA64ISAR0_DP_IMPL           (UL(0x1) << ID_AA64ISAR0_DP_SHIFT)
 353
 354 /* ID_AA64ISAR1_EL1 */
 355 #define ID_AA64ISAR1_EL1                MRS_REG(3, 0, 0, 6, 1)
 356 #define ID_AA64ISAR1_DPB_SHIFT          0
 357 #define ID_AA64ISAR1_DPB_MASK           (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
 358 #define ID_AA64ISAR1_DPB_VAL(x)         ((x) & ID_AA64ISAR1_DPB_MASK)
 359 #define  ID_AA64ISAR1_DPB_NONE          (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT)
 360 #define  ID_AA64ISAR1_DPB_IMPL          (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT)
 361 #define ID_AA64ISAR1_APA_SHIFT          4
 362 #define ID_AA64ISAR1_APA_MASK           (UL(0xf) << ID_AA64ISAR1_APA_SHIFT)
 363 #define ID_AA64ISAR1_APA_VAL(x)         ((x) & ID_AA64ISAR1_APA_MASK)
 364 #define  ID_AA64ISAR1_APA_NONE          (UL(0x0) << ID_AA64ISAR1_APA_SHIFT)
 365 #define  ID_AA64ISAR1_APA_IMPL          (UL(0x1) << ID_AA64ISAR1_APA_SHIFT)
 366 #define ID_AA64ISAR1_API_SHIFT          8
 367 #define ID_AA64ISAR1_API_MASK           (UL(0xf) << ID_AA64ISAR1_API_SHIFT)
 368 #define ID_AA64ISAR1_API_VAL(x)         ((x) & ID_AA64ISAR1_API_MASK)
 369 #define  ID_AA64ISAR1_API_NONE          (UL(0x0) << ID_AA64ISAR1_API_SHIFT)
 370 #define  ID_AA64ISAR1_API_IMPL          (UL(0x1) << ID_AA64ISAR1_API_SHIFT)
 371 #define ID_AA64ISAR1_JSCVT_SHIFT        12
 372 #define ID_AA64ISAR1_JSCVT_MASK         (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT)
 373 #define ID_AA64ISAR1_JSCVT_VAL(x)       ((x) & ID_AA64ISAR1_JSCVT_MASK)
 374 #define  ID_AA64ISAR1_JSCVT_NONE        (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT)
 375 #define  ID_AA64ISAR1_JSCVT_IMPL        (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT)
 376 #define ID_AA64ISAR1_FCMA_SHIFT         16
 377 #define ID_AA64ISAR1_FCMA_MASK          (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT)
 378 #define ID_AA64ISAR1_FCMA_VAL(x)        ((x) & ID_AA64ISAR1_FCMA_MASK)
 379 #define  ID_AA64ISAR1_FCMA_NONE         (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT)
 380 #define  ID_AA64ISAR1_FCMA_IMPL         (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT)
 381 #define ID_AA64ISAR1_LRCPC_SHIFT        20
 382 #define ID_AA64ISAR1_LRCPC_MASK         (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT)
 383 #define ID_AA64ISAR1_LRCPC_VAL(x)       ((x) & ID_AA64ISAR1_LRCPC_MASK)
 384 #define  ID_AA64ISAR1_LRCPC_NONE        (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT)
 385 #define  ID_AA64ISAR1_LRCPC_IMPL        (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT)
 386 #define ID_AA64ISAR1_GPA_SHIFT          24
 387 #define ID_AA64ISAR1_GPA_MASK           (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT)
 388 #define ID_AA64ISAR1_GPA_VAL(x)         ((x) & ID_AA64ISAR1_GPA_MASK)
 389 #define  ID_AA64ISAR1_GPA_NONE          (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT)
 390 #define  ID_AA64ISAR1_GPA_IMPL          (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT)
 391 #define ID_AA64ISAR1_GPI_SHIFT          28
 392 #define ID_AA64ISAR1_GPI_MASK           (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT)
 393 #define ID_AA64ISAR1_GPI_VAL(x)         ((x) & ID_AA64ISAR1_GPI_MASK)
 394 #define  ID_AA64ISAR1_GPI_NONE          (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT)
 395 #define  ID_AA64ISAR1_GPI_IMPL          (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT)
 396
 397 /* ID_AA64MMFR0_EL1 */
 398 #define ID_AA64MMFR0_EL1                MRS_REG(3, 0, 0, 7, 0)
 399 #define ID_AA64MMFR0_PARange_SHIFT      0
 400 #define ID_AA64MMFR0_PARange_MASK       (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
 401 #define ID_AA64MMFR0_PARange_VAL(x)     ((x) & ID_AA64MMFR0_PARange_MASK)
 402 #define  ID_AA64MMFR0_PARange_4G        (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT)
 403 #define  ID_AA64MMFR0_PARange_64G       (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT)
 404 #define  ID_AA64MMFR0_PARange_1T        (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT)
 405 #define  ID_AA64MMFR0_PARange_4T        (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT)
 406 #define  ID_AA64MMFR0_PARange_16T       (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT)
 407 #define  ID_AA64MMFR0_PARange_256T      (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT)
 408 #define  ID_AA64MMFR0_PARange_4P        (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT)
 409 #define ID_AA64MMFR0_ASIDBits_SHIFT     4
 410 #define ID_AA64MMFR0_ASIDBits_MASK      (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT)
 411 #define ID_AA64MMFR0_ASIDBits_VAL(x)    ((x) & ID_AA64MMFR0_ASIDBits_MASK)
 412 #define  ID_AA64MMFR0_ASIDBits_8        (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT)
 413 #define  ID_AA64MMFR0_ASIDBits_16       (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT)
 414 #define ID_AA64MMFR0_BigEnd_SHIFT       8
 415 #define ID_AA64MMFR0_BigEnd_MASK        (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT)
 416 #define ID_AA64MMFR0_BigEnd_VAL(x)      ((x) & ID_AA64MMFR0_BigEnd_MASK)
 417 #define  ID_AA64MMFR0_BigEnd_FIXED      (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT)
 418 #define  ID_AA64MMFR0_BigEnd_MIXED      (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT)
 419 #define ID_AA64MMFR0_SNSMem_SHIFT       12
 420 #define ID_AA64MMFR0_SNSMem_MASK        (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT)
 421 #define ID_AA64MMFR0_SNSMem_VAL(x)      ((x) & ID_AA64MMFR0_SNSMem_MASK)
 422 #define  ID_AA64MMFR0_SNSMem_NONE       (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT)
 423 #define  ID_AA64MMFR0_SNSMem_DISTINCT   (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT)
 424 #define ID_AA64MMFR0_BigEndEL0_SHIFT    16
 425 #define ID_AA64MMFR0_BigEndEL0_MASK     (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT)
 426 #define ID_AA64MMFR0_BigEndEL0_VAL(x)   ((x) & ID_AA64MMFR0_BigEndEL0_MASK)
 427 #define  ID_AA64MMFR0_BigEndEL0_FIXED   (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT)
 428 #define  ID_AA64MMFR0_BigEndEL0_MIXED   (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT)
 429 #define ID_AA64MMFR0_TGran16_SHIFT      20
 430 #define ID_AA64MMFR0_TGran16_MASK       (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT)
 431 #define ID_AA64MMFR0_TGran16_VAL(x)     ((x) & ID_AA64MMFR0_TGran16_MASK)
 432 #define  ID_AA64MMFR0_TGran16_NONE      (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT)
 433 #define  ID_AA64MMFR0_TGran16_IMPL      (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT)
 434 #define ID_AA64MMFR0_TGran64_SHIFT      24
 435 #define ID_AA64MMFR0_TGran64_MASK       (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
 436 #define ID_AA64MMFR0_TGran64_VAL(x)     ((x) & ID_AA64MMFR0_TGran64_MASK)
 437 #define  ID_AA64MMFR0_TGran64_IMPL      (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT)
 438 #define  ID_AA64MMFR0_TGran64_NONE      (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
 439 #define ID_AA64MMFR0_TGran4_SHIFT       28
 440 #define ID_AA64MMFR0_TGran4_MASK        (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
 441 #define ID_AA64MMFR0_TGran4_VAL(x)      ((x) & ID_AA64MMFR0_TGran4_MASK)
 442 #define  ID_AA64MMFR0_TGran4_IMPL       (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT)
 443 #define  ID_AA64MMFR0_TGran4_NONE       (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
 444
 445 /* ID_AA64MMFR1_EL1 */
 446 #define ID_AA64MMFR1_EL1                MRS_REG(3, 0, 0, 7, 1)
 447 #define ID_AA64MMFR1_HAFDBS_SHIFT       0
 448 #define ID_AA64MMFR1_HAFDBS_MASK        (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
 449 #define ID_AA64MMFR1_HAFDBS_VAL(x)      ((x) & ID_AA64MMFR1_HAFDBS_MASK)
 450 #define  ID_AA64MMFR1_HAFDBS_NONE       (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT)
 451 #define  ID_AA64MMFR1_HAFDBS_AF         (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT)
 452 #define  ID_AA64MMFR1_HAFDBS_AF_DBS     (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT)
 453 #define ID_AA64MMFR1_VMIDBits_SHIFT     4
 454 #define ID_AA64MMFR1_VMIDBits_MASK      (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT)
 455 #define ID_AA64MMFR1_VMIDBits_VAL(x)    ((x) & ID_AA64MMFR1_VMIDBits_MASK)
 456 #define  ID_AA64MMFR1_VMIDBits_8        (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT)
 457 #define  ID_AA64MMFR1_VMIDBits_16       (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT)
 458 #define ID_AA64MMFR1_VH_SHIFT           8
 459 #define ID_AA64MMFR1_VH_MASK            (UL(0xf) << ID_AA64MMFR1_VH_SHIFT)
 460 #define ID_AA64MMFR1_VH_VAL(x)          ((x) & ID_AA64MMFR1_VH_MASK)
 461 #define  ID_AA64MMFR1_VH_NONE           (UL(0x0) << ID_AA64MMFR1_VH_SHIFT)
 462 #define  ID_AA64MMFR1_VH_IMPL           (UL(0x1) << ID_AA64MMFR1_VH_SHIFT)
 463 #define ID_AA64MMFR1_HPDS_SHIFT         12
 464 #define ID_AA64MMFR1_HPDS_MASK          (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT)
 465 #define ID_AA64MMFR1_HPDS_VAL(x)        ((x) & ID_AA64MMFR1_HPDS_MASK)
 466 #define  ID_AA64MMFR1_HPDS_NONE         (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT)
 467 #define  ID_AA64MMFR1_HPDS_HPD          (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT)
 468 #define  ID_AA64MMFR1_HPDS_TTPBHA       (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT)
 469 #define ID_AA64MMFR1_LO_SHIFT           16
 470 #define ID_AA64MMFR1_LO_MASK            (UL(0xf) << ID_AA64MMFR1_LO_SHIFT)
 471 #define ID_AA64MMFR1_LO_VAL(x)          ((x) & ID_AA64MMFR1_LO_MASK)
 472 #define  ID_AA64MMFR1_LO_NONE           (UL(0x0) << ID_AA64MMFR1_LO_SHIFT)
 473 #define  ID_AA64MMFR1_LO_IMPL           (UL(0x1) << ID_AA64MMFR1_LO_SHIFT)
 474 #define ID_AA64MMFR1_PAN_SHIFT          20
 475 #define ID_AA64MMFR1_PAN_MASK           (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT)
 476 #define ID_AA64MMFR1_PAN_VAL(x)         ((x) & ID_AA64MMFR1_PAN_MASK)
 477 #define  ID_AA64MMFR1_PAN_NONE          (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT)
 478 #define  ID_AA64MMFR1_PAN_IMPL          (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT)
 479 #define  ID_AA64MMFR1_PAN_ATS1E1        (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT)
 480 #define ID_AA64MMFR1_SpecSEI_SHIFT      24
 481 #define ID_AA64MMFR1_SpecSEI_MASK       (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT)
 482 #define ID_AA64MMFR1_SpecSEI_VAL(x)     ((x) & ID_AA64MMFR1_SpecSEI_MASK)
 483 #define  ID_AA64MMFR1_SpecSEI_NONE      (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT)
 484 #define  ID_AA64MMFR1_SpecSEI_IMPL      (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT)
 485 #define ID_AA64MMFR1_XNX_SHIFT          28
 486 #define ID_AA64MMFR1_XNX_MASK           (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT)
 487 #define ID_AA64MMFR1_XNX_VAL(x)         ((x) & ID_AA64MMFR1_XNX_MASK)
 488 #define  ID_AA64MMFR1_XNX_NONE          (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT)
 489 #define  ID_AA64MMFR1_XNX_IMPL          (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT)
 490
 491 /* ID_AA64MMFR2_EL1 */
 492 #define ID_AA64MMFR2_EL1                MRS_REG(3, 0, 0, 7, 2)
 493 #define ID_AA64MMFR2_CnP_SHIFT          0
 494 #define ID_AA64MMFR2_CnP_MASK           (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT)
 495 #define ID_AA64MMFR2_CnP_VAL(x)         ((x) & ID_AA64MMFR2_CnP_MASK)
 496 #define  ID_AA64MMFR2_CnP_NONE          (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT)
 497 #define  ID_AA64MMFR2_CnP_IMPL          (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT)
 498 #define ID_AA64MMFR2_UAO_SHIFT          4
 499 #define ID_AA64MMFR2_UAO_MASK           (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT)
 500 #define ID_AA64MMFR2_UAO_VAL(x)         ((x) & ID_AA64MMFR2_UAO_MASK)
 501 #define  ID_AA64MMFR2_UAO_NONE          (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT)
 502 #define  ID_AA64MMFR2_UAO_IMPL          (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT)
 503 #define ID_AA64MMFR2_LSM_SHIFT          8
 504 #define ID_AA64MMFR2_LSM_MASK           (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT)
 505 #define ID_AA64MMFR2_LSM_VAL(x)         ((x) & ID_AA64MMFR2_LSM_MASK)
 506 #define  ID_AA64MMFR2_LSM_NONE          (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT)
 507 #define  ID_AA64MMFR2_LSM_IMPL          (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT)
 508 #define ID_AA64MMFR2_IESB_SHIFT         12
 509 #define ID_AA64MMFR2_IESB_MASK          (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT)
 510 #define ID_AA64MMFR2_IESB_VAL(x)        ((x) & ID_AA64MMFR2_IESB_MASK)
 511 #define  ID_AA64MMFR2_IESB_NONE         (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT)
 512 #define  ID_AA64MMFR2_IESB_IMPL         (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT)
 513 #define ID_AA64MMFR2_VARange_SHIFT      16
 514 #define ID_AA64MMFR2_VARange_MASK       (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT)
 515 #define ID_AA64MMFR2_VARange_VAL(x)     ((x) & ID_AA64MMFR2_VARange_MASK)
 516 #define  ID_AA64MMFR2_VARange_48        (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT)
 517 #define  ID_AA64MMFR2_VARange_52        (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT)
 518 #define ID_AA64MMFR2_CCIDX_SHIFT        20
 519 #define ID_AA64MMFR2_CCIDX_MASK         (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT)
 520 #define ID_AA64MMFR2_CCIDX_VAL(x)       ((x) & ID_AA64MMFR2_CCIDX_MASK)
 521 #define  ID_AA64MMFR2_CCIDX_32          (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT)
 522 #define  ID_AA64MMFR2_CCIDX_64          (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT)
 523 #define ID_AA64MMFR2_NV_SHIFT           24
 524 #define ID_AA64MMFR2_NV_MASK            (UL(0xf) << ID_AA64MMFR2_NV_SHIFT)
 525 #define ID_AA64MMFR2_NV_VAL(x)          ((x) & ID_AA64MMFR2_NV_MASK)
 526 #define  ID_AA64MMFR2_NV_NONE           (UL(0x0) << ID_AA64MMFR2_NV_SHIFT)
 527 #define  ID_AA64MMFR2_NV_IMPL           (UL(0x1) << ID_AA64MMFR2_NV_SHIFT)
 528
 529 /* ID_AA64PFR0_EL1 */
 530 #define ID_AA64PFR0_EL1                 MRS_REG(3, 0, 0, 4, 0)
 531 #define ID_AA64PFR0_EL0_SHIFT           0
 532 #define ID_AA64PFR0_EL0_MASK            (UL(0xf) << ID_AA64PFR0_EL0_SHIFT)
 533 #define ID_AA64PFR0_EL0_VAL(x)          ((x) & ID_AA64PFR0_EL0_MASK)
 534 #define  ID_AA64PFR0_EL0_64             (UL(0x1) << ID_AA64PFR0_EL0_SHIFT)
 535 #define  ID_AA64PFR0_EL0_64_32          (UL(0x2) << ID_AA64PFR0_EL0_SHIFT)
 536 #define ID_AA64PFR0_EL1_SHIFT           4
 537 #define ID_AA64PFR0_EL1_MASK            (UL(0xf) << ID_AA64PFR0_EL1_SHIFT)
 538 #define ID_AA64PFR0_EL1_VAL(x)          ((x) & ID_AA64PFR0_EL1_MASK)
 539 #define  ID_AA64PFR0_EL1_64             (UL(0x1) << ID_AA64PFR0_EL1_SHIFT)
 540 #define  ID_AA64PFR0_EL1_64_32          (UL(0x2) << ID_AA64PFR0_EL1_SHIFT)
 541 #define ID_AA64PFR0_EL2_SHIFT           8
 542 #define ID_AA64PFR0_EL2_MASK            (UL(0xf) << ID_AA64PFR0_EL2_SHIFT)
 543 #define ID_AA64PFR0_EL2_VAL(x)          ((x) & ID_AA64PFR0_EL2_MASK)
 544 #define  ID_AA64PFR0_EL2_NONE           (UL(0x0) << ID_AA64PFR0_EL2_SHIFT)
 545 #define  ID_AA64PFR0_EL2_64             (UL(0x1) << ID_AA64PFR0_EL2_SHIFT)
 546 #define  ID_AA64PFR0_EL2_64_32          (UL(0x2) << ID_AA64PFR0_EL2_SHIFT)
 547 #define ID_AA64PFR0_EL3_SHIFT           12
 548 #define ID_AA64PFR0_EL3_MASK            (UL(0xf) << ID_AA64PFR0_EL3_SHIFT)
 549 #define ID_AA64PFR0_EL3_VAL(x)          ((x) & ID_AA64PFR0_EL3_MASK)
 550 #define  ID_AA64PFR0_EL3_NONE           (UL(0x0) << ID_AA64PFR0_EL3_SHIFT)
 551 #define  ID_AA64PFR0_EL3_64             (UL(0x1) << ID_AA64PFR0_EL3_SHIFT)
 552 #define  ID_AA64PFR0_EL3_64_32          (UL(0x2) << ID_AA64PFR0_EL3_SHIFT)
 553 #define ID_AA64PFR0_FP_SHIFT            16
 554 #define ID_AA64PFR0_FP_MASK             (UL(0xf) << ID_AA64PFR0_FP_SHIFT)
 555 #define ID_AA64PFR0_FP_VAL(x)           ((x) & ID_AA64PFR0_FP_MASK)
 556 #define  ID_AA64PFR0_FP_IMPL            (UL(0x0) << ID_AA64PFR0_FP_SHIFT)
 557 #define  ID_AA64PFR0_FP_HP              (UL(0x1) << ID_AA64PFR0_FP_SHIFT)
 558 #define  ID_AA64PFR0_FP_NONE            (UL(0xf) << ID_AA64PFR0_FP_SHIFT)
 559 #define ID_AA64PFR0_AdvSIMD_SHIFT       20
 560 #define ID_AA64PFR0_AdvSIMD_MASK        (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
 561 #define ID_AA64PFR0_AdvSIMD_VAL(x)      ((x) & ID_AA64PFR0_AdvSIMD_MASK)
 562 #define  ID_AA64PFR0_AdvSIMD_IMPL       (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT)
 563 #define  ID_AA64PFR0_AdvSIMD_HP         (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT)
 564 #define  ID_AA64PFR0_AdvSIMD_NONE       (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
 565 #define ID_AA64PFR0_GIC_BITS            0x4 /* Number of bits in GIC field */
 566 #define ID_AA64PFR0_GIC_SHIFT           24
 567 #define ID_AA64PFR0_GIC_MASK            (UL(0xf) << ID_AA64PFR0_GIC_SHIFT)
 568 #define ID_AA64PFR0_GIC_VAL(x)          ((x) & ID_AA64PFR0_GIC_MASK)
 569 #define  ID_AA64PFR0_GIC_CPUIF_NONE     (UL(0x0) << ID_AA64PFR0_GIC_SHIFT)
 570 #define  ID_AA64PFR0_GIC_CPUIF_EN       (UL(0x1) << ID_AA64PFR0_GIC_SHIFT)
 571 #define ID_AA64PFR0_RAS_SHIFT           28
 572 #define ID_AA64PFR0_RAS_MASK            (UL(0xf) << ID_AA64PFR0_RAS_SHIFT)
 573 #define ID_AA64PFR0_RAS_VAL(x)          ((x) & ID_AA64PFR0_RAS_MASK)
 574 #define  ID_AA64PFR0_RAS_NONE           (UL(0x0) << ID_AA64PFR0_RAS_SHIFT)
 575 #define  ID_AA64PFR0_RAS_V1             (UL(0x1) << ID_AA64PFR0_RAS_SHIFT)
 576 #define ID_AA64PFR0_SVE_SHIFT           32
 577 #define ID_AA64PFR0_SVE_MASK            (UL(0xf) << ID_AA64PFR0_SVE_SHIFT)
 578 #define ID_AA64PFR0_SVE_VAL(x)          ((x) & ID_AA64PFR0_SVE_MASK)
 579 #define  ID_AA64PFR0_SVE_NONE           (UL(0x0) << ID_AA64PFR0_SVE_SHIFT)
 580 #define  ID_AA64PFR0_SVE_IMPL           (UL(0x1) << ID_AA64PFR0_SVE_SHIFT)
 581 #define ID_AA64PFR0_SEL2_SHIFT          36
 582 #define ID_AA64PFR0_SEL2_MASK           (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT)
 583 #define ID_AA64PFR0_SEL2_VAL(x)         ((x) & ID_AA64PFR0_SEL2_MASK)
 584 #define  ID_AA64PFR0_SEL2_NONE          (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT)
 585 #define  ID_AA64PFR0_SEL2_IMPL          (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT)
 586 #define ID_AA64PFR0_MPAM_SHIFT          40
 587 #define ID_AA64PFR0_MPAM_MASK           (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT)
 588 #define ID_AA64PFR0_MPAM_VAL(x)         ((x) & ID_AA64PFR0_MPAM_MASK)
 589 #define  ID_AA64PFR0_MPAM_NONE          (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT)
 590 #define  ID_AA64PFR0_MPAM_IMPL          (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT)
 591 #define ID_AA64PFR0_AMU_SHIFT           44
 592 #define ID_AA64PFR0_AMU_MASK            (UL(0xf) << ID_AA64PFR0_AMU_SHIFT)
 593 #define ID_AA64PFR0_AMU_VAL(x)          ((x) & ID_AA64PFR0_AMU_MASK)
 594 #define  ID_AA64PFR0_AMU_NONE           (UL(0x0) << ID_AA64PFR0_AMU_SHIFT)
 595 #define  ID_AA64PFR0_AMU_V1             (UL(0x1) << ID_AA64PFR0_AMU_SHIFT)
 596 #define ID_AA64PFR0_DIT_SHIFT           48
 597 #define ID_AA64PFR0_DIT_MASK            (UL(0xf) << ID_AA64PFR0_DIT_SHIFT)
 598 #define ID_AA64PFR0_DIT_VAL(x)          ((x) & ID_AA64PFR0_DIT_MASK)
 599 #define  ID_AA64PFR0_DIT_NONE           (UL(0x0) << ID_AA64PFR0_DIT_SHIFT)
 600 #define  ID_AA64PFR0_DIT_PSTATE         (UL(0x1) << ID_AA64PFR0_DIT_SHIFT)
 601 #define ID_AA64PFR0_CSV2_SHIFT          56
 602 #define ID_AA64PFR0_CSV2_MASK           (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT)
 603 #define ID_AA64PFR0_CSV2_VAL(x)         ((x) & ID_AA64PFR0_CSV2_MASK)
 604 #define  ID_AA64PFR0_CSV2_NONE          (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT)
 605 #define  ID_AA64PFR0_CSV2_ISOLATED      (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT)
 606 #define  ID_AA64PFR0_CSV2_SCXTNUM       (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT)
 607 #define ID_AA64PFR0_CSV3_SHIFT          60
 608 #define ID_AA64PFR0_CSV3_MASK           (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT)
 609 #define ID_AA64PFR0_CSV3_VAL(x)         ((x) & ID_AA64PFR0_CSV3_MASK)
 610 #define  ID_AA64PFR0_CSV3_NONE          (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT)
 611 #define  ID_AA64PFR0_CSV3_ISOLATED      (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT)
 612
 613 /* ID_AA64PFR1_EL1 */
 614 #define ID_AA64PFR1_EL1                 MRS_REG(3, 0, 0, 4, 1)
 615 #define ID_AA64PFR1_BT_SHIFT            0
 616 #define ID_AA64PFR1_BT_MASK             (UL(0xf) << ID_AA64PFR1_BT_SHIFT)
 617 #define ID_AA64PFR1_BT_VAL(x)           ((x) & ID_AA64PFR1_BT_MASK)
 618 #define  ID_AA64PFR1_BT_NONE            (UL(0x0) << ID_AA64PFR1_BT_SHIFT)
 619 #define  ID_AA64PFR1_BT_IMPL            (UL(0x1) << ID_AA64PFR1_BT_SHIFT)
 620 #define ID_AA64PFR1_SSBS_SHIFT          4
 621 #define ID_AA64PFR1_SSBS_MASK           (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT)
 622 #define ID_AA64PFR1_SSBS_VAL(x)         ((x) & ID_AA64PFR1_SSBS_MASK)
 623 #define  ID_AA64PFR1_SSBS_NONE          (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT)
 624 #define  ID_AA64PFR1_SSBS_PSTATE        (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT)
 625 #define  ID_AA64PFR1_SSBS_PSTATE_MSR    (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT)
 626 #define ID_AA64PFR1_MTE_SHIFT           8
 627 #define ID_AA64PFR1_MTE_MASK            (UL(0xf) << ID_AA64PFR1_MTE_SHIFT)
 628 #define ID_AA64PFR1_MTE_VAL(x)          ((x) & ID_AA64PFR1_MTE_MASK)
 629 #define  ID_AA64PFR1_MTE_NONE           (UL(0x0) << ID_AA64PFR1_MTE_SHIFT)
 630 #define  ID_AA64PFR1_MTE_IMPL_EL0       (UL(0x1) << ID_AA64PFR1_MTE_SHIFT)
 631 #define  ID_AA64PFR1_MTE_IMPL           (UL(0x2) << ID_AA64PFR1_MTE_SHIFT)
 632 #define ID_AA64PFR1_RAS_frac_SHIFT      12
 633 #define ID_AA64PFR1_RAS_frac_MASK       (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT)
 634 #define ID_AA64PFR1_RAS_frac_VAL(x)     ((x) & ID_AA64PFR1_RAS_frac_MASK)
 635 #define  ID_AA64PFR1_RAS_frac_V1        (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT)
 636 #define  ID_AA64PFR1_RAS_frac_V2        (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT)
 637
 638 /* MAIR_EL1 - Memory Attribute Indirection Register */
 639 #define MAIR_ATTR_MASK(idx)     (0xff << ((n)* 8))
 640 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
 641 #define  MAIR_DEVICE_nGnRnE     0x00
 642 #define  MAIR_NORMAL_NC         0x44
 643 #define  MAIR_NORMAL_WT         0xbb
 644 #define  MAIR_NORMAL_WB         0xff
 645
 646 /* PAR_EL1 - Physical Address Register */
 647 #define PAR_F_SHIFT             0
 648 #define PAR_F                   (0x1 << PAR_F_SHIFT)
 649 #define PAR_SUCCESS(x)          (((x) & PAR_F) == 0)
 650 /* When PAR_F == 0 (success) */
 651 #define PAR_SH_SHIFT            7
 652 #define PAR_SH_MASK             (0x3 << PAR_SH_SHIFT)
 653 #define PAR_NS_SHIFT            9
 654 #define PAR_NS_MASK             (0x3 << PAR_NS_SHIFT)
 655 #define PAR_PA_SHIFT            12
 656 #define PAR_PA_MASK             0x0000fffffffff000
 657 #define PAR_ATTR_SHIFT          56
 658 #define PAR_ATTR_MASK           (0xff << PAR_ATTR_SHIFT)
 659 /* When PAR_F == 1 (aborted) */
 660 #define PAR_FST_SHIFT           1
 661 #define PAR_FST_MASK            (0x3f << PAR_FST_SHIFT)
 662 #define PAR_PTW_SHIFT           8
 663 #define PAR_PTW_MASK            (0x1 << PAR_PTW_SHIFT)
 664 #define PAR_S_SHIFT             9
 665 #define PAR_S_MASK              (0x1 << PAR_S_SHIFT)
 666
 667 /* SCTLR_EL1 - System Control Register */
 668 #define SCTLR_RES0      0xc8222440      /* Reserved ARMv8.0, write 0 */
 669 #define SCTLR_RES1      0x30d00800      /* Reserved ARMv8.0, write 1 */
 670
 671 #define SCTLR_M         0x00000001
 672 #define SCTLR_A         0x00000002
 673 #define SCTLR_C         0x00000004
 674 #define SCTLR_SA        0x00000008
 675 #define SCTLR_SA0       0x00000010
 676 #define SCTLR_CP15BEN   0x00000020
 677 /* Bit 6 is reserved */
 678 #define SCTLR_ITD       0x00000080
 679 #define SCTLR_SED       0x00000100
 680 #define SCTLR_UMA       0x00000200
 681 /* Bit 10 is reserved */
 682 /* Bit 11 is reserved */
 683 #define SCTLR_I         0x00001000
 684 #define SCTLR_EnDB      0x00002000 /* ARMv8.3 */
 685 #define SCTLR_DZE       0x00004000
 686 #define SCTLR_UCT       0x00008000
 687 #define SCTLR_nTWI      0x00010000
 688 /* Bit 17 is reserved */
 689 #define SCTLR_nTWE      0x00040000
 690 #define SCTLR_WXN       0x00080000
 691 /* Bit 20 is reserved */
 692 #define SCTLR_IESB      0x00200000 /* ARMv8.2 */
 693 /* Bit 22 is reserved */
 694 #define SCTLR_SPAN      0x00800000 /* ARMv8.1 */
 695 #define SCTLR_EOE       0x01000000
 696 #define SCTLR_EE        0x02000000
 697 #define SCTLR_UCI       0x04000000
 698 #define SCTLR_EnDA      0x08000000 /* ARMv8.3 */
 699 #define SCTLR_nTLSMD    0x10000000 /* ARMv8.2 */
 700 #define SCTLR_LSMAOE    0x20000000 /* ARMv8.2 */
 701 #define SCTLR_EnIB      0x40000000 /* ARMv8.3 */
 702 #define SCTLR_EnIA      0x80000000 /* ARMv8.3 */
 703
 704 /* SPSR_EL1 */
 705 /*
 706  * When the exception is taken in AArch64:
 707  * M[3:2] is the exception level
 708  * M[1]   is unused
 709  * M[0]   is the SP select:
 710  *         0: always SP0
 711  *         1: current ELs SP
 712  */
 713 #define PSR_M_EL0t      0x00000000
 714 #define PSR_M_EL1t      0x00000004
 715 #define PSR_M_EL1h      0x00000005
 716 #define PSR_M_EL2t      0x00000008
 717 #define PSR_M_EL2h      0x00000009
 718 #define PSR_M_64        0x00000000
 719 #define PSR_M_32        0x00000010
 720 #define PSR_M_MASK      0x0000000f
 721
 722 #define PSR_T           0x00000020
 723
 724 #define PSR_AARCH32     0x00000010
 725 #define PSR_F           0x00000040
 726 #define PSR_I           0x00000080
 727 #define PSR_A           0x00000100
 728 #define PSR_D           0x00000200
 729 #define PSR_DAIF        (PSR_D | PSR_A | PSR_I | PSR_F)
 730 #define PSR_IL          0x00100000
 731 #define PSR_SS          0x00200000
 732 #define PSR_V           0x10000000
 733 #define PSR_C           0x20000000
 734 #define PSR_Z           0x40000000
 735 #define PSR_N           0x80000000
 736 #define PSR_FLAGS       0xf0000000
 737
 738 /* TCR_EL1 - Translation Control Register */
 739 #define TCR_HD_SHIFT    40
 740 #define TCR_HD          (0x1UL << TCR_HD_SHIFT)
 741 #define TCR_HA_SHIFT    39
 742 #define TCR_HA          (0x1UL << TCR_HA_SHIFT)
 743
 744 #define TCR_ASID_SHIFT  36
 745 #define TCR_ASID_WIDTH  1
 746 #define TCR_ASID_16     (0x1UL << TCR_ASID_SHIFT)
 747
 748 #define TCR_IPS_SHIFT   32
 749 #define TCR_IPS_WIDTH   3
 750 #define TCR_IPS_32BIT   (0 << TCR_IPS_SHIFT)
 751 #define TCR_IPS_36BIT   (1 << TCR_IPS_SHIFT)
 752 #define TCR_IPS_40BIT   (2 << TCR_IPS_SHIFT)
 753 #define TCR_IPS_42BIT   (3 << TCR_IPS_SHIFT)
 754 #define TCR_IPS_44BIT   (4 << TCR_IPS_SHIFT)
 755 #define TCR_IPS_48BIT   (5 << TCR_IPS_SHIFT)
 756
 757 #define TCR_TG1_SHIFT   30
 758 #define TCR_TG1_16K     (1 << TCR_TG1_SHIFT)
 759 #define TCR_TG1_4K      (2 << TCR_TG1_SHIFT)
 760 #define TCR_TG1_64K     (3 << TCR_TG1_SHIFT)
 761
 762 #define TCR_TG0_MASK    0x000000000000c000
 763
 764 #define TCR_SH1_SHIFT   28
 765 #define TCR_SH1_IS      (0x3UL << TCR_SH1_SHIFT)
 766 #define TCR_ORGN1_SHIFT 26
 767 #define TCR_ORGN1_WBWA  (0x1UL << TCR_ORGN1_SHIFT)
 768 #define TCR_IRGN1_SHIFT 24
 769 #define TCR_IRGN1_WBWA  (0x1UL << TCR_IRGN1_SHIFT)
 770 #define TCR_A1_SHIFT    22
 771 #define TCR_A1          (0x1UL << TCR_A1_SHIFT)
 772 #define TCR_SH0_SHIFT   12
 773 #define TCR_SH0_IS      (0x3UL << TCR_SH0_SHIFT)
 774 #define TCR_ORGN0_SHIFT 10
 775 #define TCR_ORGN0_WBWA  (0x1UL << TCR_ORGN0_SHIFT)
 776 #define TCR_IRGN0_SHIFT 8
 777 #define TCR_IRGN0_WBWA  (0x1UL << TCR_IRGN0_SHIFT)
 778
 779 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
 780                                 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
 781
 782 #ifdef SMP
 783 #define TCR_SMP_ATTRS   (TCR_SH0_IS | TCR_SH1_IS)
 784 #else
 785 #define TCR_SMP_ATTRS   0
 786 #endif
 787
 788 #define TCR_T1SZ_SHIFT  16
 789 #define TCR_T0SZ_SHIFT  0
 790 #define TCR_T0SZ_MASK   0x3f
 791 #define TCR_T1SZ(x)     ((x) << TCR_T1SZ_SHIFT)
 792 #define TCR_T0SZ(x)     ((x) << TCR_T0SZ_SHIFT)
 793 #define TCR_TxSZ(x)     (TCR_T1SZ(x) | TCR_T0SZ(x))
 794
 795 /* Saved Program Status Register */
 796 #define DBG_SPSR_SS     (0x1 << 21)
 797
 798 /* Monitor Debug System Control Register */
 799 #define DBG_MDSCR_SS    (0x1 << 0)
 800 #define DBG_MDSCR_KDE   (0x1 << 13)
 801 #define DBG_MDSCR_MDE   (0x1 << 15)
 802
 803 /* Perfomance Monitoring Counters */
 804 #define PMCR_E          (1 << 0) /* Enable all counters */
 805 #define PMCR_P          (1 << 1) /* Reset all counters */
 806 #define PMCR_C          (1 << 2) /* Clock counter reset */
 807 #define PMCR_D          (1 << 3) /* CNTR counts every 64 clk cycles */
 808 #define PMCR_X          (1 << 4) /* Export to ext. monitoring (ETM) */
 809 #define PMCR_DP         (1 << 5) /* Disable CCNT if non-invasive debug*/
 810 #define PMCR_LC         (1 << 6) /* Long cycle count enable */
 811 #define PMCR_IMP_SHIFT  24 /* Implementer code */
 812 #define PMCR_IMP_MASK   (0xff << PMCR_IMP_SHIFT)
 813 #define PMCR_IDCODE_SHIFT       16 /* Identification code */
 814 #define PMCR_IDCODE_MASK        (0xff << PMCR_IDCODE_SHIFT)
 815 #define  PMCR_IDCODE_CORTEX_A57 0x01
 816 #define  PMCR_IDCODE_CORTEX_A72 0x02
 817 #define  PMCR_IDCODE_CORTEX_A53 0x03
 818 #define PMCR_N_SHIFT    11       /* Number of counters implemented */
 819 #define PMCR_N_MASK     (0x1f << PMCR_N_SHIFT)
 820
 821 #endif /* !_MACHINE_ARMREG_H_ */