2 * Copyright (c) 2013, 2014 Andrew Turner
3 * Copyright (c) 2015 The FreeBSD Foundation
6 * This software was developed by Andrew Turner under
7 * sponsorship from the FreeBSD Foundation.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef _MACHINE_ARMREG_H_
34 #define _MACHINE_ARMREG_H_
36 #define READ_SPECIALREG(reg) \
38 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \
41 #define WRITE_SPECIALREG(reg, val) \
42 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val))
44 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
45 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */
46 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */
47 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */
48 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */
49 #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/
52 #define CPACR_FPEN_MASK (0x3 << 20)
53 #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */
54 #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */
55 #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */
56 #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */
57 #define CPACR_TTA (0x1 << 28)
59 /* CTR_EL0 - Cache Type Register */
60 #define CTR_DLINE_SHIFT 16
61 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT)
62 #define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
63 #define CTR_ILINE_SHIFT 0
64 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT)
65 #define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
68 #define ESR_ELx_ISS_MASK 0x00ffffff
69 #define ISS_INSN_FnV (0x01 << 10)
70 #define ISS_INSN_EA (0x01 << 9)
71 #define ISS_INSN_S1PTW (0x01 << 7)
72 #define ISS_INSN_IFSC_MASK (0x1f << 0)
73 #define ISS_DATA_ISV (0x01 << 24)
74 #define ISS_DATA_SAS_MASK (0x03 << 22)
75 #define ISS_DATA_SSE (0x01 << 21)
76 #define ISS_DATA_SRT_MASK (0x1f << 16)
77 #define ISS_DATA_SF (0x01 << 15)
78 #define ISS_DATA_AR (0x01 << 14)
79 #define ISS_DATA_FnV (0x01 << 10)
80 #define ISS_DATa_EA (0x01 << 9)
81 #define ISS_DATa_CM (0x01 << 8)
82 #define ISS_INSN_S1PTW (0x01 << 7)
83 #define ISS_DATa_WnR (0x01 << 6)
84 #define ISS_DATA_DFSC_MASK (0x1f << 0)
85 #define ESR_ELx_IL (0x01 << 25)
86 #define ESR_ELx_EC_SHIFT 26
87 #define ESR_ELx_EC_MASK (0x3f << 26)
88 #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
89 #define EXCP_UNKNOWN 0x00 /* Unkwn exception */
90 #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */
91 #define EXCP_ILL_STATE 0x0e /* Illegal execution state */
92 #define EXCP_SVC 0x15 /* SVC trap */
93 #define EXCP_MSR 0x18 /* MSR/MRS trap */
94 #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */
95 #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */
96 #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */
97 #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */
98 #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */
99 #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */
100 #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */
101 #define EXCP_SERROR 0x2f /* SError interrupt */
102 #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */
103 #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */
104 #define EXCP_BRK 0x3c /* Breakpoint */
107 #define ICC_CTLR_EL1_EOIMODE (1U << 1)
110 #define ICC_IAR1_EL1_SPUR (0x03ff)
112 /* ICC_IGRPEN0_EL1 */
113 #define ICC_IGRPEN0_EL1_EN (1U << 0)
116 #define ICC_PMR_EL1_PRIO_MASK (0xFFUL)
119 #define ICC_SRE_EL1_SRE (1U << 0)
122 #define ICC_SRE_EL2_EN (1U << 3)
124 /* ID_AA64PFR0_EL1 */
125 #define ID_AA64PFR0_EL0_MASK (0xf << 0)
126 #define ID_AA64PFR0_EL1_MASK (0xf << 4)
127 #define ID_AA64PFR0_EL2_MASK (0xf << 8)
128 #define ID_AA64PFR0_EL3_MASK (0xf << 12)
129 #define ID_AA64PFR0_FP_MASK (0xf << 16)
130 #define ID_AA64PFR0_FP_IMPL (0x0 << 16) /* Floating-point implemented */
131 #define ID_AA64PFR0_FP_NONE (0xf << 16) /* Floating-point not implemented */
132 #define ID_AA64PFR0_ADV_SIMD_MASK (0xf << 20)
133 #define ID_AA64PFR0_GIC_SHIFT (24)
134 #define ID_AA64PFR0_GIC_BITS (0x4) /* Number of bits in GIC field */
135 #define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT)
136 #define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT)
138 /* MAIR_EL1 - Memory Attribute Indirection Register */
139 #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))
140 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
142 /* SCTLR_EL1 - System Control Register */
143 #define SCTLR_RES0 0xc8222400 /* Reserved, write 0 */
144 #define SCTLR_RES1 0x30d00800 /* Reserved, write 1 */
146 #define SCTLR_M 0x00000001
147 #define SCTLR_A 0x00000002
148 #define SCTLR_C 0x00000004
149 #define SCTLR_SA 0x00000008
150 #define SCTLR_SA0 0x00000010
151 #define SCTLR_CP15BEN 0x00000020
152 #define SCTLR_THEE 0x00000040
153 #define SCTLR_ITD 0x00000080
154 #define SCTLR_SED 0x00000100
155 #define SCTLR_UMA 0x00000200
156 #define SCTLR_I 0x00001000
157 #define SCTLR_DZE 0x00004000
158 #define SCTLR_UCT 0x00008000
159 #define SCTLR_nTWI 0x00010000
160 #define SCTLR_nTWE 0x00040000
161 #define SCTLR_WXN 0x00080000
162 #define SCTLR_EOE 0x01000000
163 #define SCTLR_EE 0x02000000
164 #define SCTLR_UCI 0x04000000
168 * When the exception is taken in AArch64:
169 * M[4] is 0 for AArch64 mode
170 * M[3:2] is the exception level
172 * M[0] is the SP select:
176 #define PSR_M_EL0t 0x00000000
177 #define PSR_M_EL1t 0x00000004
178 #define PSR_M_EL1h 0x00000005
179 #define PSR_M_EL2t 0x00000008
180 #define PSR_M_EL2h 0x00000009
181 #define PSR_M_MASK 0x0000001f
183 #define PSR_F 0x00000040
184 #define PSR_I 0x00000080
185 #define PSR_A 0x00000100
186 #define PSR_D 0x00000200
187 #define PSR_IL 0x00100000
188 #define PSR_SS 0x00200000
189 #define PSR_V 0x10000000
190 #define PSR_C 0x20000000
191 #define PSR_Z 0x40000000
192 #define PSR_N 0x80000000
194 /* TCR_EL1 - Translation Control Register */
195 #define TCR_ASID_16 (1 << 36)
197 #define TCR_IPS_SHIFT 32
198 #define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT)
199 #define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT)
200 #define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT)
201 #define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT)
202 #define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT)
203 #define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT)
205 #define TCR_TG1_SHIFT 30
206 #define TCR_TG1_16K (1 << TCR_TG1_SHIFT)
207 #define TCR_TG1_4K (2 << TCR_TG1_SHIFT)
208 #define TCR_TG1_64K (3 << TCR_TG1_SHIFT)
210 #define TCR_SH1_SHIFT 28
211 #define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT)
212 #define TCR_ORGN1_SHIFT 26
213 #define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT)
214 #define TCR_IRGN1_SHIFT 24
215 #define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT)
216 #define TCR_SH0_SHIFT 12
217 #define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT)
218 #define TCR_ORGN0_SHIFT 10
219 #define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT)
220 #define TCR_IRGN0_SHIFT 8
221 #define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT)
223 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
224 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
227 #define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS)
229 #define TCR_SMP_ATTRS 0
232 #define TCR_T1SZ_SHIFT 16
233 #define TCR_T0SZ_SHIFT 0
234 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT)
235 #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT)
236 #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x))
238 /* Saved Program Status Register */
239 #define DBG_SPSR_SS (0x1 << 21)
241 /* Monitor Debug System Control Register */
242 #define DBG_MDSCR_SS (0x1 << 0)
243 #define DBG_MDSCR_KDE (0x1 << 13)
244 #define DBG_MDSCR_MDE (0x1 << 15)
246 /* Perfomance Monitoring Counters */
247 #define PMCR_E (1 << 0) /* Enable all counters */
248 #define PMCR_P (1 << 1) /* Reset all counters */
249 #define PMCR_C (1 << 2) /* Clock counter reset */
250 #define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */
251 #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */
252 #define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
253 #define PMCR_LC (1 << 6) /* Long cycle count enable */
254 #define PMCR_IMP_SHIFT 24 /* Implementer code */
255 #define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT)
256 #define PMCR_IDCODE_SHIFT 16 /* Identification code */
257 #define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT)
258 #define PMCR_IDCODE_CORTEX_A57 0x01
259 #define PMCR_IDCODE_CORTEX_A72 0x02
260 #define PMCR_IDCODE_CORTEX_A53 0x03
261 #define PMCR_N_SHIFT 11 /* Number of counters implemented */
262 #define PMCR_N_MASK (0x1f << PMCR_N_SHIFT)
264 #endif /* !_MACHINE_ARMREG_H_ */