2 * Copyright (c) 2013, 2014 Andrew Turner
3 * Copyright (c) 2015 The FreeBSD Foundation
6 * This software was developed by Andrew Turner under
7 * sponsorship from the FreeBSD Foundation.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef _MACHINE_ARMREG_H_
34 #define _MACHINE_ARMREG_H_
38 #define MRS_MASK 0xfff00000
39 #define MRS_VALUE 0xd5300000
40 #define MRS_SPECIAL(insn) ((insn) & 0x000fffe0)
41 #define MRS_REGISTER(insn) ((insn) & 0x0000001f)
42 #define MRS_Op0_SHIFT 19
43 #define MRS_Op0_MASK 0x00080000
44 #define MRS_Op1_SHIFT 16
45 #define MRS_Op1_MASK 0x00070000
46 #define MRS_CRn_SHIFT 12
47 #define MRS_CRn_MASK 0x0000f000
48 #define MRS_CRm_SHIFT 8
49 #define MRS_CRm_MASK 0x00000f00
50 #define MRS_Op2_SHIFT 5
51 #define MRS_Op2_MASK 0x000000e0
52 #define MRS_Rt_SHIFT 0
53 #define MRS_Rt_MASK 0x0000001f
54 #define MRS_REG(op0, op1, crn, crm, op2) \
55 (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) | \
56 ((crn) << MRS_CRn_SHIFT) | ((crm) << MRS_CRm_SHIFT) | \
57 ((op2) << MRS_Op2_SHIFT))
59 #define READ_SPECIALREG(reg) \
61 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \
64 #define WRITE_SPECIALREG(reg, _val) \
65 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val))
67 #define UL(x) UINT64_C(x)
69 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
70 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */
71 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */
72 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */
73 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */
74 #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/
77 #define CPACR_FPEN_MASK (0x3 << 20)
78 #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */
79 #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */
80 #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */
81 #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */
82 #define CPACR_TTA (0x1 << 28)
84 /* CTR_EL0 - Cache Type Register */
85 #define CTR_DLINE_SHIFT 16
86 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT)
87 #define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
88 #define CTR_ILINE_SHIFT 0
89 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT)
90 #define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
92 /* DAIF - Interrupt Mask Bits */
93 #define DAIF_D_MASKED (1 << 9)
94 #define DAIF_A_MASKED (1 << 8)
95 #define DAIF_I_MASKED (1 << 7)
96 #define DAIF_F_MASKED (1 << 6)
98 /* DCZID_EL0 - Data Cache Zero ID register */
99 #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */
100 #define DCZID_BS_SHIFT 0
101 #define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT)
102 #define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
105 #define ESR_ELx_ISS_MASK 0x00ffffff
106 #define ISS_INSN_FnV (0x01 << 10)
107 #define ISS_INSN_EA (0x01 << 9)
108 #define ISS_INSN_S1PTW (0x01 << 7)
109 #define ISS_INSN_IFSC_MASK (0x1f << 0)
110 #define ISS_DATA_ISV (0x01 << 24)
111 #define ISS_DATA_SAS_MASK (0x03 << 22)
112 #define ISS_DATA_SSE (0x01 << 21)
113 #define ISS_DATA_SRT_MASK (0x1f << 16)
114 #define ISS_DATA_SF (0x01 << 15)
115 #define ISS_DATA_AR (0x01 << 14)
116 #define ISS_DATA_FnV (0x01 << 10)
117 #define ISS_DATA_EA (0x01 << 9)
118 #define ISS_DATA_CM (0x01 << 8)
119 #define ISS_DATA_S1PTW (0x01 << 7)
120 #define ISS_DATA_WnR (0x01 << 6)
121 #define ISS_DATA_DFSC_MASK (0x3f << 0)
122 #define ISS_DATA_DFSC_ASF_L0 (0x00 << 0)
123 #define ISS_DATA_DFSC_ASF_L1 (0x01 << 0)
124 #define ISS_DATA_DFSC_ASF_L2 (0x02 << 0)
125 #define ISS_DATA_DFSC_ASF_L3 (0x03 << 0)
126 #define ISS_DATA_DFSC_TF_L0 (0x04 << 0)
127 #define ISS_DATA_DFSC_TF_L1 (0x05 << 0)
128 #define ISS_DATA_DFSC_TF_L2 (0x06 << 0)
129 #define ISS_DATA_DFSC_TF_L3 (0x07 << 0)
130 #define ISS_DATA_DFSC_AFF_L1 (0x09 << 0)
131 #define ISS_DATA_DFSC_AFF_L2 (0x0a << 0)
132 #define ISS_DATA_DFSC_AFF_L3 (0x0b << 0)
133 #define ISS_DATA_DFSC_PF_L1 (0x0d << 0)
134 #define ISS_DATA_DFSC_PF_L2 (0x0e << 0)
135 #define ISS_DATA_DFSC_PF_L3 (0x0f << 0)
136 #define ISS_DATA_DFSC_EXT (0x10 << 0)
137 #define ISS_DATA_DFSC_EXT_L0 (0x14 << 0)
138 #define ISS_DATA_DFSC_EXT_L1 (0x15 << 0)
139 #define ISS_DATA_DFSC_EXT_L2 (0x16 << 0)
140 #define ISS_DATA_DFSC_EXT_L3 (0x17 << 0)
141 #define ISS_DATA_DFSC_ECC (0x18 << 0)
142 #define ISS_DATA_DFSC_ECC_L0 (0x1c << 0)
143 #define ISS_DATA_DFSC_ECC_L1 (0x1d << 0)
144 #define ISS_DATA_DFSC_ECC_L2 (0x1e << 0)
145 #define ISS_DATA_DFSC_ECC_L3 (0x1f << 0)
146 #define ISS_DATA_DFSC_ALIGN (0x21 << 0)
147 #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0)
148 #define ESR_ELx_IL (0x01 << 25)
149 #define ESR_ELx_EC_SHIFT 26
150 #define ESR_ELx_EC_MASK (0x3f << 26)
151 #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
152 #define EXCP_UNKNOWN 0x00 /* Unkwn exception */
153 #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */
154 #define EXCP_ILL_STATE 0x0e /* Illegal execution state */
155 #define EXCP_SVC32 0x11 /* SVC trap for AArch32 */
156 #define EXCP_SVC64 0x15 /* SVC trap for AArch64 */
157 #define EXCP_MSR 0x18 /* MSR/MRS trap */
158 #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */
159 #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */
160 #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */
161 #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */
162 #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */
163 #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */
164 #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */
165 #define EXCP_SERROR 0x2f /* SError interrupt */
166 #define EXCP_BRKPT_EL0 0x30 /* Hardware breakpoint, from same EL */
167 #define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */
168 #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */
169 #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */
170 #define EXCP_BRK 0x3c /* Breakpoint */
173 #define ICC_CTLR_EL1_EOIMODE (1U << 1)
176 #define ICC_IAR1_EL1_SPUR (0x03ff)
178 /* ICC_IGRPEN0_EL1 */
179 #define ICC_IGRPEN0_EL1_EN (1U << 0)
182 #define ICC_PMR_EL1_PRIO_MASK (0xFFUL)
185 #define ICC_SGI1R_EL1_TL_MASK 0xffffUL
186 #define ICC_SGI1R_EL1_AFF1_SHIFT 16
187 #define ICC_SGI1R_EL1_SGIID_SHIFT 24
188 #define ICC_SGI1R_EL1_AFF2_SHIFT 32
189 #define ICC_SGI1R_EL1_AFF3_SHIFT 48
190 #define ICC_SGI1R_EL1_SGIID_MASK 0xfUL
191 #define ICC_SGI1R_EL1_IRM (0x1UL << 40)
194 #define ICC_SRE_EL1_SRE (1U << 0)
197 #define ICC_SRE_EL2_SRE (1U << 0)
198 #define ICC_SRE_EL2_EN (1U << 3)
200 /* ID_AA64DFR0_EL1 */
201 #define ID_AA64DFR0_EL1 MRS_REG(3, 0, 0, 5, 0)
202 #define ID_AA64DFR0_DebugVer_SHIFT 0
203 #define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)
204 #define ID_AA64DFR0_DebugVer_VAL(x) ((x) & ID_AA64DFR0_DebugVer_MASK)
205 #define ID_AA64DFR0_DebugVer_8 (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT)
206 #define ID_AA64DFR0_DebugVer_8_VHE (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT)
207 #define ID_AA64DFR0_DebugVer_8_2 (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT)
208 #define ID_AA64DFR0_TraceVer_SHIFT 4
209 #define ID_AA64DFR0_TraceVer_MASK (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT)
210 #define ID_AA64DFR0_TraceVer_VAL(x) ((x) & ID_AA64DFR0_TraceVer_MASK)
211 #define ID_AA64DFR0_TraceVer_NONE (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT)
212 #define ID_AA64DFR0_TraceVer_IMPL (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT)
213 #define ID_AA64DFR0_PMUVer_SHIFT 8
214 #define ID_AA64DFR0_PMUVer_MASK (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
215 #define ID_AA64DFR0_PMUVer_VAL(x) ((x) & ID_AA64DFR0_PMUVer_MASK)
216 #define ID_AA64DFR0_PMUVer_NONE (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT)
217 #define ID_AA64DFR0_PMUVer_3 (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT)
218 #define ID_AA64DFR0_PMUVer_3_1 (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT)
219 #define ID_AA64DFR0_PMUVer_IMPL (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
220 #define ID_AA64DFR0_BRPs_SHIFT 12
221 #define ID_AA64DFR0_BRPs_MASK (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT)
222 #define ID_AA64DFR0_BRPs_VAL(x) \
223 ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1)
224 #define ID_AA64DFR0_WRPs_SHIFT 20
225 #define ID_AA64DFR0_WRPs_MASK (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT)
226 #define ID_AA64DFR0_WRPs_VAL(x) \
227 ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1)
228 #define ID_AA64DFR0_CTX_CMPs_SHIFT 28
229 #define ID_AA64DFR0_CTX_CMPs_MASK (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT)
230 #define ID_AA64DFR0_CTX_CMPs_VAL(x) \
231 ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1)
232 #define ID_AA64DFR0_PMSVer_SHIFT 32
233 #define ID_AA64DFR0_PMSVer_MASK (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT)
234 #define ID_AA64DFR0_PMSVer_VAL(x) ((x) & ID_AA64DFR0_PMSVer_MASK)
235 #define ID_AA64DFR0_PMSVer_NONE (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT)
236 #define ID_AA64DFR0_PMSVer_V1 (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT)
238 /* ID_AA64ISAR0_EL1 */
239 #define ID_AA64ISAR0_EL1 MRS_REG(3, 0, 0, 6, 0)
240 #define ID_AA64ISAR0_AES_SHIFT 4
241 #define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT)
242 #define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK)
243 #define ID_AA64ISAR0_AES_NONE (UL(0x0) << ID_AA64ISAR0_AES_SHIFT)
244 #define ID_AA64ISAR0_AES_BASE (UL(0x1) << ID_AA64ISAR0_AES_SHIFT)
245 #define ID_AA64ISAR0_AES_PMULL (UL(0x2) << ID_AA64ISAR0_AES_SHIFT)
246 #define ID_AA64ISAR0_SHA1_SHIFT 8
247 #define ID_AA64ISAR0_SHA1_MASK (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT)
248 #define ID_AA64ISAR0_SHA1_VAL(x) ((x) & ID_AA64ISAR0_SHA1_MASK)
249 #define ID_AA64ISAR0_SHA1_NONE (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT)
250 #define ID_AA64ISAR0_SHA1_BASE (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT)
251 #define ID_AA64ISAR0_SHA2_SHIFT 12
252 #define ID_AA64ISAR0_SHA2_MASK (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT)
253 #define ID_AA64ISAR0_SHA2_VAL(x) ((x) & ID_AA64ISAR0_SHA2_MASK)
254 #define ID_AA64ISAR0_SHA2_NONE (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT)
255 #define ID_AA64ISAR0_SHA2_BASE (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT)
256 #define ID_AA64ISAR0_SHA2_512 (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT)
257 #define ID_AA64ISAR0_CRC32_SHIFT 16
258 #define ID_AA64ISAR0_CRC32_MASK (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT)
259 #define ID_AA64ISAR0_CRC32_VAL(x) ((x) & ID_AA64ISAR0_CRC32_MASK)
260 #define ID_AA64ISAR0_CRC32_NONE (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT)
261 #define ID_AA64ISAR0_CRC32_BASE (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT)
262 #define ID_AA64ISAR0_Atomic_SHIFT 20
263 #define ID_AA64ISAR0_Atomic_MASK (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT)
264 #define ID_AA64ISAR0_Atomic_VAL(x) ((x) & ID_AA64ISAR0_Atomic_MASK)
265 #define ID_AA64ISAR0_Atomic_NONE (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT)
266 #define ID_AA64ISAR0_Atomic_IMPL (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT)
267 #define ID_AA64ISAR0_RDM_SHIFT 28
268 #define ID_AA64ISAR0_RDM_MASK (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT)
269 #define ID_AA64ISAR0_RDM_VAL(x) ((x) & ID_AA64ISAR0_RDM_MASK)
270 #define ID_AA64ISAR0_RDM_NONE (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT)
271 #define ID_AA64ISAR0_RDM_IMPL (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT)
272 #define ID_AA64ISAR0_SHA3_SHIFT 32
273 #define ID_AA64ISAR0_SHA3_MASK (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT)
274 #define ID_AA64ISAR0_SHA3_VAL(x) ((x) & ID_AA64ISAR0_SHA3_MASK)
275 #define ID_AA64ISAR0_SHA3_NONE (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT)
276 #define ID_AA64ISAR0_SHA3_IMPL (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT)
277 #define ID_AA64ISAR0_SM3_SHIFT 36
278 #define ID_AA64ISAR0_SM3_MASK (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT)
279 #define ID_AA64ISAR0_SM3_VAL(x) ((x) & ID_AA64ISAR0_SM3_MASK)
280 #define ID_AA64ISAR0_SM3_NONE (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT)
281 #define ID_AA64ISAR0_SM3_IMPL (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT)
282 #define ID_AA64ISAR0_SM4_SHIFT 40
283 #define ID_AA64ISAR0_SM4_MASK (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT)
284 #define ID_AA64ISAR0_SM4_VAL(x) ((x) & ID_AA64ISAR0_SM4_MASK)
285 #define ID_AA64ISAR0_SM4_NONE (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT)
286 #define ID_AA64ISAR0_SM4_IMPL (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT)
287 #define ID_AA64ISAR0_DP_SHIFT 44
288 #define ID_AA64ISAR0_DP_MASK (UL(0xf) << ID_AA64ISAR0_DP_SHIFT)
289 #define ID_AA64ISAR0_DP_VAL(x) ((x) & ID_AA64ISAR0_DP_MASK)
290 #define ID_AA64ISAR0_DP_NONE (UL(0x0) << ID_AA64ISAR0_DP_SHIFT)
291 #define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT)
293 /* ID_AA64ISAR1_EL1 */
294 #define ID_AA64ISAR1_EL1 MRS_REG(3, 0, 0, 6, 1)
295 #define ID_AA64ISAR1_DPB_SHIFT 0
296 #define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
297 #define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK)
298 #define ID_AA64ISAR1_DPB_NONE (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT)
299 #define ID_AA64ISAR1_DPB_IMPL (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT)
300 #define ID_AA64ISAR1_APA_SHIFT 4
301 #define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT)
302 #define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK)
303 #define ID_AA64ISAR1_APA_NONE (UL(0x0) << ID_AA64ISAR1_APA_SHIFT)
304 #define ID_AA64ISAR1_APA_IMPL (UL(0x1) << ID_AA64ISAR1_APA_SHIFT)
305 #define ID_AA64ISAR1_API_SHIFT 8
306 #define ID_AA64ISAR1_API_MASK (UL(0xf) << ID_AA64ISAR1_API_SHIFT)
307 #define ID_AA64ISAR1_API_VAL(x) ((x) & ID_AA64ISAR1_API_MASK)
308 #define ID_AA64ISAR1_API_NONE (UL(0x0) << ID_AA64ISAR1_API_SHIFT)
309 #define ID_AA64ISAR1_API_IMPL (UL(0x1) << ID_AA64ISAR1_API_SHIFT)
310 #define ID_AA64ISAR1_JSCVT_SHIFT 12
311 #define ID_AA64ISAR1_JSCVT_MASK (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT)
312 #define ID_AA64ISAR1_JSCVT_VAL(x) ((x) & ID_AA64ISAR1_JSCVT_MASK)
313 #define ID_AA64ISAR1_JSCVT_NONE (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT)
314 #define ID_AA64ISAR1_JSCVT_IMPL (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT)
315 #define ID_AA64ISAR1_FCMA_SHIFT 16
316 #define ID_AA64ISAR1_FCMA_MASK (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT)
317 #define ID_AA64ISAR1_FCMA_VAL(x) ((x) & ID_AA64ISAR1_FCMA_MASK)
318 #define ID_AA64ISAR1_FCMA_NONE (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT)
319 #define ID_AA64ISAR1_FCMA_IMPL (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT)
320 #define ID_AA64ISAR1_LRCPC_SHIFT 20
321 #define ID_AA64ISAR1_LRCPC_MASK (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT)
322 #define ID_AA64ISAR1_LRCPC_VAL(x) ((x) & ID_AA64ISAR1_LRCPC_MASK)
323 #define ID_AA64ISAR1_LRCPC_NONE (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT)
324 #define ID_AA64ISAR1_LRCPC_IMPL (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT)
325 #define ID_AA64ISAR1_GPA_SHIFT 24
326 #define ID_AA64ISAR1_GPA_MASK (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT)
327 #define ID_AA64ISAR1_GPA_VAL(x) ((x) & ID_AA64ISAR1_GPA_MASK)
328 #define ID_AA64ISAR1_GPA_NONE (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT)
329 #define ID_AA64ISAR1_GPA_IMPL (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT)
330 #define ID_AA64ISAR1_GPI_SHIFT 28
331 #define ID_AA64ISAR1_GPI_MASK (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT)
332 #define ID_AA64ISAR1_GPI_VAL(x) ((x) & ID_AA64ISAR1_GPI_MASK)
333 #define ID_AA64ISAR1_GPI_NONE (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT)
334 #define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT)
336 /* ID_AA64MMFR0_EL1 */
337 #define ID_AA64MMFR0_EL1 MRS_REG(3, 0, 0, 7, 0)
338 #define ID_AA64MMFR0_PARange_SHIFT 0
339 #define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
340 #define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK)
341 #define ID_AA64MMFR0_PARange_4G (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT)
342 #define ID_AA64MMFR0_PARange_64G (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT)
343 #define ID_AA64MMFR0_PARange_1T (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT)
344 #define ID_AA64MMFR0_PARange_4T (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT)
345 #define ID_AA64MMFR0_PARange_16T (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT)
346 #define ID_AA64MMFR0_PARange_256T (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT)
347 #define ID_AA64MMFR0_PARange_4P (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT)
348 #define ID_AA64MMFR0_ASIDBits_SHIFT 4
349 #define ID_AA64MMFR0_ASIDBits_MASK (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT)
350 #define ID_AA64MMFR0_ASIDBits_VAL(x) ((x) & ID_AA64MMFR0_ASIDBits_MASK)
351 #define ID_AA64MMFR0_ASIDBits_8 (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT)
352 #define ID_AA64MMFR0_ASIDBits_16 (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT)
353 #define ID_AA64MMFR0_BigEnd_SHIFT 8
354 #define ID_AA64MMFR0_BigEnd_MASK (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT)
355 #define ID_AA64MMFR0_BigEnd_VAL(x) ((x) & ID_AA64MMFR0_BigEnd_MASK)
356 #define ID_AA64MMFR0_BigEnd_FIXED (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT)
357 #define ID_AA64MMFR0_BigEnd_MIXED (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT)
358 #define ID_AA64MMFR0_SNSMem_SHIFT 12
359 #define ID_AA64MMFR0_SNSMem_MASK (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT)
360 #define ID_AA64MMFR0_SNSMem_VAL(x) ((x) & ID_AA64MMFR0_SNSMem_MASK)
361 #define ID_AA64MMFR0_SNSMem_NONE (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT)
362 #define ID_AA64MMFR0_SNSMem_DISTINCT (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT)
363 #define ID_AA64MMFR0_BigEndEL0_SHIFT 16
364 #define ID_AA64MMFR0_BigEndEL0_MASK (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT)
365 #define ID_AA64MMFR0_BigEndEL0_VAL(x) ((x) & ID_AA64MMFR0_BigEndEL0_MASK)
366 #define ID_AA64MMFR0_BigEndEL0_FIXED (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT)
367 #define ID_AA64MMFR0_BigEndEL0_MIXED (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT)
368 #define ID_AA64MMFR0_TGran16_SHIFT 20
369 #define ID_AA64MMFR0_TGran16_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT)
370 #define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK)
371 #define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT)
372 #define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT)
373 #define ID_AA64MMFR0_TGran64_SHIFT 24
374 #define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
375 #define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK)
376 #define ID_AA64MMFR0_TGran64_IMPL (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT)
377 #define ID_AA64MMFR0_TGran64_NONE (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
378 #define ID_AA64MMFR0_TGran4_SHIFT 28
379 #define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
380 #define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK)
381 #define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT)
382 #define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
384 /* ID_AA64MMFR1_EL1 */
385 #define ID_AA64MMFR1_EL1 MRS_REG(3, 0, 0, 7, 1)
386 #define ID_AA64MMFR1_HAFDBS_SHIFT 0
387 #define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
388 #define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK)
389 #define ID_AA64MMFR1_HAFDBS_NONE (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT)
390 #define ID_AA64MMFR1_HAFDBS_AF (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT)
391 #define ID_AA64MMFR1_HAFDBS_AF_DBS (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT)
392 #define ID_AA64MMFR1_VMIDBits_SHIFT 4
393 #define ID_AA64MMFR1_VMIDBits_MASK (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT)
394 #define ID_AA64MMFR1_VMIDBits_VAL(x) ((x) & ID_AA64MMFR1_VMIDBits_MASK)
395 #define ID_AA64MMFR1_VMIDBits_8 (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT)
396 #define ID_AA64MMFR1_VMIDBits_16 (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT)
397 #define ID_AA64MMFR1_VH_SHIFT 8
398 #define ID_AA64MMFR1_VH_MASK (UL(0xf) << ID_AA64MMFR1_VH_SHIFT)
399 #define ID_AA64MMFR1_VH_VAL(x) ((x) & ID_AA64MMFR1_VH_MASK)
400 #define ID_AA64MMFR1_VH_NONE (UL(0x0) << ID_AA64MMFR1_VH_SHIFT)
401 #define ID_AA64MMFR1_VH_IMPL (UL(0x1) << ID_AA64MMFR1_VH_SHIFT)
402 #define ID_AA64MMFR1_HPDS_SHIFT 12
403 #define ID_AA64MMFR1_HPDS_MASK (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT)
404 #define ID_AA64MMFR1_HPDS_VAL(x) ((x) & ID_AA64MMFR1_HPDS_MASK)
405 #define ID_AA64MMFR1_HPDS_NONE (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT)
406 #define ID_AA64MMFR1_HPDS_HPD (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT)
407 #define ID_AA64MMFR1_HPDS_TTPBHA (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT)
408 #define ID_AA64MMFR1_LO_SHIFT 16
409 #define ID_AA64MMFR1_LO_MASK (UL(0xf) << ID_AA64MMFR1_LO_SHIFT)
410 #define ID_AA64MMFR1_LO_VAL(x) ((x) & ID_AA64MMFR1_LO_MASK)
411 #define ID_AA64MMFR1_LO_NONE (UL(0x0) << ID_AA64MMFR1_LO_SHIFT)
412 #define ID_AA64MMFR1_LO_IMPL (UL(0x1) << ID_AA64MMFR1_LO_SHIFT)
413 #define ID_AA64MMFR1_PAN_SHIFT 20
414 #define ID_AA64MMFR1_PAN_MASK (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT)
415 #define ID_AA64MMFR1_PAN_VAL(x) ((x) & ID_AA64MMFR1_PAN_MASK)
416 #define ID_AA64MMFR1_PAN_NONE (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT)
417 #define ID_AA64MMFR1_PAN_IMPL (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT)
418 #define ID_AA64MMFR1_PAN_ATS1E1 (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT)
419 #define ID_AA64MMFR1_SpecSEI_SHIFT 24
420 #define ID_AA64MMFR1_SpecSEI_MASK (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT)
421 #define ID_AA64MMFR1_SpecSEI_VAL(x) ((x) & ID_AA64MMFR1_SpecSEI_MASK)
422 #define ID_AA64MMFR1_SpecSEI_NONE (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT)
423 #define ID_AA64MMFR1_SpecSEI_IMPL (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT)
424 #define ID_AA64MMFR1_XNX_SHIFT 28
425 #define ID_AA64MMFR1_XNX_MASK (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT)
426 #define ID_AA64MMFR1_XNX_VAL(x) ((x) & ID_AA64MMFR1_XNX_MASK)
427 #define ID_AA64MMFR1_XNX_NONE (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT)
428 #define ID_AA64MMFR1_XNX_IMPL (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT)
430 /* ID_AA64MMFR2_EL1 */
431 #define ID_AA64MMFR2_EL1 MRS_REG(3, 0, 0, 7, 2)
432 #define ID_AA64MMFR2_CnP_SHIFT 0
433 #define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT)
434 #define ID_AA64MMFR2_CnP_VAL(x) ((x) & ID_AA64MMFR2_CnP_MASK)
435 #define ID_AA64MMFR2_CnP_NONE (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT)
436 #define ID_AA64MMFR2_CnP_IMPL (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT)
437 #define ID_AA64MMFR2_UAO_SHIFT 4
438 #define ID_AA64MMFR2_UAO_MASK (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT)
439 #define ID_AA64MMFR2_UAO_VAL(x) ((x) & ID_AA64MMFR2_UAO_MASK)
440 #define ID_AA64MMFR2_UAO_NONE (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT)
441 #define ID_AA64MMFR2_UAO_IMPL (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT)
442 #define ID_AA64MMFR2_LSM_SHIFT 8
443 #define ID_AA64MMFR2_LSM_MASK (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT)
444 #define ID_AA64MMFR2_LSM_VAL(x) ((x) & ID_AA64MMFR2_LSM_MASK)
445 #define ID_AA64MMFR2_LSM_NONE (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT)
446 #define ID_AA64MMFR2_LSM_IMPL (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT)
447 #define ID_AA64MMFR2_IESB_SHIFT 12
448 #define ID_AA64MMFR2_IESB_MASK (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT)
449 #define ID_AA64MMFR2_IESB_VAL(x) ((x) & ID_AA64MMFR2_IESB_MASK)
450 #define ID_AA64MMFR2_IESB_NONE (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT)
451 #define ID_AA64MMFR2_IESB_IMPL (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT)
452 #define ID_AA64MMFR2_VARange_SHIFT 16
453 #define ID_AA64MMFR2_VARange_MASK (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT)
454 #define ID_AA64MMFR2_VARange_VAL(x) ((x) & ID_AA64MMFR2_VARange_MASK)
455 #define ID_AA64MMFR2_VARange_48 (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT)
456 #define ID_AA64MMFR2_VARange_52 (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT)
457 #define ID_AA64MMFR2_CCIDX_SHIFT 20
458 #define ID_AA64MMFR2_CCIDX_MASK (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT)
459 #define ID_AA64MMFR2_CCIDX_VAL(x) ((x) & ID_AA64MMFR2_CCIDX_MASK)
460 #define ID_AA64MMFR2_CCIDX_32 (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT)
461 #define ID_AA64MMFR2_CCIDX_64 (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT)
462 #define ID_AA64MMFR2_NV_SHIFT 24
463 #define ID_AA64MMFR2_NV_MASK (UL(0xf) << ID_AA64MMFR2_NV_SHIFT)
464 #define ID_AA64MMFR2_NV_VAL(x) ((x) & ID_AA64MMFR2_NV_MASK)
465 #define ID_AA64MMFR2_NV_NONE (UL(0x0) << ID_AA64MMFR2_NV_SHIFT)
466 #define ID_AA64MMFR2_NV_IMPL (UL(0x1) << ID_AA64MMFR2_NV_SHIFT)
468 /* ID_AA64PFR0_EL1 */
469 #define ID_AA64PFR0_EL1 MRS_REG(3, 0, 0, 4, 0)
470 #define ID_AA64PFR0_EL0_SHIFT 0
471 #define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT)
472 #define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK)
473 #define ID_AA64PFR0_EL0_64 (UL(0x1) << ID_AA64PFR0_EL0_SHIFT)
474 #define ID_AA64PFR0_EL0_64_32 (UL(0x2) << ID_AA64PFR0_EL0_SHIFT)
475 #define ID_AA64PFR0_EL1_SHIFT 4
476 #define ID_AA64PFR0_EL1_MASK (UL(0xf) << ID_AA64PFR0_EL1_SHIFT)
477 #define ID_AA64PFR0_EL1_VAL(x) ((x) & ID_AA64PFR0_EL1_MASK)
478 #define ID_AA64PFR0_EL1_64 (UL(0x1) << ID_AA64PFR0_EL1_SHIFT)
479 #define ID_AA64PFR0_EL1_64_32 (UL(0x2) << ID_AA64PFR0_EL1_SHIFT)
480 #define ID_AA64PFR0_EL2_SHIFT 8
481 #define ID_AA64PFR0_EL2_MASK (UL(0xf) << ID_AA64PFR0_EL2_SHIFT)
482 #define ID_AA64PFR0_EL2_VAL(x) ((x) & ID_AA64PFR0_EL2_MASK)
483 #define ID_AA64PFR0_EL2_NONE (UL(0x0) << ID_AA64PFR0_EL2_SHIFT)
484 #define ID_AA64PFR0_EL2_64 (UL(0x1) << ID_AA64PFR0_EL2_SHIFT)
485 #define ID_AA64PFR0_EL2_64_32 (UL(0x2) << ID_AA64PFR0_EL2_SHIFT)
486 #define ID_AA64PFR0_EL3_SHIFT 12
487 #define ID_AA64PFR0_EL3_MASK (UL(0xf) << ID_AA64PFR0_EL3_SHIFT)
488 #define ID_AA64PFR0_EL3_VAL(x) ((x) & ID_AA64PFR0_EL3_MASK)
489 #define ID_AA64PFR0_EL3_NONE (UL(0x0) << ID_AA64PFR0_EL3_SHIFT)
490 #define ID_AA64PFR0_EL3_64 (UL(0x1) << ID_AA64PFR0_EL3_SHIFT)
491 #define ID_AA64PFR0_EL3_64_32 (UL(0x2) << ID_AA64PFR0_EL3_SHIFT)
492 #define ID_AA64PFR0_FP_SHIFT 16
493 #define ID_AA64PFR0_FP_MASK (UL(0xf) << ID_AA64PFR0_FP_SHIFT)
494 #define ID_AA64PFR0_FP_VAL(x) ((x) & ID_AA64PFR0_FP_MASK)
495 #define ID_AA64PFR0_FP_IMPL (UL(0x0) << ID_AA64PFR0_FP_SHIFT)
496 #define ID_AA64PFR0_FP_HP (UL(0x1) << ID_AA64PFR0_FP_SHIFT)
497 #define ID_AA64PFR0_FP_NONE (UL(0xf) << ID_AA64PFR0_FP_SHIFT)
498 #define ID_AA64PFR0_AdvSIMD_SHIFT 20
499 #define ID_AA64PFR0_AdvSIMD_MASK (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
500 #define ID_AA64PFR0_AdvSIMD_VAL(x) ((x) & ID_AA64PFR0_AdvSIMD_MASK)
501 #define ID_AA64PFR0_AdvSIMD_IMPL (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT)
502 #define ID_AA64PFR0_AdvSIMD_HP (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT)
503 #define ID_AA64PFR0_AdvSIMD_NONE (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
504 #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */
505 #define ID_AA64PFR0_GIC_SHIFT 24
506 #define ID_AA64PFR0_GIC_MASK (UL(0xf) << ID_AA64PFR0_GIC_SHIFT)
507 #define ID_AA64PFR0_GIC_VAL(x) ((x) & ID_AA64PFR0_GIC_MASK)
508 #define ID_AA64PFR0_GIC_CPUIF_NONE (UL(0x0) << ID_AA64PFR0_GIC_SHIFT)
509 #define ID_AA64PFR0_GIC_CPUIF_EN (UL(0x1) << ID_AA64PFR0_GIC_SHIFT)
510 #define ID_AA64PFR0_RAS_SHIFT 28
511 #define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT)
512 #define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK)
513 #define ID_AA64PFR0_RAS_NONE (UL(0x0) << ID_AA64PFR0_RAS_SHIFT)
514 #define ID_AA64PFR0_RAS_V1 (UL(0x1) << ID_AA64PFR0_RAS_SHIFT)
515 #define ID_AA64PFR0_SVE_SHIFT 32
516 #define ID_AA64PFR0_SVE_MASK (UL(0xf) << ID_AA64PFR0_SVE_SHIFT)
517 #define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK)
518 #define ID_AA64PFR0_SVE_NONE (UL(0x0) << ID_AA64PFR0_SVE_SHIFT)
519 #define ID_AA64PFR0_SVE_IMPL (UL(0x1) << ID_AA64PFR0_SVE_SHIFT)
521 /* MAIR_EL1 - Memory Attribute Indirection Register */
522 #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))
523 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
524 #define MAIR_DEVICE_nGnRnE 0x00
525 #define MAIR_NORMAL_NC 0x44
526 #define MAIR_NORMAL_WT 0xbb
527 #define MAIR_NORMAL_WB 0xff
529 /* PAR_EL1 - Physical Address Register */
530 #define PAR_F_SHIFT 0
531 #define PAR_F (0x1 << PAR_F_SHIFT)
532 #define PAR_SUCCESS(x) (((x) & PAR_F) == 0)
533 /* When PAR_F == 0 (success) */
534 #define PAR_SH_SHIFT 7
535 #define PAR_SH_MASK (0x3 << PAR_SH_SHIFT)
536 #define PAR_NS_SHIFT 9
537 #define PAR_NS_MASK (0x3 << PAR_NS_SHIFT)
538 #define PAR_PA_SHIFT 12
539 #define PAR_PA_MASK 0x0000fffffffff000
540 #define PAR_ATTR_SHIFT 56
541 #define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT)
542 /* When PAR_F == 1 (aborted) */
543 #define PAR_FST_SHIFT 1
544 #define PAR_FST_MASK (0x3f << PAR_FST_SHIFT)
545 #define PAR_PTW_SHIFT 8
546 #define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT)
547 #define PAR_S_SHIFT 9
548 #define PAR_S_MASK (0x1 << PAR_S_SHIFT)
550 /* SCTLR_EL1 - System Control Register */
551 #define SCTLR_RES0 0xc8222440 /* Reserved ARMv8.0, write 0 */
552 #define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */
554 #define SCTLR_M 0x00000001
555 #define SCTLR_A 0x00000002
556 #define SCTLR_C 0x00000004
557 #define SCTLR_SA 0x00000008
558 #define SCTLR_SA0 0x00000010
559 #define SCTLR_CP15BEN 0x00000020
560 /* Bit 6 is reserved */
561 #define SCTLR_ITD 0x00000080
562 #define SCTLR_SED 0x00000100
563 #define SCTLR_UMA 0x00000200
564 /* Bit 10 is reserved */
565 /* Bit 11 is reserved */
566 #define SCTLR_I 0x00001000
567 #define SCTLR_EnDB 0x00002000 /* ARMv8.3 */
568 #define SCTLR_DZE 0x00004000
569 #define SCTLR_UCT 0x00008000
570 #define SCTLR_nTWI 0x00010000
571 /* Bit 17 is reserved */
572 #define SCTLR_nTWE 0x00040000
573 #define SCTLR_WXN 0x00080000
574 /* Bit 20 is reserved */
575 #define SCTLR_IESB 0x00200000 /* ARMv8.2 */
576 /* Bit 22 is reserved */
577 #define SCTLR_SPAN 0x00800000 /* ARMv8.1 */
578 #define SCTLR_EOE 0x01000000
579 #define SCTLR_EE 0x02000000
580 #define SCTLR_UCI 0x04000000
581 #define SCTLR_EnDA 0x08000000 /* ARMv8.3 */
582 #define SCTLR_nTLSMD 0x10000000 /* ARMv8.2 */
583 #define SCTLR_LSMAOE 0x20000000 /* ARMv8.2 */
584 #define SCTLR_EnIB 0x40000000 /* ARMv8.3 */
585 #define SCTLR_EnIA 0x80000000 /* ARMv8.3 */
589 * When the exception is taken in AArch64:
590 * M[3:2] is the exception level
592 * M[0] is the SP select:
596 #define PSR_M_EL0t 0x00000000
597 #define PSR_M_EL1t 0x00000004
598 #define PSR_M_EL1h 0x00000005
599 #define PSR_M_EL2t 0x00000008
600 #define PSR_M_EL2h 0x00000009
601 #define PSR_M_64 0x00000000
602 #define PSR_M_32 0x00000010
603 #define PSR_M_MASK 0x0000000f
605 #define PSR_T 0x00000020
607 #define PSR_AARCH32 0x00000010
608 #define PSR_F 0x00000040
609 #define PSR_I 0x00000080
610 #define PSR_A 0x00000100
611 #define PSR_D 0x00000200
612 #define PSR_DAIF (PSR_D | PSR_A | PSR_I | PSR_F)
613 #define PSR_IL 0x00100000
614 #define PSR_SS 0x00200000
615 #define PSR_V 0x10000000
616 #define PSR_C 0x20000000
617 #define PSR_Z 0x40000000
618 #define PSR_N 0x80000000
619 #define PSR_FLAGS 0xf0000000
621 /* TCR_EL1 - Translation Control Register */
622 #define TCR_HD_SHIFT 40
623 #define TCR_HD (0x1UL << TCR_HD_SHIFT)
624 #define TCR_HA_SHIFT 39
625 #define TCR_HA (0x1UL << TCR_HA_SHIFT)
627 #define TCR_ASID_SHIFT 36
628 #define TCR_ASID_WIDTH 1
629 #define TCR_ASID_16 (0x1UL << TCR_ASID_SHIFT)
631 #define TCR_IPS_SHIFT 32
632 #define TCR_IPS_WIDTH 3
633 #define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT)
634 #define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT)
635 #define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT)
636 #define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT)
637 #define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT)
638 #define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT)
640 #define TCR_TG1_SHIFT 30
641 #define TCR_TG1_16K (1 << TCR_TG1_SHIFT)
642 #define TCR_TG1_4K (2 << TCR_TG1_SHIFT)
643 #define TCR_TG1_64K (3 << TCR_TG1_SHIFT)
645 #define TCR_SH1_SHIFT 28
646 #define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT)
647 #define TCR_ORGN1_SHIFT 26
648 #define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT)
649 #define TCR_IRGN1_SHIFT 24
650 #define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT)
651 #define TCR_A1_SHIFT 22
652 #define TCR_A1 (0x1UL << TCR_A1_SHIFT)
653 #define TCR_SH0_SHIFT 12
654 #define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT)
655 #define TCR_ORGN0_SHIFT 10
656 #define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT)
657 #define TCR_IRGN0_SHIFT 8
658 #define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT)
660 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
661 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
664 #define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS)
666 #define TCR_SMP_ATTRS 0
669 #define TCR_T1SZ_SHIFT 16
670 #define TCR_T0SZ_SHIFT 0
671 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT)
672 #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT)
673 #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x))
675 /* Saved Program Status Register */
676 #define DBG_SPSR_SS (0x1 << 21)
678 /* Monitor Debug System Control Register */
679 #define DBG_MDSCR_SS (0x1 << 0)
680 #define DBG_MDSCR_KDE (0x1 << 13)
681 #define DBG_MDSCR_MDE (0x1 << 15)
683 /* Perfomance Monitoring Counters */
684 #define PMCR_E (1 << 0) /* Enable all counters */
685 #define PMCR_P (1 << 1) /* Reset all counters */
686 #define PMCR_C (1 << 2) /* Clock counter reset */
687 #define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */
688 #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */
689 #define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
690 #define PMCR_LC (1 << 6) /* Long cycle count enable */
691 #define PMCR_IMP_SHIFT 24 /* Implementer code */
692 #define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT)
693 #define PMCR_IDCODE_SHIFT 16 /* Identification code */
694 #define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT)
695 #define PMCR_IDCODE_CORTEX_A57 0x01
696 #define PMCR_IDCODE_CORTEX_A72 0x02
697 #define PMCR_IDCODE_CORTEX_A53 0x03
698 #define PMCR_N_SHIFT 11 /* Number of counters implemented */
699 #define PMCR_N_MASK (0x1f << PMCR_N_SHIFT)
701 #endif /* !_MACHINE_ARMREG_H_ */