2 * Copyright (c) 2013 Andrew Turner <andrew@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _MACHINE_ATOMIC_H_
30 #define _MACHINE_ATOMIC_H_
32 #define isb() __asm __volatile("isb" : : : "memory")
35 * Options for DMB and DSB:
36 * oshld Outer Shareable, load
37 * oshst Outer Shareable, store
38 * osh Outer Shareable, all
39 * nshld Non-shareable, load
40 * nshst Non-shareable, store
41 * nsh Non-shareable, all
42 * ishld Inner Shareable, load
43 * ishst Inner Shareable, store
44 * ish Inner Shareable, all
45 * ld Full system, load
46 * st Full system, store
49 #define dsb(opt) __asm __volatile("dsb " __STRING(opt) : : : "memory")
50 #define dmb(opt) __asm __volatile("dmb " __STRING(opt) : : : "memory")
52 #define mb() dmb(sy) /* Full system memory barrier all */
53 #define wmb() dmb(st) /* Full system memory barrier store */
54 #define rmb() dmb(ld) /* Full system memory barrier load */
56 #define ATOMIC_OP(op, asm_op, bar, a, l) \
57 static __inline void \
58 atomic_##op##_##bar##32(volatile uint32_t *p, uint32_t val) \
64 "1: ld"#a"xr %w0, [%2] \n" \
65 " "#asm_op" %w0, %w0, %w3 \n" \
66 " st"#l"xr %w1, %w0, [%2] \n" \
68 : "=&r"(tmp), "=&r"(res) \
69 : "r" (p), "r" (val) \
74 static __inline void \
75 atomic_##op##_##bar##64(volatile uint64_t *p, uint64_t val) \
81 "1: ld"#a"xr %0, [%2] \n" \
82 " "#asm_op" %0, %0, %3 \n" \
83 " st"#l"xr %w1, %0, [%2] \n" \
85 : "=&r"(tmp), "=&r"(res) \
86 : "r" (p), "r" (val) \
91 #define ATOMIC(op, asm_op) \
92 ATOMIC_OP(op, asm_op, , , ) \
93 ATOMIC_OP(op, asm_op, acq_, a, ) \
94 ATOMIC_OP(op, asm_op, rel_, , l) \
101 #define ATOMIC_FCMPSET(bar, a, l) \
102 static __inline int \
103 atomic_fcmpset_##bar##32(volatile uint32_t *p, uint32_t *cmpval, \
107 uint32_t _cmpval = *cmpval; \
111 "1: mov %w1, #1 \n" \
112 " ld"#a"xr %w0, [%2] \n" \
115 " st"#l"xr %w1, %w4, [%2] \n" \
117 : "=&r"(tmp), "=&r"(res) \
118 : "r" (p), "r" (_cmpval), "r" (newval) \
126 static __inline int \
127 atomic_fcmpset_##bar##64(volatile uint64_t *p, uint64_t *cmpval, \
131 uint64_t _cmpval = *cmpval; \
135 "1: mov %w1, #1 \n" \
136 " ld"#a"xr %0, [%2] \n" \
139 " st"#l"xr %w1, %4, [%2] \n" \
141 : "=&r"(tmp), "=&r"(res) \
142 : "r" (p), "r" (_cmpval), "r" (newval) \
150 ATOMIC_FCMPSET( , , )
151 ATOMIC_FCMPSET(acq_, a, )
152 ATOMIC_FCMPSET(rel_, ,l)
154 #undef ATOMIC_FCMPSET
156 #define ATOMIC_CMPSET(bar, a, l) \
157 static __inline int \
158 atomic_cmpset_##bar##32(volatile uint32_t *p, uint32_t cmpval, \
165 "1: mov %w1, #1 \n" \
166 " ld"#a"xr %w0, [%2] \n" \
169 " st"#l"xr %w1, %w4, [%2] \n" \
172 : "=&r"(tmp), "=&r"(res) \
173 : "r" (p), "r" (cmpval), "r" (newval) \
180 static __inline int \
181 atomic_cmpset_##bar##64(volatile uint64_t *p, uint64_t cmpval, \
188 "1: mov %w1, #1 \n" \
189 " ld"#a"xr %0, [%2] \n" \
192 " st"#l"xr %w1, %4, [%2] \n" \
195 : "=&r"(tmp), "=&r"(res) \
196 : "r" (p), "r" (cmpval), "r" (newval) \
204 ATOMIC_CMPSET(acq_, a, )
205 ATOMIC_CMPSET(rel_, ,l)
207 static __inline uint32_t
208 atomic_fetchadd_32(volatile uint32_t *p, uint32_t val)
214 "1: ldxr %w2, [%3] \n"
215 " add %w0, %w2, %w4 \n"
216 " stxr %w1, %w0, [%3] \n"
218 : "=&r"(tmp), "=&r"(res), "=&r"(ret)
226 static __inline uint64_t
227 atomic_fetchadd_64(volatile uint64_t *p, uint64_t val)
233 "1: ldxr %2, [%3] \n"
235 " stxr %w1, %0, [%3] \n"
237 : "=&r"(tmp), "=&r"(res), "=&r"(ret)
245 static __inline uint32_t
246 atomic_readandclear_32(volatile uint32_t *p)
252 "1: ldxr %w1, [%2] \n"
253 " stxr %w0, wzr, [%2] \n"
255 : "=&r"(res), "=&r"(ret)
263 static __inline uint64_t
264 atomic_readandclear_64(volatile uint64_t *p)
270 "1: ldxr %1, [%2] \n"
271 " stxr %w0, xzr, [%2] \n"
273 : "=&r"(res), "=&r"(ret)
281 static __inline uint32_t
282 atomic_swap_32(volatile uint32_t *p, uint32_t val)
288 "1: ldxr %w0, [%2] \n"
289 " stxr %w1, %w3, [%2] \n"
291 : "=&r"(ret), "=&r"(res)
299 static __inline uint64_t
300 atomic_swap_64(volatile uint64_t *p, uint64_t val)
306 "1: ldxr %0, [%2] \n"
307 " stxr %w1, %3, [%2] \n"
309 : "=&r"(ret), "=&r"(res)
317 static __inline uint32_t
318 atomic_load_acq_32(volatile uint32_t *p)
331 static __inline uint64_t
332 atomic_load_acq_64(volatile uint64_t *p)
346 atomic_store_rel_32(volatile uint32_t *p, uint32_t val)
357 atomic_store_rel_64(volatile uint64_t *p, uint64_t val)
368 #define atomic_add_int atomic_add_32
369 #define atomic_fcmpset_int atomic_fcmpset_32
370 #define atomic_clear_int atomic_clear_32
371 #define atomic_cmpset_int atomic_cmpset_32
372 #define atomic_fetchadd_int atomic_fetchadd_32
373 #define atomic_readandclear_int atomic_readandclear_32
374 #define atomic_set_int atomic_set_32
375 #define atomic_swap_int atomic_swap_32
376 #define atomic_subtract_int atomic_subtract_32
378 #define atomic_add_acq_int atomic_add_acq_32
379 #define atomic_fcmpset_acq_int atomic_fcmpset_acq_32
380 #define atomic_clear_acq_int atomic_clear_acq_32
381 #define atomic_cmpset_acq_int atomic_cmpset_acq_32
382 #define atomic_load_acq_int atomic_load_acq_32
383 #define atomic_set_acq_int atomic_set_acq_32
384 #define atomic_subtract_acq_int atomic_subtract_acq_32
386 #define atomic_add_rel_int atomic_add_rel_32
387 #define atomic_fcmpset_rel_int atomic_fcmpset_rel_32
388 #define atomic_clear_rel_int atomic_add_rel_32
389 #define atomic_cmpset_rel_int atomic_cmpset_rel_32
390 #define atomic_set_rel_int atomic_set_rel_32
391 #define atomic_subtract_rel_int atomic_subtract_rel_32
392 #define atomic_store_rel_int atomic_store_rel_32
394 #define atomic_add_long atomic_add_64
395 #define atomic_fcmpset_long atomic_fcmpset_64
396 #define atomic_clear_long atomic_clear_64
397 #define atomic_cmpset_long atomic_cmpset_64
398 #define atomic_fetchadd_long atomic_fetchadd_64
399 #define atomic_readandclear_long atomic_readandclear_64
400 #define atomic_set_long atomic_set_64
401 #define atomic_swap_long atomic_swap_64
402 #define atomic_subtract_long atomic_subtract_64
404 #define atomic_add_ptr atomic_add_64
405 #define atomic_fcmpset_ptr atomic_fcmpset_64
406 #define atomic_clear_ptr atomic_clear_64
407 #define atomic_cmpset_ptr atomic_cmpset_64
408 #define atomic_fetchadd_ptr atomic_fetchadd_64
409 #define atomic_readandclear_ptr atomic_readandclear_64
410 #define atomic_set_ptr atomic_set_64
411 #define atomic_swap_ptr atomic_swap_64
412 #define atomic_subtract_ptr atomic_subtract_64
414 #define atomic_add_acq_long atomic_add_acq_64
415 #define atomic_fcmpset_acq_long atomic_fcmpset_acq_64
416 #define atomic_clear_acq_long atomic_add_acq_64
417 #define atomic_cmpset_acq_long atomic_cmpset_acq_64
418 #define atomic_load_acq_long atomic_load_acq_64
419 #define atomic_set_acq_long atomic_set_acq_64
420 #define atomic_subtract_acq_long atomic_subtract_acq_64
422 #define atomic_add_acq_ptr atomic_add_acq_64
423 #define atomic_fcmpset_acq_ptr atomic_fcmpset_acq_64
424 #define atomic_clear_acq_ptr atomic_add_acq_64
425 #define atomic_cmpset_acq_ptr atomic_cmpset_acq_64
426 #define atomic_load_acq_ptr atomic_load_acq_64
427 #define atomic_set_acq_ptr atomic_set_acq_64
428 #define atomic_subtract_acq_ptr atomic_subtract_acq_64
430 #define atomic_add_rel_long atomic_add_rel_64
431 #define atomic_fcmpset_rel_long atomic_fcmpset_rel_64
432 #define atomic_clear_rel_long atomic_clear_rel_64
433 #define atomic_cmpset_rel_long atomic_cmpset_rel_64
434 #define atomic_set_rel_long atomic_set_rel_64
435 #define atomic_subtract_rel_long atomic_subtract_rel_64
436 #define atomic_store_rel_long atomic_store_rel_64
438 #define atomic_add_rel_ptr atomic_add_rel_64
439 #define atomic_fcmpset_rel_ptr atomic_fcmpset_rel_64
440 #define atomic_clear_rel_ptr atomic_clear_rel_64
441 #define atomic_cmpset_rel_ptr atomic_cmpset_rel_64
442 #define atomic_set_rel_ptr atomic_set_rel_64
443 #define atomic_subtract_rel_ptr atomic_subtract_rel_64
444 #define atomic_store_rel_ptr atomic_store_rel_64
447 atomic_thread_fence_acq(void)
454 atomic_thread_fence_rel(void)
461 atomic_thread_fence_acq_rel(void)
468 atomic_thread_fence_seq_cst(void)
474 #endif /* _MACHINE_ATOMIC_H_ */