2 * Copyright (c) 2013 Andrew Turner <andrew@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _MACHINE_ATOMIC_H_
30 #define _MACHINE_ATOMIC_H_
32 #define isb() __asm __volatile("isb" : : : "memory")
35 * Options for DMB and DSB:
36 * oshld Outer Shareable, load
37 * oshst Outer Shareable, store
38 * osh Outer Shareable, all
39 * nshld Non-shareable, load
40 * nshst Non-shareable, store
41 * nsh Non-shareable, all
42 * ishld Inner Shareable, load
43 * ishst Inner Shareable, store
44 * ish Inner Shareable, all
45 * ld Full system, load
46 * st Full system, store
49 #define dsb(opt) __asm __volatile("dsb " __STRING(opt) : : : "memory")
50 #define dmb(opt) __asm __volatile("dmb " __STRING(opt) : : : "memory")
52 #define mb() dmb(sy) /* Full system memory barrier all */
53 #define wmb() dmb(st) /* Full system memory barrier store */
54 #define rmb() dmb(ld) /* Full system memory barrier load */
56 #define ATOMIC_OP(op, asm_op, bar, a, l) \
57 static __inline void \
58 atomic_##op##_##bar##32(volatile uint32_t *p, uint32_t val) \
64 "1: ld"#a"xr %w0, [%2] \n" \
65 " "#asm_op" %w0, %w0, %w3 \n" \
66 " st"#l"xr %w1, %w0, [%2] \n" \
68 : "=&r"(tmp), "=&r"(res) \
69 : "r" (p), "r" (val) \
74 static __inline void \
75 atomic_##op##_##bar##64(volatile uint64_t *p, uint64_t val) \
81 "1: ld"#a"xr %0, [%2] \n" \
82 " "#asm_op" %0, %0, %3 \n" \
83 " st"#l"xr %w1, %0, [%2] \n" \
85 : "=&r"(tmp), "=&r"(res) \
86 : "r" (p), "r" (val) \
91 #define ATOMIC(op, asm_op) \
92 ATOMIC_OP(op, asm_op, , , ) \
93 ATOMIC_OP(op, asm_op, acq_, a, ) \
94 ATOMIC_OP(op, asm_op, rel_, , l) \
101 #define ATOMIC_CMPSET(bar, a, l) \
102 static __inline int \
103 atomic_cmpset_##bar##32(volatile uint32_t *p, uint32_t cmpval, \
110 "1: mov %w1, #1 \n" \
111 " ld"#a"xr %w0, [%2] \n" \
114 " st"#l"xr %w1, %w4, [%2] \n" \
117 : "=&r"(tmp), "=&r"(res) \
118 : "r" (p), "r" (cmpval), "r" (newval) \
125 static __inline int \
126 atomic_cmpset_##bar##64(volatile uint64_t *p, uint64_t cmpval, \
133 "1: mov %w1, #1 \n" \
134 " ld"#a"xr %0, [%2] \n" \
137 " st"#l"xr %w1, %4, [%2] \n" \
140 : "=&r"(tmp), "=&r"(res) \
141 : "r" (p), "r" (cmpval), "r" (newval) \
149 ATOMIC_CMPSET(acq_, a, )
150 ATOMIC_CMPSET(rel_, ,l)
152 static __inline uint32_t
153 atomic_fetchadd_32(volatile uint32_t *p, uint32_t val)
159 "1: ldxr %w2, [%3] \n"
160 " add %w0, %w2, %w4 \n"
161 " stxr %w1, %w0, [%3] \n"
163 : "=&r"(tmp), "=&r"(res), "=&r"(ret)
171 static __inline uint64_t
172 atomic_fetchadd_64(volatile uint64_t *p, uint64_t val)
178 "1: ldxr %2, [%3] \n"
180 " stxr %w1, %0, [%3] \n"
182 : "=&r"(tmp), "=&r"(res), "=&r"(ret)
190 static __inline uint32_t
191 atomic_readandclear_32(volatile uint32_t *p)
197 "1: ldxr %w1, [%2] \n"
198 " stxr %w0, wzr, [%2] \n"
200 : "=&r"(res), "=&r"(ret)
208 static __inline uint64_t
209 atomic_readandclear_64(volatile uint64_t *p)
215 "1: ldxr %1, [%2] \n"
216 " stxr %w0, xzr, [%2] \n"
218 : "=&r"(res), "=&r"(ret)
226 static __inline uint32_t
227 atomic_swap_32(volatile uint32_t *p, uint32_t val)
233 "1: ldxr %w0, [%2] \n"
234 " stxr %w1, %w3, [%2] \n"
236 : "=&r"(ret), "=&r"(res)
244 static __inline uint64_t
245 atomic_swap_64(volatile uint64_t *p, uint64_t val)
251 "1: ldxr %0, [%2] \n"
252 " stxr %w1, %3, [%2] \n"
254 : "=&r"(ret), "=&r"(res)
262 static __inline uint32_t
263 atomic_load_acq_32(volatile uint32_t *p)
276 static __inline uint64_t
277 atomic_load_acq_64(volatile uint64_t *p)
291 atomic_store_rel_32(volatile uint32_t *p, uint32_t val)
302 atomic_store_rel_64(volatile uint64_t *p, uint64_t val)
313 #define atomic_add_int atomic_add_32
314 #define atomic_clear_int atomic_clear_32
315 #define atomic_cmpset_int atomic_cmpset_32
316 #define atomic_fetchadd_int atomic_fetchadd_32
317 #define atomic_readandclear_int atomic_readandclear_32
318 #define atomic_set_int atomic_set_32
319 #define atomic_swap_int atomic_swap_32
320 #define atomic_subtract_int atomic_subtract_32
322 #define atomic_add_acq_int atomic_add_acq_32
323 #define atomic_clear_acq_int atomic_clear_acq_32
324 #define atomic_cmpset_acq_int atomic_cmpset_acq_32
325 #define atomic_load_acq_int atomic_load_acq_32
326 #define atomic_set_acq_int atomic_set_acq_32
327 #define atomic_subtract_acq_int atomic_subtract_acq_32
329 #define atomic_add_rel_int atomic_add_rel_32
330 #define atomic_clear_rel_int atomic_add_rel_32
331 #define atomic_cmpset_rel_int atomic_cmpset_rel_32
332 #define atomic_set_rel_int atomic_set_rel_32
333 #define atomic_subtract_rel_int atomic_subtract_rel_32
334 #define atomic_store_rel_int atomic_store_rel_32
336 #define atomic_add_long atomic_add_64
337 #define atomic_clear_long atomic_clear_64
338 #define atomic_cmpset_long atomic_cmpset_64
339 #define atomic_fetchadd_long atomic_fetchadd_64
340 #define atomic_readandclear_long atomic_readandclear_64
341 #define atomic_set_long atomic_set_64
342 #define atomic_swap_long atomic_swap_64
343 #define atomic_subtract_long atomic_subtract_64
345 #define atomic_add_ptr atomic_add_64
346 #define atomic_clear_ptr atomic_clear_64
347 #define atomic_cmpset_ptr atomic_cmpset_64
348 #define atomic_fetchadd_ptr atomic_fetchadd_64
349 #define atomic_readandclear_ptr atomic_readandclear_64
350 #define atomic_set_ptr atomic_set_64
351 #define atomic_swap_ptr atomic_swap_64
352 #define atomic_subtract_ptr atomic_subtract_64
354 #define atomic_add_acq_long atomic_add_acq_64
355 #define atomic_clear_acq_long atomic_add_acq_64
356 #define atomic_cmpset_acq_long atomic_cmpset_acq_64
357 #define atomic_load_acq_long atomic_load_acq_64
358 #define atomic_set_acq_long atomic_set_acq_64
359 #define atomic_subtract_acq_long atomic_subtract_acq_64
361 #define atomic_add_acq_ptr atomic_add_acq_64
362 #define atomic_clear_acq_ptr atomic_add_acq_64
363 #define atomic_cmpset_acq_ptr atomic_cmpset_acq_64
364 #define atomic_load_acq_ptr atomic_load_acq_64
365 #define atomic_set_acq_ptr atomic_set_acq_64
366 #define atomic_subtract_acq_ptr atomic_subtract_acq_64
368 #define atomic_add_rel_long atomic_add_rel_64
369 #define atomic_clear_rel_long atomic_clear_rel_64
370 #define atomic_cmpset_rel_long atomic_cmpset_rel_64
371 #define atomic_set_rel_long atomic_set_rel_64
372 #define atomic_subtract_rel_long atomic_subtract_rel_64
373 #define atomic_store_rel_long atomic_store_rel_64
375 #define atomic_add_rel_ptr atomic_add_rel_64
376 #define atomic_clear_rel_ptr atomic_clear_rel_64
377 #define atomic_cmpset_rel_ptr atomic_cmpset_rel_64
378 #define atomic_set_rel_ptr atomic_set_rel_64
379 #define atomic_subtract_rel_ptr atomic_subtract_rel_64
380 #define atomic_store_rel_ptr atomic_store_rel_64
383 atomic_thread_fence_acq(void)
390 atomic_thread_fence_rel(void)
397 atomic_thread_fence_acq_rel(void)
404 atomic_thread_fence_seq_cst(void)
410 #endif /* _MACHINE_ATOMIC_H_ */