2 * Copyright (c) 2014 Andrew Turner
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <arm/cpufunc.h>
31 #ifndef _MACHINE_CPUFUNC_H_
32 #define _MACHINE_CPUFUNC_H_
42 #include <machine/armreg.h>
44 void pan_enable(void);
46 static __inline register_t
53 "msr daifset, #(" __XSTRING(DAIF_D) ") \n"
63 __asm __volatile("msr daifclr, #(" __XSTRING(DAIF_D) ")");
66 static __inline register_t
69 /* DAIF is a 32-bit register */
74 "msr daifset, #(" __XSTRING(DAIF_INTR) ") \n"
81 intr_restore(register_t s)
84 WRITE_SPECIALREG(daif, s);
91 __asm __volatile("msr daifclr, #(" __XSTRING(DAIF_INTR) ")");
98 __asm __volatile("msr daifclr, #(" __XSTRING(DAIF_A) ")");
101 static __inline register_t
106 midr = READ_SPECIALREG(midr_el1);
111 static __inline register_t
116 mpidr = READ_SPECIALREG(mpidr_el1);
126 * Ensure compiler barrier, otherwise the monitor clear might
127 * occur too late for us ?
129 __asm __volatile("clrex" : : : "memory");
133 set_ttbr0(uint64_t ttbr0)
137 "msr ttbr0_el1, %0 \n"
144 invalidate_icache(void)
154 invalidate_local_icache(void)
163 extern bool icache_aliasing;
164 extern bool icache_vmid;
166 extern int64_t dcache_line_size;
167 extern int64_t icache_line_size;
168 extern int64_t idcache_line_size;
169 extern int64_t dczva_line_size;
171 #define cpu_nullop() arm64_nullop()
172 #define cpufunc_nullop() arm64_nullop()
174 #define cpu_tlb_flushID() arm64_tlb_flushID()
176 #define cpu_dcache_wbinv_range(a, s) arm64_dcache_wbinv_range((a), (s))
177 #define cpu_dcache_inv_range(a, s) arm64_dcache_inv_range((a), (s))
178 #define cpu_dcache_wb_range(a, s) arm64_dcache_wb_range((a), (s))
180 extern void (*arm64_icache_sync_range)(vm_offset_t, vm_size_t);
182 #define cpu_icache_sync_range(a, s) arm64_icache_sync_range((a), (s))
183 #define cpu_icache_sync_range_checked(a, s) arm64_icache_sync_range_checked((a), (s))
185 void arm64_nullop(void);
186 void arm64_tlb_flushID(void);
187 void arm64_dic_idc_icache_sync_range(vm_offset_t, vm_size_t);
188 void arm64_idc_aliasing_icache_sync_range(vm_offset_t, vm_size_t);
189 void arm64_aliasing_icache_sync_range(vm_offset_t, vm_size_t);
190 int arm64_icache_sync_range_checked(vm_offset_t, vm_size_t);
191 void arm64_dcache_wbinv_range(vm_offset_t, vm_size_t);
192 void arm64_dcache_inv_range(vm_offset_t, vm_size_t);
193 void arm64_dcache_wb_range(vm_offset_t, vm_size_t);
194 bool arm64_get_writable_addr(vm_offset_t, vm_offset_t *);
197 #endif /* _MACHINE_CPUFUNC_H_ */
199 #endif /* !__arm__ */