2 * Copyright (c) 2014 Andrew Turner
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _MACHINE_CPUFUNC_H_
30 #define _MACHINE_CPUFUNC_H_
34 #include <machine/armreg.h>
36 void pan_enable(void);
45 static __inline register_t
62 __asm __volatile("msr daifclr, #8");
65 static __inline register_t
68 /* DAIF is a 32-bit register */
80 intr_restore(register_t s)
83 WRITE_SPECIALREG(daif, s);
90 __asm __volatile("msr daifclr, #2");
93 static __inline register_t
98 midr = READ_SPECIALREG(midr_el1);
103 static __inline register_t
108 mpidr = READ_SPECIALREG(mpidr_el1);
118 * Ensure compiler barrier, otherwise the monitor clear might
119 * occur too late for us ?
121 __asm __volatile("clrex" : : : "memory");
124 extern int64_t dcache_line_size;
125 extern int64_t icache_line_size;
126 extern int64_t idcache_line_size;
127 extern int64_t dczva_line_size;
129 #define cpu_nullop() arm64_nullop()
130 #define cpufunc_nullop() arm64_nullop()
131 #define cpu_setttb(a) arm64_setttb(a)
133 #define cpu_tlb_flushID() arm64_tlb_flushID()
135 #define cpu_dcache_wbinv_range(a, s) arm64_dcache_wbinv_range((a), (s))
136 #define cpu_dcache_inv_range(a, s) arm64_dcache_inv_range((a), (s))
137 #define cpu_dcache_wb_range(a, s) arm64_dcache_wb_range((a), (s))
139 #define cpu_idcache_wbinv_range(a, s) arm64_idcache_wbinv_range((a), (s))
140 #define cpu_icache_sync_range(a, s) arm64_icache_sync_range((a), (s))
142 void arm64_nullop(void);
143 void arm64_setttb(vm_offset_t);
144 void arm64_tlb_flushID(void);
145 void arm64_tlb_flushID_SE(vm_offset_t);
146 void arm64_icache_sync_range(vm_offset_t, vm_size_t);
147 void arm64_idcache_wbinv_range(vm_offset_t, vm_size_t);
148 void arm64_dcache_wbinv_range(vm_offset_t, vm_size_t);
149 void arm64_dcache_inv_range(vm_offset_t, vm_size_t);
150 void arm64_dcache_wb_range(vm_offset_t, vm_size_t);
153 #endif /* _MACHINE_CPUFUNC_H_ */