2 * Copyright (c) 2014 Andrew Turner
3 * Copyright (c) 2014-2015 The FreeBSD Foundation
6 * This software was developed by Andrew Turner under
7 * sponsorship from the FreeBSD Foundation.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef _ARM64_IOMMU_IOMMU_PTE_H_
32 #define _ARM64_IOMMU_IOMMU_PTE_H_
34 /* Level 0 table, 512GiB per entry */
35 #define IOMMU_L0_SHIFT 39
36 #define IOMMU_L0_INVAL 0x0 /* An invalid address */
37 /* 0x1 Level 0 doesn't support block translation */
38 /* 0x2 also marks an invalid address */
39 #define IOMMU_L0_TABLE 0x3 /* A next-level table */
41 /* Level 1 table, 1GiB per entry */
42 #define IOMMU_L1_SHIFT 30
43 #define IOMMU_L1_INVAL IOMMU_L0_INVAL
44 #define IOMMU_L1_BLOCK 0x1
45 #define IOMMU_L1_TABLE IOMMU_L0_TABLE
47 /* Level 2 table, 2MiB per entry */
48 #define IOMMU_L2_SHIFT 21
49 #define IOMMU_L2_INVAL IOMMU_L1_INVAL
50 #define IOMMU_L2_BLOCK IOMMU_L1_BLOCK
51 #define IOMMU_L2_TABLE IOMMU_L1_TABLE
53 /* Level 3 table, 4KiB per entry */
54 #define IOMMU_L3_SHIFT 12
55 #define IOMMU_L3_SIZE (1 << IOMMU_L3_SHIFT)
56 #define IOMMU_L3_SHIFT 12
57 #define IOMMU_L3_INVAL 0x0
59 /* 0x2 also marks an invalid address */
60 #define IOMMU_L3_PAGE 0x3
61 #define IOMMU_L3_BLOCK IOMMU_L2_BLOCK /* Mali GPU only. */
63 #define IOMMU_L0_ENTRIES_SHIFT 9
64 #define IOMMU_L0_ENTRIES (1 << IOMMU_L0_ENTRIES_SHIFT)
65 #define IOMMU_L0_ADDR_MASK (IOMMU_L0_ENTRIES - 1)
67 #define IOMMU_Ln_ENTRIES_SHIFT 9
68 #define IOMMU_Ln_ENTRIES (1 << IOMMU_Ln_ENTRIES_SHIFT)
69 #define IOMMU_Ln_ADDR_MASK (IOMMU_Ln_ENTRIES - 1)
70 #define IOMMU_Ln_TABLE_MASK ((1 << 12) - 1)
72 #endif /* !_ARM64_IOMMU_IOMMU_PTE_H_ */