2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2019-2020 Ruslan Bukin <br@bsdpad.com>
6 * This software was developed by SRI International and the University of
7 * Cambridge Computer Laboratory (Department of Computer Science and
8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
9 * DARPA SSITH research programme.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #ifndef _ARM64_IOMMU_SMMUVAR_H_
36 #define _ARM64_IOMMU_SMMUVAR_H_
38 #define SMMU_DEVSTR "ARM System Memory Management Unit"
39 #define SMMU_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
40 #define SMMU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
42 DECLARE_CLASS(smmu_driver);
45 struct iommu_unit iommu;
46 LIST_HEAD(, smmu_domain) domain_list;
47 LIST_ENTRY(smmu_unit) next;
53 struct iommu_domain iodom;
54 LIST_HEAD(, smmu_ctx) ctx_list;
55 LIST_ENTRY(smmu_domain) next;
63 struct iommu_ctx ioctx;
64 struct smmu_domain *domain;
65 LIST_ENTRY(smmu_ctx) next;
73 struct smmu_queue_local_copy {
90 struct smmu_queue_local_copy lc;
99 struct smmu_cmdq_entry {
133 uint32_t num_l1_entries;
139 struct resource *res[4];
140 void *intr_cookie[3];
141 uint32_t ias; /* Intermediate Physical Address */
142 uint32_t oas; /* Physical Address */
149 #define SMMU_FEATURE_2_LVL_STREAM_TABLE (1 << 0)
150 #define SMMU_FEATURE_2_LVL_CD (1 << 1)
151 #define SMMU_FEATURE_TT_LE (1 << 2)
152 #define SMMU_FEATURE_TT_BE (1 << 3)
153 #define SMMU_FEATURE_SEV (1 << 4)
154 #define SMMU_FEATURE_MSI (1 << 5)
155 #define SMMU_FEATURE_HYP (1 << 6)
156 #define SMMU_FEATURE_ATS (1 << 7)
157 #define SMMU_FEATURE_PRI (1 << 8)
158 #define SMMU_FEATURE_STALL_FORCE (1 << 9)
159 #define SMMU_FEATURE_STALL (1 << 10)
160 #define SMMU_FEATURE_S1P (1 << 11)
161 #define SMMU_FEATURE_S2P (1 << 12)
162 #define SMMU_FEATURE_VAX (1 << 13)
163 #define SMMU_FEATURE_COHERENCY (1 << 14)
164 #define SMMU_FEATURE_RANGE_INV (1 << 15)
165 struct smmu_queue cmdq;
166 struct smmu_queue evtq;
167 struct smmu_queue priq;
168 struct smmu_strtab strtab;
173 struct mtx asid_set_mutex;
174 struct smmu_unit unit;
178 MALLOC_DECLARE(M_SMMU);
181 int smmu_attach(device_t dev);
182 int smmu_detach(device_t dev);
184 struct smmu_ctx *smmu_ctx_lookup_by_sid(device_t dev, u_int sid);
185 bool smmu_quirks_check(device_t dev, u_int sid, uint8_t event_id,
186 uintptr_t input_addr);
188 #endif /* _ARM64_IOMMU_SMMUVAR_H_ */