sys/arm64/nvidia/tegra210/tegra210_car.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #ifndef _TEGRA210_CAR_
  29 #define _TEGRA210_CAR_
  30
  31 #include "clkdev_if.h"
  32
  33 #define RD4(sc, reg, val)       CLKDEV_READ_4((sc)->clkdev, reg, val)
  34 #define WR4(sc, reg, val)       CLKDEV_WRITE_4((sc)->clkdev, reg, val)
  35 #define MD4(sc, reg, mask, set) CLKDEV_MODIFY_4((sc)->clkdev, reg, mask, set)
  36 #define DEVICE_LOCK(sc)         CLKDEV_DEVICE_LOCK((sc)->clkdev)
  37 #define DEVICE_UNLOCK(sc)       CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
  38
  39 #define RST_SOURCE                      0x000
  40 #define RST_DEVICES_L                   0x004
  41 #define RST_DEVICES_H                   0x008
  42 #define RST_DEVICES_U                   0x00C
  43 #define CLK_OUT_ENB_L                   0x010
  44 #define CLK_OUT_ENB_H                   0x014
  45 #define CLK_OUT_ENB_U                   0x018
  46 #define SUPER_CCLK_DIVIDER              0x024
  47 #define SCLK_BURST_POLICY               0x028
  48 #define SUPER_SCLK_DIVIDER              0x02c
  49 #define CLK_SYSTEM_RATE                 0x030
  50 #define CLK_MASK_ARM                    0x044
  51 #define MISC_CLK_ENB                    0x048
  52
  53 #define OSC_CTRL                        0x050
  54  #define        OSC_CTRL_OSC_FREQ_GET(x)        (((x) >> 28) & 0x0F)
  55  #define        OSC_CTRL_PLL_REF_DIV_GET(x)     (((x) >> 26) & 0x03)
  56
  57 #define OSC_FREQ_DET_STATUS             0x05c
  58 #define PLLE_SS_CNTL                    0x068
  59 #define  PLLE_SS_CNTL_INTEGOFFSET(x)            (((x) & 0x03) << 30)
  60 #define  PLLE_SS_CNTL_SSCINCINTRV(x)            (((x) & 0x3f) << 24)
  61 #define  PLLE_SS_CNTL_SSCINC(x)                 (((x) & 0xff) << 16)
  62 #define  PLLE_SS_CNTL_SSCINVERT                 (1 << 15)
  63 #define  PLLE_SS_CNTL_SSCCENTER                 (1 << 14)
  64 #define  PLLE_SS_CNTL_SSCPDMBYP                 (1 << 13)
  65 #define  PLLE_SS_CNTL_SSCBYP                    (1 << 12)
  66 #define  PLLE_SS_CNTL_INTERP_RESET              (1 << 11)
  67 #define  PLLE_SS_CNTL_BYPASS_SS                 (1 << 10)
  68 #define  PLLE_SS_CNTL_SSCMAX(x)                 (((x) & 0x1ff) <<  0)
  69
  70 #define  PLLE_SS_CNTL_SSCINCINTRV_MASK          (0x3f << 24)
  71 #define  PLLE_SS_CNTL_SSCINCINTRV_VAL           (0x20 << 24)
  72 #define  PLLE_SS_CNTL_SSCINC_MASK               (0xff << 16)
  73 #define  PLLE_SS_CNTL_SSCINC_VAL                (0x1 << 16)
  74 #define  PLLE_SS_CNTL_SSCMAX_MASK               0x1ff
  75 #define  PLLE_SS_CNTL_SSCMAX_VAL                0x25
  76 #define  PLLE_SS_CNTL_DISABLE                   (PLLE_SS_CNTL_BYPASS_SS |    \
  77                                                  PLLE_SS_CNTL_INTERP_RESET | \
  78                                                  PLLE_SS_CNTL_SSCBYP)
  79 #define  PLLE_SS_CNTL_COEFFICIENTS_MASK         (PLLE_SS_CNTL_SSCMAX_MASK |  \
  80                                                  PLLE_SS_CNTL_SSCINC_MASK |  \
  81                                                  PLLE_SS_CNTL_SSCINCINTRV_MASK)
  82 #define  PLLE_SS_CNTL_COEFFICIENTS_VAL          (PLLE_SS_CNTL_SSCMAX_VAL |   \
  83                                                  PLLE_SS_CNTL_SSCINC_VAL |   \
  84                                                  PLLE_SS_CNTL_SSCINCINTRV_VAL)
  85
  86 #define PLLE_MISC1                      0x06C
  87 #define PLLC_BASE                       0x080
  88 #define PLLC_OUT                        0x084
  89 #define PLLC_MISC_0                     0x088
  90 #define PLLC_MISC_1                     0x08c
  91 #define PLLM_BASE                       0x090
  92 #define PLLM_MISC1                      0x099
  93 #define PLLM_MISC2                      0x09c
  94 #define PLLP_BASE                       0x0a0
  95 #define PLLP_OUTA                       0x0a4
  96 #define PLLP_OUTB                       0x0a8
  97 #define PLLP_MISC                       0x0ac
  98 #define PLLA_BASE                       0x0b0
  99 #define PLLA_OUT                        0x0b4
 100 #define PLLA_MISC1                      0x0b8
 101 #define PLLA_MISC                       0x0bc
 102 #define PLLU_BASE                       0x0c0
 103 #define PLLU_OUTA                       0x0c4
 104 #define PLLU_MISC1                      0x0c8
 105 #define PLLU_MISC                       0x0cc
 106 #define PLLD_BASE                       0x0d0
 107 #define PLLD_MISC1                      0x0d8
 108 #define PLLD_MISC                       0x0dc
 109 #define PLLX_BASE                       0x0e0
 110 #define PLLX_MISC                       0x0e4
 111 #define  PLLX_MISC_LOCK_ENABLE                  (1 << 18)
 112
 113 #define PLLE_BASE                       0x0e8
 114 #define  PLLE_BASE_ENABLE                       (1U << 31)
 115 #define  PLLE_BASE_LOCK_OVERRIDE                (1 << 30)
 116
 117 #define PLLE_MISC                       0x0ec
 118 #define  PLLE_MISC_SETUP_BASE(x)                (((x) & 0xFFFF) << 16)
 119 #define  PLLE_MISC_CLKENABLE                    (1 << 15)
 120 #define  PLLE_MISC_IDDQ_SWCTL                   (1 << 14)
 121 #define  PLLE_MISC_IDDQ_OVERRIDE_VALUE          (1 << 13)
 122 #define  PLLE_MISC_IDDQ_FREQLOCK                (1 << 12)
 123 #define  PLLE_MISC_LOCK                         (1 << 11)
 124 #define  PLLE_MISC_REF_DIS                      (1 << 10)
 125 #define  PLLE_MISC_LOCK_ENABLE                  (1 <<  9)
 126 #define  PLLE_MISC_PTS                          (1 <<  8)
 127 #define  PLLE_MISC_KCP(x)                       (((x) & 0x03) << 6)
 128 #define  PLLE_MISC_VREG_BG_CTRL(x)              (((x) & 0x03) << 4)
 129 #define  PLLE_MISC_VREG_CTRL(x)                 (((x) & 0x03) << 2)
 130 #define  PLLE_MISC_KVCO                         (1 <<  0)
 131
 132 #define  PLLE_MISC_VREG_BG_CTRL_SHIFT           4
 133 #define  PLLE_MISC_VREG_BG_CTRL_MASK            (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
 134 #define  PLLE_MISC_VREG_CTRL_SHIFT              2
 135 #define  PLLE_MISC_VREG_CTRL_MASK               (2 << PLLE_MISC_VREG_CTRL_SHIFT)
 136 #define  PLLE_MISC_SETUP_BASE_SHIFT             16
 137 #define  PLLE_MISC_SETUP_BASE_MASK              (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
 138
 139 #define PLLE_SS_CNTL1                   0x0f0
 140 #define PLLE_SS_CNTL2                   0x0f4
 141 #define LVL2_CLK_GATE_OVRA              0x0f8
 142 #define LVL2_CLK_GATE_OVRB              0x0fc
 143 #define LVL2_CLK_GATE_OVRC              0x3a0   /* Misordered in TRM */
 144 #define LVL2_CLK_GATE_OVRD              0x3a4
 145 #define LVL2_CLK_GATE_OVRE              0x554
 146
 147 #define CLK_SOURCE_I2S2                 0x100
 148 #define CLK_SOURCE_I2S3                 0x104
 149 #define CLK_SOURCE_SPDIF_OUT            0x108
 150 #define CLK_SOURCE_SPDIF_IN             0x10c
 151 #define CLK_SOURCE_PWM                  0x110
 152 #define CLK_SOURCE_SPI2                 0x118
 153 #define CLK_SOURCE_SPI3                 0x11c
 154 #define CLK_SOURCE_I2C1                 0x124
 155 #define CLK_SOURCE_I2C5                 0x128
 156 #define CLK_SOURCE_SPI1                 0x134
 157 #define CLK_SOURCE_DISP1                0x138
 158 #define CLK_SOURCE_DISP2                0x13c
 159 #define CLK_SOURCE_ISP                  0x144
 160 #define CLK_SOURCE_VI                   0x148
 161 #define CLK_SOURCE_SDMMC1               0x150
 162 #define CLK_SOURCE_SDMMC2               0x154
 163 #define CLK_SOURCE_SDMMC4               0x164
 164 #define CLK_SOURCE_UARTA                0x178
 165 #define CLK_SOURCE_UARTB                0x17c
 166 #define CLK_SOURCE_HOST1X               0x180
 167 #define CLK_SOURCE_I2C2                 0x198
 168 #define CLK_SOURCE_EMC                  0x19c
 169 #define CLK_SOURCE_UARTC                0x1a0
 170 #define CLK_SOURCE_VI_SENSOR            0x1a8
 171 #define CLK_SOURCE_SPI4                 0x1b4
 172 #define CLK_SOURCE_I2C3                 0x1b8
 173 #define CLK_SOURCE_SDMMC3               0x1bc
 174 #define CLK_SOURCE_UARTD                0x1c0
 175 #define CLK_SOURCE_OWR                  0x1cc
 176 #define CLK_SOURCE_CSITE                0x1d4
 177 #define CLK_SOURCE_I2S1                 0x1d8
 178 #define CLK_SOURCE_DTV                  0x1dc
 179 #define CLK_SOURCE_TSEC                 0x1f4
 180 #define CLK_SOURCE_SPARE2               0x1f8
 181
 182 #define CLK_OUT_ENB_X                   0x280
 183 #define CLK_ENB_X_SET                   0x284
 184 #define CLK_ENB_X_CLR                   0x288
 185 #define RST_DEVICES_X                   0x28C
 186 #define RST_DEV_X_SET                   0x290
 187 #define RST_DEV_X_CLR                   0x294
 188 #define CLK_OUT_ENB_Y                   0x298
 189 #define CLK_ENB_Y_SET                   0x29c
 190 #define CLK_ENB_Y_CLR                   0x2a0
 191 #define RST_DEVICES_Y                   0x2a4
 192 #define RST_DEV_Y_SET                   0x2a8
 193 #define RST_DEV_Y_CLR                   0x2ac
 194 #define DFLL_BASE                       0x2f4
 195 #define  DFLL_BASE_DVFS_DFLL_RESET              (1 << 0)
 196
 197 #define RST_DEV_L_SET                   0x300
 198 #define RST_DEV_L_CLR                   0x304
 199 #define RST_DEV_H_SET                   0x308
 200 #define RST_DEV_H_CLR                   0x30c
 201 #define RST_DEV_U_SET                   0x310
 202 #define RST_DEV_U_CLR                   0x314
 203 #define CLK_ENB_L_SET                   0x320
 204 #define CLK_ENB_L_CLR                   0x324
 205 #define CLK_ENB_H_SET                   0x328
 206 #define CLK_ENB_H_CLR                   0x32c
 207 #define CLK_ENB_U_SET                   0x330
 208 #define CLK_ENB_U_CLR                   0x334
 209 #define CCPLEX_PG_SM_OVRD               0x33c
 210 #define CPU_CMPLX_SET                   0x340
 211 #define RST_DEVICES_V                   0x358
 212 #define RST_DEVICES_W                   0x35c
 213 #define CLK_OUT_ENB_V                   0x360
 214 #define CLK_OUT_ENB_W                   0x364
 215 #define CCLKG_BURST_POLICY              0x368
 216 #define SUPER_CCLKG_DIVIDER             0x36C
 217 #define CCLKLP_BURST_POLICY             0x370
 218 #define SUPER_CCLKLP_DIVIDER            0x374
 219 #define CLK_CPUG_CMPLX                  0x378
 220 #define CPU_SOFTRST_CTRL                0x380
 221 #define CPU_SOFTRST_CTRL1               0x384
 222 #define CPU_SOFTRST_CTRL2               0x388
 223 #define CLK_SOURCE_MSELECT              0x3b4
 224 #define CLK_SOURCE_TSENSOR              0x3b8
 225 #define CLK_SOURCE_I2S4                 0x3bc
 226 #define CLK_SOURCE_I2S5                 0x3c0
 227 #define CLK_SOURCE_I2C4                 0x3c4
 228 #define CLK_SOURCE_AHUB                 0x3d0
 229 #define CLK_SOURCE_HDA2CODEC_2X         0x3e4
 230 #define CLK_SOURCE_ACTMON               0x3e8
 231 #define CLK_SOURCE_EXTPERIPH1           0x3ec
 232 #define CLK_SOURCE_EXTPERIPH2           0x3f0
 233 #define CLK_SOURCE_EXTPERIPH3           0x3f4
 234 #define CLK_SOURCE_I2C_SLOW             0x3fc
 235
 236 #define CLK_SOURCE_SYS                  0x400
 237 #define CLK_SOURCE_ISPB                 0x404
 238 #define CLK_SOURCE_SOR1                 0x410
 239 #define CLK_SOURCE_SOR0                 0x414
 240 #define CLK_SOURCE_SATA_OOB             0x420
 241 #define CLK_SOURCE_SATA                 0x424
 242 #define CLK_SOURCE_HDA                  0x428
 243 #define RST_DEV_V_SET                   0x430
 244 #define RST_DEV_V_CLR                   0x434
 245 #define RST_DEV_W_SET                   0x438
 246 #define RST_DEV_W_CLR                   0x43c
 247 #define CLK_ENB_V_SET                   0x440
 248 #define CLK_ENB_V_CLR                   0x444
 249 #define CLK_ENB_W_SET                   0x448
 250 #define CLK_ENB_W_CLR                   0x44c
 251 #define RST_CPUG_CMPLX_SET              0x450
 252 #define RST_CPUG_CMPLX_CLR              0x454
 253 #define CLK_CPUG_CMPLX_SET              0x460
 254 #define CLK_CPUG_CMPLX_CLR              0x464
 255 #define CPU_CMPLX_STATUS                0x470
 256 #define INTSTATUS                       0x478
 257 #define INTMASK                         0x47c
 258 #define UTMIP_PLL_CFG0                  0x480
 259
 260 #define UTMIP_PLL_CFG1                  0x484
 261 #define  UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP              (1 << 17)
 262 #define  UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN            (1 << 16)
 263 #define  UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP        (1 << 15)
 264 #define  UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN      (1 << 14)
 265 #define  UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN      (1 << 12)
 266 #define  UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x)             (((x) & 0x1f) << 6)
 267 #define  UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
 268
 269 #define UTMIP_PLL_CFG2                  0x488
 270 #define  UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN                (1 << 30)
 271 #define  UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP         (1 << 25)
 272 #define  UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN       (1 << 24)
 273 #define  UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x)             (((x) & 0x3f) << 18)
 274 #define  UTMIP_PLL_CFG2_STABLE_COUNT(x)                 (((x) & 0xffff) << 6)
 275 #define  UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP         (1 << 5)
 276 #define  UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN       (1 << 4)
 277 #define  UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP         (1 << 3)
 278 #define  UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN       (1 << 2)
 279 #define  UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP         (1 << 1)
 280 #define  UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN       (1 << 0)
 281
 282 #define PLLE_AUX                        0x48c
 283 #define  PLLE_AUX_SS_SEQ_INCLUDE                        (1U << 31)
 284 #define  PLLE_AUX_REF_SEL_PLLREFE                       (1 << 28)
 285 #define  PLLE_AUX_SEQ_STATE_GET(x)                      (((x) >> 26) & 0x03)
 286 #define   PLLE_AUX_SEQ_STATE_OFF                        0
 287 #define   PLLE_AUX_SEQ_STATE_ON                         1
 288 #define   PLLE_AUX_SEQ_STATE_BUSY                       2
 289 #define  PLLE_AUX_SEQ_START_STATE                       (1 << 25)
 290 #define  PLLE_AUX_SEQ_ENABLE                            (1 << 24)
 291 #define  PLLE_AUX_SS_DLY(x)                             (((x) & 0xFF) << 16)
 292 #define  PLLE_AUX_SS_LOCK_DLY(x)                        (((x) & 0xFF) <<  8)
 293 #define  PLLE_AUX_SS_TEST_FAST_PT                       (1 <<  7)
 294 #define  PLLE_AUX_SS_SWCTL                              (1 <<  6)
 295 #define  PLLE_AUX_CONFIG_SWCTL                          (1 <<  6)
 296 #define  PLLE_AUX_ENABLE_SWCTL                          (1 <<  4)
 297 #define  PLLE_AUX_USE_LOCKDET                           (1 <<  3)
 298 #define  PLLE_AUX_REF_SRC                               (1 <<  2)
 299 #define  PLLE_AUX_PLLP_CML1_OEN                         (1 <<  1)
 300 #define  PLLE_AUX_PLLP_CML0_OEN                         (1 <<  0)
 301
 302 #define SATA_PLL_CFG0                   0x490
 303 #define SATA_PLL_CFG0_SEQ_START_STATE                   (1 << 25)
 304 #define SATA_PLL_CFG0_SEQ_ENABLE                        (1 << 24)
 305 #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ                 (1 << 13)
 306 #define SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE         (1 <<  7)
 307 #define SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE           (1 <<  6)
 308 #define SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE             (1 <<  5)
 309 #define SATA_PLL_CFG0_SEQ_IN_SWCTL                      (1 <<  4)
 310 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET                (1 <<  2)
 311 #define SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE       (1 <<  1)
 312 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL                (1 <<  0)
 313
 314 #define SATA_PLL_CFG1                   0x494
 315 #define PCIE_PLL_CFG                    0x498
 316 #define PCIE_PLL_CFG_SEQ_START_STATE                    (1 << 25)
 317 #define PCIE_PLL_CFG_SEQ_ENABLE                         (1 << 24)
 318
 319 #define PROG_AUDIO_DLY_CLK              0x49c
 320 #define AUDIO_SYNC_CLK_I2S1             0x4a0
 321 #define AUDIO_SYNC_CLK_I2S2             0x4a4
 322 #define AUDIO_SYNC_CLK_I2S3             0x4a8
 323 #define AUDIO_SYNC_CLK_I2S4             0x4ac
 324 #define AUDIO_SYNC_CLK_I2S5             0x4b0
 325 #define AUDIO_SYNC_CLK_SPDIF            0x4b4
 326 #define PLLD2_BASE                      0x4b8
 327 #define PLLD2_MISC                      0x4bc
 328 #define UTMIP_PLL_CFG3                  0x4c0
 329 #define PLLREFE_BASE                    0x4c4
 330 #define PLLREFE_MISC                    0x4c8
 331 #define PLLREFE_OUT                     0x4cc
 332 #define CPU_FINETRIM_BYP                0x4d0
 333 #define CPU_FINETRIM_SELECT             0x4d4
 334 #define CPU_FINETRIM_DR                 0x4d8
 335 #define CPU_FINETRIM_DF                 0x4dc
 336 #define CPU_FINETRIM_F                  0x4e0
 337 #define CPU_FINETRIM_R                  0x4e4
 338 #define PLLC2_BASE                      0x4e8
 339 #define PLLC2_MISC_0                    0x4ec
 340 #define PLLC2_MISC_1                    0x4f0
 341 #define PLLC2_MISC_2                    0x4f4
 342 #define PLLC2_MISC_3                    0x4f8
 343 #define PLLC3_BASE                      0x4fc
 344
 345 #define PLLC3_MISC_0                    0x500
 346 #define PLLC3_MISC_1                    0x504
 347 #define PLLC3_MISC_2                    0x508
 348 #define PLLC3_MISC_3                    0x50c
 349 #define PLLX_MISC_2                     0x514
 350 #define PLLX_MISC_2                     0x514
 351 #define  PLLX_MISC_2_DYNRAMP_STEPB(x)                   (((x) & 0xFF) << 24)
 352 #define  PLLX_MISC_2_DYNRAMP_STEPA(x)                   (((x) & 0xFF) << 16)
 353 #define  PLLX_MISC_2_NDIV_NEW(x)                        (((x) & 0xFF) <<  8)
 354 #define  PLLX_MISC_2_EN_FSTLCK                          (1 << 5)
 355 #define  PLLX_MISC_2_LOCK_OVERRIDE                      (1 << 4)
 356 #define  PLLX_MISC_2_PLL_FREQLOCK                       (1 << 3)
 357 #define  PLLX_MISC_2_DYNRAMP_DONE                       (1 << 2)
 358 #define  PLLX_MISC_2_EN_DYNRAMP                         (1 << 0)
 359
 360 #define PLLX_MISC_3                     0x518
 361
 362 #define XUSBIO_PLL_CFG0                 0x51c
 363 #define  XUSBIO_PLL_CFG0_SEQ_START_STATE                (1 << 25)
 364 #define  XUSBIO_PLL_CFG0_SEQ_ENABLE                     (1 << 24)
 365 #define  XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ              (1 << 13)
 366 #define  XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET             (1 <<  6)
 367 #define  XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL               (1 <<  2)
 368 #define  XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL             (1 <<  0)
 369
 370 #define XUSBIO_PLL_CFG1                 0x520
 371 #define PLLE_AUX1                       0x524
 372 #define PLLP_RESHIFT                    0x528
 373 #define UTMIPLL_HW_PWRDN_CFG0           0x52c
 374 #define  UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK             (1U << 31)
 375 #define  UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE          (1 << 25)
 376 #define  UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE               (1 << 24)
 377 #define  UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE          (1 << 7)
 378 #define  UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET              (1 <<  6)
 379 #define  UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE    (1 <<  5)
 380 #define  UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL             (1 <<  4)
 381 #define  UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL         (1 <<  2)
 382 #define  UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE            (1 <<  1)
 383 #define  UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL               (1 <<  0)
 384
 385 #define PLLU_HW_PWRDN_CFG0              0x530
 386 #define  PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE             (1 << 28)
 387 #define  PLLU_HW_PWRDN_CFG0_SEQ_ENABLE                  (1 << 24)
 388 #define  PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT           (1 <<  7)
 389 #define  PLLU_HW_PWRDN_CFG0_USE_LOCKDET                 (1 <<  6)
 390 #define  PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL            (1 <<  2)
 391 #define  PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL            (1 <<  0)
 392
 393 #define XUSB_PLL_CFG0                   0x534
 394 #define  XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY                 0x3ff
 395 #define  XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK               (0x3ff << 14)
 396
 397 #define CLK_CPU_MISC                    0x53c
 398 #define CLK_CPUG_MISC                   0x540
 399 #define PLLX_HW_CTRL_CFG                0x548
 400 #define PLLX_SW_RAMP_CFG                0x54c
 401 #define PLLX_HW_CTRL_STATUS             0x550
 402 #define SPARE_REG0                      0x55c
 403 #define  SPARE_REG0_MDIV_GET(x)                         (((x) >> 2) & 0x03)
 404
 405 #define AUDIO_SYNC_CLK_DMIC1            0x560
 406 #define AUDIO_SYNC_CLK_DMIC2            0x564
 407 #define PLLD2_SS_CFG                    0x570
 408 #define PLLD2_SS_CTRL1                  0x574
 409 #define PLLD2_SS_CTRL2                  0x578
 410 #define PLLDP_BASE                      0x590
 411 #define PLLDP_MISC                      0x594
 412 #define PLLDP_SS_CFG                    0x594
 413 #define PLLDP_SS_CTRL1                  0x598
 414 #define PLLDP_SS_CTRL2                  0x5a0
 415 #define PLLC4_BASE                      0x5a4
 416 #define PLLC4_MISC                      0x5a8
 417 #define SPARE0                          0x5c4
 418 #define SPARE1                          0x5c8
 419 #define GPU_ISOB_CTRL                   0x5cc
 420 #define PLLC_MISC_2                     0x5d0
 421 #define PLLC_MISC_3                     0x5d4
 422 #define PLLA_MISC2                      0x5d8
 423 #define PLLC4_OUT                       0x5e4
 424 #define PLLMB_BASE                      0x5e8
 425 #define PLLMB_MISC1                     0x5ec
 426 #define PLLX_MISC_4                     0x5f0
 427 #define PLLX_MISC_5                     0x5f4
 428
 429 #define CLK_SOURCE_XUSB_CORE_HOST       0x600
 430 #define CLK_SOURCE_XUSB_FALCON          0x604
 431 #define CLK_SOURCE_XUSB_FS              0x608
 432 #define CLK_SOURCE_XUSB_CORE_DEV        0x60c
 433 #define CLK_SOURCE_XUSB_SS              0x610
 434 #define CLK_SOURCE_CILAB                0x614
 435 #define CLK_SOURCE_CILCD                0x618
 436 #define CLK_SOURCE_CILEF                0x61c
 437 #define CLK_SOURCE_DSIA_LP              0x620
 438 #define CLK_SOURCE_DSIB_LP              0x624
 439 #define CLK_SOURCE_ENTROPY              0x628
 440 #define CLK_SOURCE_DVFS_REF             0x62c
 441 #define CLK_SOURCE_DVFS_SOC             0x630
 442 #define CLK_SOURCE_EMC_LATENCY          0x640
 443 #define CLK_SOURCE_SOC_THERM            0x644
 444 #define CLK_SOURCE_DMIC1                0x64c
 445 #define CLK_SOURCE_DMIC2                0x650
 446 #define CLK_SOURCE_VI_SENSOR2           0x658
 447 #define CLK_SOURCE_I2C6                 0x65c
 448 #define CLK_SOURCE_MIPIBIF              0x660
 449 #define CLK_SOURCE_EMC_DLL              0x664
 450 #define CLK_SOURCE_UART_FST_MIPI_CAL    0x66c
 451 #define CLK_SOURCE_VIC                  0x678
 452 #define PLLP_OUTC                       0x67c
 453 #define PLLP_MISC1                      0x680
 454 #define EMC_DIV_CLK_SHAPER_CTRL         0x68c
 455 #define EMC_PLLC_SHAPER_CTRL            0x690
 456 #define CLK_SOURCE_SDMMC_LEGACY_TM      0x694
 457 #define CLK_SOURCE_NVDEC                0x698
 458 #define CLK_SOURCE_NVJPG                0x69c
 459 #define CLK_SOURCE_NVENC                0x6a0
 460 #define PLLA1_BASE                      0x6a4
 461 #define PLLA1_MISC_0                    0x6a8
 462 #define PLLA1_MISC_1                    0x6ac
 463 #define PLLA1_MISC_2                    0x6b0
 464 #define PLLA1_MISC_3                    0x6b4
 465 #define AUDIO_SYNC_CLK_DMIC3            0x6b8
 466 #define CLK_SOURCE_DMIC3                0x6bc
 467 #define CLK_SOURCE_APE                  0x6c0
 468 #define CLK_SOURCE_QSPI                 0x6c4
 469 #define CLK_SOURCE_VI_I2C               0x6c8
 470 #define CLK_SOURCE_USB2_HSIC_TRK        0x6cc
 471 #define CLK_SOURCE_PEX_SATA_USB_RX_BYP  0x6d0
 472 #define CLK_SOURCE_MAUD                 0x6d4
 473 #define CLK_SOURCE_TSECB                0x6d8
 474 #define CLK_CPUG_MISC1                  0x6d8
 475 #define ACLK_BURST_POLICY               0x6e0
 476 #define SUPER_ACLK_DIVIDER              0x6e4
 477 #define NVENC_SUPER_CLK_DIVIDER         0x6e8
 478 #define VI_SUPER_CLK_DIVIDER            0x6ec
 479 #define VIC_SUPER_CLK_DIVIDER           0x6f0
 480 #define NVDEC_SUPER_CLK_DIVIDER         0x6f4
 481 #define ISP_SUPER_CLK_DIVIDER           0x6f8
 482 #define ISPB_SUPER_CLK_DIVIDER          0x6fc
 483
 484 #define NVJPG_SUPER_CLK_DIVIDER         0x700
 485 #define SE_SUPER_CLK_DIVIDER            0x704
 486 #define TSEC_SUPER_CLK_DIVIDER          0x708
 487 #define TSECB_SUPER_CLK_DIVIDER         0x70c
 488 #define CLK_SOURCE_UARTAPE              0x710
 489 #define CLK_CPUG_MISC2                  0x714
 490 #define CLK_SOURCE_DBGAPB               0x718
 491 #define CLK_CCPLEX_CC4_RET_CLK_ENB      0x71c
 492 #define ACTMON_CPU_CLK                  0x720
 493 #define CLK_SOURCE_EMC_SAFE             0x724
 494 #define SDMMC2_PLLC4_OUT0_SHAPER_CTRL   0x728
 495 #define SDMMC2_PLLC4_OUT1_SHAPER_CTRL   0x72c
 496 #define SDMMC2_PLLC4_OUT2_SHAPER_CTRL   0x730
 497 #define SDMMC2_DIV_CLK_SHAPER_CTRL      0x734
 498 #define SDMMC4_PLLC4_OUT0_SHAPER_CTRL   0x738
 499 #define SDMMC4_PLLC4_OUT1_SHAPER_CTRL   0x73c
 500 #define SDMMC4_PLLC4_OUT2_SHAPER_CTRL   0x740
 501 #define SDMMC4_DIV_CLK_SHAPER_CTRL      0x744
 502
 503 struct tegra210_car_softc {
 504         device_t                dev;
 505         struct resource *       mem_res;
 506         struct mtx              mtx;
 507         struct clkdom           *clkdom;
 508         int                     type;
 509 };
 510
 511 struct tegra210_init_item {
 512         char            *name;
 513         char            *parent;
 514         uint64_t        frequency;
 515         int             enable;
 516 };
 517
 518 void tegra210_init_plls(struct tegra210_car_softc *sc);
 519
 520 void tegra210_periph_clock(struct tegra210_car_softc *sc);
 521 void tegra210_super_mux_clock(struct tegra210_car_softc *sc);
 522
 523 int tegra210_hwreset_by_idx(struct tegra210_car_softc *sc, intptr_t idx,
 524     bool reset);
 525
 526 #endif /*_TEGRA210_CAR_*/