2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _TEGRA210_CAR_
31 #define _TEGRA210_CAR_
33 #include "clkdev_if.h"
35 #define RD4(sc, reg, val) CLKDEV_READ_4((sc)->clkdev, reg, val)
36 #define WR4(sc, reg, val) CLKDEV_WRITE_4((sc)->clkdev, reg, val)
37 #define MD4(sc, reg, mask, set) CLKDEV_MODIFY_4((sc)->clkdev, reg, mask, set)
38 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
39 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
41 #define RST_SOURCE 0x000
42 #define RST_DEVICES_L 0x004
43 #define RST_DEVICES_H 0x008
44 #define RST_DEVICES_U 0x00C
45 #define CLK_OUT_ENB_L 0x010
46 #define CLK_OUT_ENB_H 0x014
47 #define CLK_OUT_ENB_U 0x018
48 #define SUPER_CCLK_DIVIDER 0x024
49 #define SCLK_BURST_POLICY 0x028
50 #define SUPER_SCLK_DIVIDER 0x02c
51 #define CLK_SYSTEM_RATE 0x030
52 #define CLK_MASK_ARM 0x044
53 #define MISC_CLK_ENB 0x048
55 #define OSC_CTRL 0x050
56 #define OSC_CTRL_OSC_FREQ_GET(x) (((x) >> 28) & 0x0F)
57 #define OSC_CTRL_PLL_REF_DIV_GET(x) (((x) >> 26) & 0x03)
59 #define OSC_FREQ_DET_STATUS 0x05c
60 #define PLLE_SS_CNTL 0x068
61 #define PLLE_SS_CNTL_INTEGOFFSET(x) (((x) & 0x03) << 30)
62 #define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
63 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
64 #define PLLE_SS_CNTL_SSCINVERT (1 << 15)
65 #define PLLE_SS_CNTL_SSCCENTER (1 << 14)
66 #define PLLE_SS_CNTL_SSCPDMBYP (1 << 13)
67 #define PLLE_SS_CNTL_SSCBYP (1 << 12)
68 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
69 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
70 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
72 #define PLLE_SS_CNTL_SSCINCINTRV_MASK (0x3f << 24)
73 #define PLLE_SS_CNTL_SSCINCINTRV_VAL (0x20 << 24)
74 #define PLLE_SS_CNTL_SSCINC_MASK (0xff << 16)
75 #define PLLE_SS_CNTL_SSCINC_VAL (0x1 << 16)
76 #define PLLE_SS_CNTL_SSCMAX_MASK 0x1ff
77 #define PLLE_SS_CNTL_SSCMAX_VAL 0x25
78 #define PLLE_SS_CNTL_DISABLE (PLLE_SS_CNTL_BYPASS_SS | \
79 PLLE_SS_CNTL_INTERP_RESET | \
81 #define PLLE_SS_CNTL_COEFFICIENTS_MASK (PLLE_SS_CNTL_SSCMAX_MASK | \
82 PLLE_SS_CNTL_SSCINC_MASK | \
83 PLLE_SS_CNTL_SSCINCINTRV_MASK)
84 #define PLLE_SS_CNTL_COEFFICIENTS_VAL (PLLE_SS_CNTL_SSCMAX_VAL | \
85 PLLE_SS_CNTL_SSCINC_VAL | \
86 PLLE_SS_CNTL_SSCINCINTRV_VAL)
88 #define PLLE_MISC1 0x06C
89 #define PLLC_BASE 0x080
90 #define PLLC_OUT 0x084
91 #define PLLC_MISC_0 0x088
92 #define PLLC_MISC_1 0x08c
93 #define PLLM_BASE 0x090
94 #define PLLM_MISC1 0x099
95 #define PLLM_MISC2 0x09c
96 #define PLLP_BASE 0x0a0
97 #define PLLP_OUTA 0x0a4
98 #define PLLP_OUTB 0x0a8
99 #define PLLP_MISC 0x0ac
100 #define PLLA_BASE 0x0b0
101 #define PLLA_OUT 0x0b4
102 #define PLLA_MISC1 0x0b8
103 #define PLLA_MISC 0x0bc
104 #define PLLU_BASE 0x0c0
105 #define PLLU_OUTA 0x0c4
106 #define PLLU_MISC1 0x0c8
107 #define PLLU_MISC 0x0cc
108 #define PLLD_BASE 0x0d0
109 #define PLLD_MISC1 0x0d8
110 #define PLLD_MISC 0x0dc
111 #define PLLX_BASE 0x0e0
112 #define PLLX_MISC 0x0e4
113 #define PLLX_MISC_LOCK_ENABLE (1 << 18)
115 #define PLLE_BASE 0x0e8
116 #define PLLE_BASE_ENABLE (1U << 31)
117 #define PLLE_BASE_LOCK_OVERRIDE (1 << 30)
119 #define PLLE_MISC 0x0ec
120 #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xFFFF) << 16)
121 #define PLLE_MISC_CLKENABLE (1 << 15)
122 #define PLLE_MISC_IDDQ_SWCTL (1 << 14)
123 #define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13)
124 #define PLLE_MISC_IDDQ_FREQLOCK (1 << 12)
125 #define PLLE_MISC_LOCK (1 << 11)
126 #define PLLE_MISC_REF_DIS (1 << 10)
127 #define PLLE_MISC_LOCK_ENABLE (1 << 9)
128 #define PLLE_MISC_PTS (1 << 8)
129 #define PLLE_MISC_KCP(x) (((x) & 0x03) << 6)
130 #define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x03) << 4)
131 #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x03) << 2)
132 #define PLLE_MISC_KVCO (1 << 0)
134 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
135 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
136 #define PLLE_MISC_VREG_CTRL_SHIFT 2
137 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
138 #define PLLE_MISC_SETUP_BASE_SHIFT 16
139 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
141 #define PLLE_SS_CNTL1 0x0f0
142 #define PLLE_SS_CNTL2 0x0f4
143 #define LVL2_CLK_GATE_OVRA 0x0f8
144 #define LVL2_CLK_GATE_OVRB 0x0fc
145 #define LVL2_CLK_GATE_OVRC 0x3a0 /* Misordered in TRM */
146 #define LVL2_CLK_GATE_OVRD 0x3a4
147 #define LVL2_CLK_GATE_OVRE 0x554
149 #define CLK_SOURCE_I2S2 0x100
150 #define CLK_SOURCE_I2S3 0x104
151 #define CLK_SOURCE_SPDIF_OUT 0x108
152 #define CLK_SOURCE_SPDIF_IN 0x10c
153 #define CLK_SOURCE_PWM 0x110
154 #define CLK_SOURCE_SPI2 0x118
155 #define CLK_SOURCE_SPI3 0x11c
156 #define CLK_SOURCE_I2C1 0x124
157 #define CLK_SOURCE_I2C5 0x128
158 #define CLK_SOURCE_SPI1 0x134
159 #define CLK_SOURCE_DISP1 0x138
160 #define CLK_SOURCE_DISP2 0x13c
161 #define CLK_SOURCE_ISP 0x144
162 #define CLK_SOURCE_VI 0x148
163 #define CLK_SOURCE_SDMMC1 0x150
164 #define CLK_SOURCE_SDMMC2 0x154
165 #define CLK_SOURCE_SDMMC4 0x164
166 #define CLK_SOURCE_UARTA 0x178
167 #define CLK_SOURCE_UARTB 0x17c
168 #define CLK_SOURCE_HOST1X 0x180
169 #define CLK_SOURCE_I2C2 0x198
170 #define CLK_SOURCE_EMC 0x19c
171 #define CLK_SOURCE_UARTC 0x1a0
172 #define CLK_SOURCE_VI_SENSOR 0x1a8
173 #define CLK_SOURCE_SPI4 0x1b4
174 #define CLK_SOURCE_I2C3 0x1b8
175 #define CLK_SOURCE_SDMMC3 0x1bc
176 #define CLK_SOURCE_UARTD 0x1c0
177 #define CLK_SOURCE_OWR 0x1cc
178 #define CLK_SOURCE_CSITE 0x1d4
179 #define CLK_SOURCE_I2S1 0x1d8
180 #define CLK_SOURCE_DTV 0x1dc
181 #define CLK_SOURCE_TSEC 0x1f4
182 #define CLK_SOURCE_SPARE2 0x1f8
184 #define CLK_OUT_ENB_X 0x280
185 #define CLK_ENB_X_SET 0x284
186 #define CLK_ENB_X_CLR 0x288
187 #define RST_DEVICES_X 0x28C
188 #define RST_DEV_X_SET 0x290
189 #define RST_DEV_X_CLR 0x294
190 #define CLK_OUT_ENB_Y 0x298
191 #define CLK_ENB_Y_SET 0x29c
192 #define CLK_ENB_Y_CLR 0x2a0
193 #define RST_DEVICES_Y 0x2a4
194 #define RST_DEV_Y_SET 0x2a8
195 #define RST_DEV_Y_CLR 0x2ac
196 #define DFLL_BASE 0x2f4
197 #define DFLL_BASE_DVFS_DFLL_RESET (1 << 0)
199 #define RST_DEV_L_SET 0x300
200 #define RST_DEV_L_CLR 0x304
201 #define RST_DEV_H_SET 0x308
202 #define RST_DEV_H_CLR 0x30c
203 #define RST_DEV_U_SET 0x310
204 #define RST_DEV_U_CLR 0x314
205 #define CLK_ENB_L_SET 0x320
206 #define CLK_ENB_L_CLR 0x324
207 #define CLK_ENB_H_SET 0x328
208 #define CLK_ENB_H_CLR 0x32c
209 #define CLK_ENB_U_SET 0x330
210 #define CLK_ENB_U_CLR 0x334
211 #define CCPLEX_PG_SM_OVRD 0x33c
212 #define CPU_CMPLX_SET 0x340
213 #define RST_DEVICES_V 0x358
214 #define RST_DEVICES_W 0x35c
215 #define CLK_OUT_ENB_V 0x360
216 #define CLK_OUT_ENB_W 0x364
217 #define CCLKG_BURST_POLICY 0x368
218 #define SUPER_CCLKG_DIVIDER 0x36C
219 #define CCLKLP_BURST_POLICY 0x370
220 #define SUPER_CCLKLP_DIVIDER 0x374
221 #define CLK_CPUG_CMPLX 0x378
222 #define CPU_SOFTRST_CTRL 0x380
223 #define CPU_SOFTRST_CTRL1 0x384
224 #define CPU_SOFTRST_CTRL2 0x388
225 #define CLK_SOURCE_MSELECT 0x3b4
226 #define CLK_SOURCE_TSENSOR 0x3b8
227 #define CLK_SOURCE_I2S4 0x3bc
228 #define CLK_SOURCE_I2S5 0x3c0
229 #define CLK_SOURCE_I2C4 0x3c4
230 #define CLK_SOURCE_AHUB 0x3d0
231 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4
232 #define CLK_SOURCE_ACTMON 0x3e8
233 #define CLK_SOURCE_EXTPERIPH1 0x3ec
234 #define CLK_SOURCE_EXTPERIPH2 0x3f0
235 #define CLK_SOURCE_EXTPERIPH3 0x3f4
236 #define CLK_SOURCE_I2C_SLOW 0x3fc
238 #define CLK_SOURCE_SYS 0x400
239 #define CLK_SOURCE_ISPB 0x404
240 #define CLK_SOURCE_SOR1 0x410
241 #define CLK_SOURCE_SOR0 0x414
242 #define CLK_SOURCE_SATA_OOB 0x420
243 #define CLK_SOURCE_SATA 0x424
244 #define CLK_SOURCE_HDA 0x428
245 #define RST_DEV_V_SET 0x430
246 #define RST_DEV_V_CLR 0x434
247 #define RST_DEV_W_SET 0x438
248 #define RST_DEV_W_CLR 0x43c
249 #define CLK_ENB_V_SET 0x440
250 #define CLK_ENB_V_CLR 0x444
251 #define CLK_ENB_W_SET 0x448
252 #define CLK_ENB_W_CLR 0x44c
253 #define RST_CPUG_CMPLX_SET 0x450
254 #define RST_CPUG_CMPLX_CLR 0x454
255 #define CLK_CPUG_CMPLX_SET 0x460
256 #define CLK_CPUG_CMPLX_CLR 0x464
257 #define CPU_CMPLX_STATUS 0x470
258 #define INTSTATUS 0x478
259 #define INTMASK 0x47c
260 #define UTMIP_PLL_CFG0 0x480
262 #define UTMIP_PLL_CFG1 0x484
263 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17)
264 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
265 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15)
266 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
267 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
268 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
269 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
271 #define UTMIP_PLL_CFG2 0x488
272 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN (1 << 30)
273 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP (1 << 25)
274 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN (1 << 24)
275 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
276 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
277 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP (1 << 5)
278 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
279 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP (1 << 3)
280 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
281 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP (1 << 1)
282 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
284 #define PLLE_AUX 0x48c
285 #define PLLE_AUX_SS_SEQ_INCLUDE (1U << 31)
286 #define PLLE_AUX_REF_SEL_PLLREFE (1 << 28)
287 #define PLLE_AUX_SEQ_STATE_GET(x) (((x) >> 26) & 0x03)
288 #define PLLE_AUX_SEQ_STATE_OFF 0
289 #define PLLE_AUX_SEQ_STATE_ON 1
290 #define PLLE_AUX_SEQ_STATE_BUSY 2
291 #define PLLE_AUX_SEQ_START_STATE (1 << 25)
292 #define PLLE_AUX_SEQ_ENABLE (1 << 24)
293 #define PLLE_AUX_SS_DLY(x) (((x) & 0xFF) << 16)
294 #define PLLE_AUX_SS_LOCK_DLY(x) (((x) & 0xFF) << 8)
295 #define PLLE_AUX_SS_TEST_FAST_PT (1 << 7)
296 #define PLLE_AUX_SS_SWCTL (1 << 6)
297 #define PLLE_AUX_CONFIG_SWCTL (1 << 6)
298 #define PLLE_AUX_ENABLE_SWCTL (1 << 4)
299 #define PLLE_AUX_USE_LOCKDET (1 << 3)
300 #define PLLE_AUX_REF_SRC (1 << 2)
301 #define PLLE_AUX_PLLP_CML1_OEN (1 << 1)
302 #define PLLE_AUX_PLLP_CML0_OEN (1 << 0)
304 #define SATA_PLL_CFG0 0x490
305 #define SATA_PLL_CFG0_SEQ_START_STATE (1 << 25)
306 #define SATA_PLL_CFG0_SEQ_ENABLE (1 << 24)
307 #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
308 #define SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE (1 << 7)
309 #define SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE (1 << 6)
310 #define SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5)
311 #define SATA_PLL_CFG0_SEQ_IN_SWCTL (1 << 4)
312 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 2)
313 #define SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE (1 << 1)
314 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
316 #define SATA_PLL_CFG1 0x494
317 #define PCIE_PLL_CFG 0x498
318 #define PCIE_PLL_CFG_SEQ_START_STATE (1 << 25)
319 #define PCIE_PLL_CFG_SEQ_ENABLE (1 << 24)
321 #define PROG_AUDIO_DLY_CLK 0x49c
322 #define AUDIO_SYNC_CLK_I2S1 0x4a0
323 #define AUDIO_SYNC_CLK_I2S2 0x4a4
324 #define AUDIO_SYNC_CLK_I2S3 0x4a8
325 #define AUDIO_SYNC_CLK_I2S4 0x4ac
326 #define AUDIO_SYNC_CLK_I2S5 0x4b0
327 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
328 #define PLLD2_BASE 0x4b8
329 #define PLLD2_MISC 0x4bc
330 #define UTMIP_PLL_CFG3 0x4c0
331 #define PLLREFE_BASE 0x4c4
332 #define PLLREFE_MISC 0x4c8
333 #define PLLREFE_OUT 0x4cc
334 #define CPU_FINETRIM_BYP 0x4d0
335 #define CPU_FINETRIM_SELECT 0x4d4
336 #define CPU_FINETRIM_DR 0x4d8
337 #define CPU_FINETRIM_DF 0x4dc
338 #define CPU_FINETRIM_F 0x4e0
339 #define CPU_FINETRIM_R 0x4e4
340 #define PLLC2_BASE 0x4e8
341 #define PLLC2_MISC_0 0x4ec
342 #define PLLC2_MISC_1 0x4f0
343 #define PLLC2_MISC_2 0x4f4
344 #define PLLC2_MISC_3 0x4f8
345 #define PLLC3_BASE 0x4fc
347 #define PLLC3_MISC_0 0x500
348 #define PLLC3_MISC_1 0x504
349 #define PLLC3_MISC_2 0x508
350 #define PLLC3_MISC_3 0x50c
351 #define PLLX_MISC_2 0x514
352 #define PLLX_MISC_2 0x514
353 #define PLLX_MISC_2_DYNRAMP_STEPB(x) (((x) & 0xFF) << 24)
354 #define PLLX_MISC_2_DYNRAMP_STEPA(x) (((x) & 0xFF) << 16)
355 #define PLLX_MISC_2_NDIV_NEW(x) (((x) & 0xFF) << 8)
356 #define PLLX_MISC_2_EN_FSTLCK (1 << 5)
357 #define PLLX_MISC_2_LOCK_OVERRIDE (1 << 4)
358 #define PLLX_MISC_2_PLL_FREQLOCK (1 << 3)
359 #define PLLX_MISC_2_DYNRAMP_DONE (1 << 2)
360 #define PLLX_MISC_2_EN_DYNRAMP (1 << 0)
362 #define PLLX_MISC_3 0x518
364 #define XUSBIO_PLL_CFG0 0x51c
365 #define XUSBIO_PLL_CFG0_SEQ_START_STATE (1 << 25)
366 #define XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
367 #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
368 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
369 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
370 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
372 #define XUSBIO_PLL_CFG1 0x520
373 #define PLLE_AUX1 0x524
374 #define PLLP_RESHIFT 0x528
375 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
376 #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK (1U << 31)
377 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1 << 25)
378 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1 << 24)
379 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE (1 << 7)
380 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1 << 6)
381 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5)
382 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1 << 4)
383 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1 << 2)
384 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1 << 1)
385 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1 << 0)
387 #define PLLU_HW_PWRDN_CFG0 0x530
388 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE (1 << 28)
389 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE (1 << 24)
390 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT (1 << 7)
391 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET (1 << 6)
392 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1 << 2)
393 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL (1 << 0)
395 #define XUSB_PLL_CFG0 0x534
396 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
397 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14)
399 #define CLK_CPU_MISC 0x53c
400 #define CLK_CPUG_MISC 0x540
401 #define PLLX_HW_CTRL_CFG 0x548
402 #define PLLX_SW_RAMP_CFG 0x54c
403 #define PLLX_HW_CTRL_STATUS 0x550
404 #define SPARE_REG0 0x55c
405 #define SPARE_REG0_MDIV_GET(x) (((x) >> 2) & 0x03)
407 #define AUDIO_SYNC_CLK_DMIC1 0x560
408 #define AUDIO_SYNC_CLK_DMIC2 0x564
409 #define PLLD2_SS_CFG 0x570
410 #define PLLD2_SS_CTRL1 0x574
411 #define PLLD2_SS_CTRL2 0x578
412 #define PLLDP_BASE 0x590
413 #define PLLDP_MISC 0x594
414 #define PLLDP_SS_CFG 0x594
415 #define PLLDP_SS_CTRL1 0x598
416 #define PLLDP_SS_CTRL2 0x5a0
417 #define PLLC4_BASE 0x5a4
418 #define PLLC4_MISC 0x5a8
421 #define GPU_ISOB_CTRL 0x5cc
422 #define PLLC_MISC_2 0x5d0
423 #define PLLC_MISC_3 0x5d4
424 #define PLLA_MISC2 0x5d8
425 #define PLLC4_OUT 0x5e4
426 #define PLLMB_BASE 0x5e8
427 #define PLLMB_MISC1 0x5ec
428 #define PLLX_MISC_4 0x5f0
429 #define PLLX_MISC_5 0x5f4
431 #define CLK_SOURCE_XUSB_CORE_HOST 0x600
432 #define CLK_SOURCE_XUSB_FALCON 0x604
433 #define CLK_SOURCE_XUSB_FS 0x608
434 #define CLK_SOURCE_XUSB_CORE_DEV 0x60c
435 #define CLK_SOURCE_XUSB_SS 0x610
436 #define CLK_SOURCE_CILAB 0x614
437 #define CLK_SOURCE_CILCD 0x618
438 #define CLK_SOURCE_CILEF 0x61c
439 #define CLK_SOURCE_DSIA_LP 0x620
440 #define CLK_SOURCE_DSIB_LP 0x624
441 #define CLK_SOURCE_ENTROPY 0x628
442 #define CLK_SOURCE_DVFS_REF 0x62c
443 #define CLK_SOURCE_DVFS_SOC 0x630
444 #define CLK_SOURCE_EMC_LATENCY 0x640
445 #define CLK_SOURCE_SOC_THERM 0x644
446 #define CLK_SOURCE_DMIC1 0x64c
447 #define CLK_SOURCE_DMIC2 0x650
448 #define CLK_SOURCE_VI_SENSOR2 0x658
449 #define CLK_SOURCE_I2C6 0x65c
450 #define CLK_SOURCE_MIPIBIF 0x660
451 #define CLK_SOURCE_EMC_DLL 0x664
452 #define CLK_SOURCE_UART_FST_MIPI_CAL 0x66c
453 #define CLK_SOURCE_VIC 0x678
454 #define PLLP_OUTC 0x67c
455 #define PLLP_MISC1 0x680
456 #define EMC_DIV_CLK_SHAPER_CTRL 0x68c
457 #define EMC_PLLC_SHAPER_CTRL 0x690
458 #define CLK_SOURCE_SDMMC_LEGACY_TM 0x694
459 #define CLK_SOURCE_NVDEC 0x698
460 #define CLK_SOURCE_NVJPG 0x69c
461 #define CLK_SOURCE_NVENC 0x6a0
462 #define PLLA1_BASE 0x6a4
463 #define PLLA1_MISC_0 0x6a8
464 #define PLLA1_MISC_1 0x6ac
465 #define PLLA1_MISC_2 0x6b0
466 #define PLLA1_MISC_3 0x6b4
467 #define AUDIO_SYNC_CLK_DMIC3 0x6b8
468 #define CLK_SOURCE_DMIC3 0x6bc
469 #define CLK_SOURCE_APE 0x6c0
470 #define CLK_SOURCE_QSPI 0x6c4
471 #define CLK_SOURCE_VI_I2C 0x6c8
472 #define CLK_SOURCE_USB2_HSIC_TRK 0x6cc
473 #define CLK_SOURCE_PEX_SATA_USB_RX_BYP 0x6d0
474 #define CLK_SOURCE_MAUD 0x6d4
475 #define CLK_SOURCE_TSECB 0x6d8
476 #define CLK_CPUG_MISC1 0x6d8
477 #define ACLK_BURST_POLICY 0x6e0
478 #define SUPER_ACLK_DIVIDER 0x6e4
479 #define NVENC_SUPER_CLK_DIVIDER 0x6e8
480 #define VI_SUPER_CLK_DIVIDER 0x6ec
481 #define VIC_SUPER_CLK_DIVIDER 0x6f0
482 #define NVDEC_SUPER_CLK_DIVIDER 0x6f4
483 #define ISP_SUPER_CLK_DIVIDER 0x6f8
484 #define ISPB_SUPER_CLK_DIVIDER 0x6fc
486 #define NVJPG_SUPER_CLK_DIVIDER 0x700
487 #define SE_SUPER_CLK_DIVIDER 0x704
488 #define TSEC_SUPER_CLK_DIVIDER 0x708
489 #define TSECB_SUPER_CLK_DIVIDER 0x70c
490 #define CLK_SOURCE_UARTAPE 0x710
491 #define CLK_CPUG_MISC2 0x714
492 #define CLK_SOURCE_DBGAPB 0x718
493 #define CLK_CCPLEX_CC4_RET_CLK_ENB 0x71c
494 #define ACTMON_CPU_CLK 0x720
495 #define CLK_SOURCE_EMC_SAFE 0x724
496 #define SDMMC2_PLLC4_OUT0_SHAPER_CTRL 0x728
497 #define SDMMC2_PLLC4_OUT1_SHAPER_CTRL 0x72c
498 #define SDMMC2_PLLC4_OUT2_SHAPER_CTRL 0x730
499 #define SDMMC2_DIV_CLK_SHAPER_CTRL 0x734
500 #define SDMMC4_PLLC4_OUT0_SHAPER_CTRL 0x738
501 #define SDMMC4_PLLC4_OUT1_SHAPER_CTRL 0x73c
502 #define SDMMC4_PLLC4_OUT2_SHAPER_CTRL 0x740
503 #define SDMMC4_DIV_CLK_SHAPER_CTRL 0x744
505 struct tegra210_car_softc {
507 struct resource * mem_res;
509 struct clkdom *clkdom;
513 struct tegra210_init_item {
520 void tegra210_init_plls(struct tegra210_car_softc *sc);
522 void tegra210_periph_clock(struct tegra210_car_softc *sc);
523 void tegra210_super_mux_clock(struct tegra210_car_softc *sc);
525 int tegra210_hwreset_by_idx(struct tegra210_car_softc *sc, intptr_t idx,
528 #endif /*_TEGRA210_CAR_*/