2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/malloc.h>
37 #include <sys/mutex.h>
40 #include <machine/bus.h>
42 #include <dev/extres/clk/clk.h>
43 #include <dev/extres/hwreset/hwreset.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/psci/smccc.h>
48 #include <arm/nvidia/tegra_pmc.h>
50 #define PMC_CNTRL 0x000
51 #define PMC_CNTRL_SHUTDOWN_OE (1 << 22)
52 #define PMC_CNTRL_CPUPWRGOOD_SEL_MASK (0x3 << 20)
53 #define PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT 20
54 #define PMC_CNTRL_CPUPWRGOOD_EN (1 << 19)
55 #define PMC_CNTRL_FUSE_OVERRIDE (1 << 18)
56 #define PMC_CNTRL_INTR_POLARITY (1 << 17)
57 #define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16)
58 #define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15)
59 #define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14)
60 #define PMC_CNTRL_AOINIT (1 << 13)
61 #define PMC_CNTRL_PWRGATE_DIS (1 << 12)
62 #define PMC_CNTRL_SYSCLK_OE (1 << 11)
63 #define PMC_CNTRL_SYSCLK_POLARITY (1 << 10)
64 #define PMC_CNTRL_PWRREQ_OE (1 << 9)
65 #define PMC_CNTRL_PWRREQ_POLARITY (1 << 8)
66 #define PMC_CNTRL_BLINK_EN (1 << 7)
67 #define PMC_CNTRL_GLITCHDET_DIS (1 << 6)
68 #define PMC_CNTRL_LATCHWAKE_EN (1 << 5)
69 #define PMC_CNTRL_MAIN_RST (1 << 4)
70 #define PMC_CNTRL_KBC_RST (1 << 3)
71 #define PMC_CNTRL_RTC_RST (1 << 2)
72 #define PMC_CNTRL_RTC_CLK_DIS (1 << 1)
73 #define PMC_CNTRL_KBC_CLK_DIS (1 << 0)
75 #define PMC_DPD_SAMPLE 0x020
77 #define PMC_CLAMP_STATUS 0x02C
78 #define PMC_CLAMP_STATUS_PARTID(x) (1 << ((x) & 0x1F))
80 #define PMC_PWRGATE_TOGGLE 0x030
81 #define PMC_PWRGATE_TOGGLE_START (1 << 8)
82 #define PMC_PWRGATE_TOGGLE_PARTID(x) (((x) & 0x1F) << 0)
84 #define PMC_REMOVE_CLAMPING_CMD 0x034
85 #define PMC_REMOVE_CLAMPING_CMD_PARTID(x) (1 << ((x) & 0x1F))
87 #define PMC_PWRGATE_STATUS 0x038
88 #define PMC_PWRGATE_STATUS_PARTID(x) (1 << ((x) & 0x1F))
90 #define PMC_SCRATCH0 0x050
91 #define PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
92 #define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30)
93 #define PMC_SCRATCH0_MODE_RCM (1 << 1)
94 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
95 PMC_SCRATCH0_MODE_BOOTLOADER | \
96 PMC_SCRATCH0_MODE_RCM)
98 #define PMC_CPUPWRGOOD_TIMER 0x0c8
99 #define PMC_CPUPWROFF_TIMER 0x0cc
101 #define PMC_SCRATCH41 0x140
103 #define PMC_SENSOR_CTRL 0x1b0
104 #define PMC_SENSOR_CTRL_BLOCK_SCRATCH_WRITE (1 << 2)
105 #define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1)
106 #define PMC_SENSOR_CTRL_ENABLE_PG (1 << 0)
108 #define PMC_IO_DPD_REQ 0x1b8
109 #define PMC_IO_DPD_REQ_CODE_IDLE (0 << 30)
110 #define PMC_IO_DPD_REQ_CODE_OFF (1 << 30)
111 #define PMC_IO_DPD_REQ_CODE_ON (2 << 30)
112 #define PMC_IO_DPD_REQ_CODE_MASK (3 << 30)
114 #define PMC_IO_DPD_STATUS 0x1bc
115 #define PMC_IO_DPD_STATUS_HDMI (1 << 28)
116 #define PMC_IO_DPD2_REQ 0x1c0
117 #define PMC_IO_DPD2_STATUS 0x1c4
118 #define PMC_IO_DPD2_STATUS_HV (1 << 6)
119 #define PMC_SEL_DPD_TIM 0x1c8
121 #define PMC_SCRATCH54 0x258
122 #define PMC_SCRATCH54_DATA_SHIFT 8
123 #define PMC_SCRATCH54_ADDR_SHIFT 0
125 #define PMC_SCRATCH55 0x25c
126 #define PMC_SCRATCH55_RST_ENABLE (1 << 31)
127 #define PMC_SCRATCH55_CNTRL_TYPE (1 << 30)
128 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
129 #define PMC_SCRATCH55_CNTRL_ID_MASK 0x07
130 #define PMC_SCRATCH55_PINMUX_SHIFT 24
131 #define PMC_SCRATCH55_PINMUX_MASK 0x07
132 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
133 #define PMC_SCRATCH55_CHECKSUM_MASK 0xFF
134 #define PMC_SCRATCH55_16BITOP (1 << 15)
135 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
136 #define PMC_SCRATCH55_I2CSLV1_MASK 0x7F
138 #define PMC_GPU_RG_CNTRL 0x2d4
141 #define PMC_SMC 0xc2fffe00
142 #define PMC_SMC_READ 0xaa
143 #define PMC_SMC_WRITE 0xbb
145 #define PMC_LOCK(_sc) mtx_lock(&(_sc)->mtx)
146 #define PMC_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
147 #define PMC_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
148 device_get_nameunit(_sc->dev), "tegra210_pmc", MTX_DEF)
149 #define PMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx);
150 #define PMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED);
151 #define PMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED);
153 struct tegra210_pmc_softc {
155 struct resource *mem_res;
161 enum tegra_suspend_mode suspend_mode;
162 uint32_t cpu_good_time;
163 uint32_t cpu_off_time;
164 uint32_t core_osc_time;
165 uint32_t core_pmu_time;
166 uint32_t core_off_time;
171 uint32_t lp0_vec_phys;
172 uint32_t lp0_vec_size;
175 static struct ofw_compat_data compat_data[] = {
176 {"nvidia,tegra210-pmc", 1},
180 static struct tegra210_pmc_softc *pmc_sc;
182 static inline struct tegra210_pmc_softc *
183 tegra210_pmc_get_sc(void)
186 panic("To early call to Tegra PMC driver.\n");
191 WR4(struct tegra210_pmc_softc *sc, bus_size_t r, uint32_t v)
193 struct arm_smccc_res res;
195 if (sc->secure_access) {
196 arm_smccc_smc(PMC_SMC, PMC_SMC_WRITE, r, v, 0, 0, 0, 0, &res);
198 device_printf(sc->dev," PMC SMC write failed: %lu\n",
202 bus_write_4(sc->mem_res, r, v);
206 RD4(struct tegra210_pmc_softc *sc, bus_size_t r)
208 struct arm_smccc_res res;
210 if (sc->secure_access) {
211 arm_smccc_smc(PMC_SMC, PMC_SMC_READ, r, 0, 0, 0, 0, 0, &res);
213 device_printf(sc->dev," PMC SMC write failed: %lu\n",
215 return((uint32_t)res.a1);
218 return(bus_read_4(sc->mem_res, r));
222 tegra210_pmc_set_powergate(struct tegra210_pmc_softc *sc,
223 enum tegra_powergate_id id, int ena)
230 reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id);
231 if (((reg != 0) && ena) || ((reg == 0) && !ena)) {
236 for (i = 100; i > 0; i--) {
237 reg = RD4(sc, PMC_PWRGATE_TOGGLE);
238 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)
243 device_printf(sc->dev,
244 "Timeout when waiting for TOGGLE_START\n");
246 WR4(sc, PMC_PWRGATE_TOGGLE,
247 PMC_PWRGATE_TOGGLE_START | PMC_PWRGATE_TOGGLE_PARTID(id));
249 for (i = 100; i > 0; i--) {
250 reg = RD4(sc, PMC_PWRGATE_TOGGLE);
251 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)
256 device_printf(sc->dev,
257 "Timeout when waiting for TOGGLE_START\n");
263 tegra_powergate_remove_clamping(enum tegra_powergate_id id)
265 struct tegra210_pmc_softc *sc;
267 enum tegra_powergate_id swid;
270 sc = tegra210_pmc_get_sc();
272 if (id == TEGRA_POWERGATE_3D) {
273 WR4(sc, PMC_GPU_RG_CNTRL, 0);
277 reg = RD4(sc, PMC_PWRGATE_STATUS);
278 if ((reg & PMC_PWRGATE_STATUS_PARTID(id)) == 0)
279 panic("Attempt to remove clamping for unpowered partition.\n");
281 if (id == TEGRA_POWERGATE_PCX)
282 swid = TEGRA_POWERGATE_VDE;
283 else if (id == TEGRA_POWERGATE_VDE)
284 swid = TEGRA_POWERGATE_PCX;
287 WR4(sc, PMC_REMOVE_CLAMPING_CMD, PMC_REMOVE_CLAMPING_CMD_PARTID(swid));
289 for (i = 100; i > 0; i--) {
290 reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD);
291 if ((reg & PMC_REMOVE_CLAMPING_CMD_PARTID(swid)) == 0)
296 device_printf(sc->dev, "Timeout when remove clamping\n");
298 reg = RD4(sc, PMC_CLAMP_STATUS);
299 if ((reg & PMC_CLAMP_STATUS_PARTID(id)) != 0)
300 panic("Cannot remove clamping\n");
306 tegra_powergate_is_powered(enum tegra_powergate_id id)
308 struct tegra210_pmc_softc *sc;
311 sc = tegra210_pmc_get_sc();
313 reg = RD4(sc, PMC_PWRGATE_STATUS);
314 return ((reg & PMC_PWRGATE_STATUS_PARTID(id)) ? 1 : 0);
318 tegra_powergate_power_on(enum tegra_powergate_id id)
320 struct tegra210_pmc_softc *sc;
323 sc = tegra210_pmc_get_sc();
325 rv = tegra210_pmc_set_powergate(sc, id, 1);
327 device_printf(sc->dev, "Cannot set powergate: %d\n", id);
331 for (i = 100; i > 0; i--) {
332 if (tegra_powergate_is_powered(id))
337 device_printf(sc->dev, "Timeout when waiting on power up\n");
345 tegra_powergate_power_off(enum tegra_powergate_id id)
347 struct tegra210_pmc_softc *sc;
350 sc = tegra210_pmc_get_sc();
352 rv = tegra210_pmc_set_powergate(sc, id, 0);
354 device_printf(sc->dev, "Cannot set powergate: %d\n", id);
357 for (i = 100; i > 0; i--) {
358 if (!tegra_powergate_is_powered(id))
363 device_printf(sc->dev, "Timeout when waiting on power off\n");
369 tegra_powergate_sequence_power_up(enum tegra_powergate_id id, clk_t clk,
372 struct tegra210_pmc_softc *sc;
375 sc = tegra210_pmc_get_sc();
377 rv = hwreset_assert(rst);
379 device_printf(sc->dev, "Cannot assert reset\n");
385 device_printf(sc->dev, "Cannot stop clock\n");
389 rv = tegra_powergate_power_on(id);
391 device_printf(sc->dev, "Cannot power on powergate\n");
395 rv = clk_enable(clk);
397 device_printf(sc->dev, "Cannot enable clock\n");
402 rv = tegra_powergate_remove_clamping(id);
404 device_printf(sc->dev, "Cannot remove clamping\n");
407 rv = hwreset_deassert(rst);
409 device_printf(sc->dev, "Cannot unreset reset\n");
418 tegra_powergate_power_off(id);
423 tegra210_pmc_parse_fdt(struct tegra210_pmc_softc *sc, phandle_t node)
429 rv = OF_getencprop(node, "nvidia,suspend-mode", &tmp, sizeof(tmp));
433 sc->suspend_mode = TEGRA_SUSPEND_LP0;
437 sc->suspend_mode = TEGRA_SUSPEND_LP1;
441 sc->suspend_mode = TEGRA_SUSPEND_LP2;
445 sc->suspend_mode = TEGRA_SUSPEND_NONE;
450 rv = OF_getencprop(node, "nvidia,cpu-pwr-good-time", &tmp, sizeof(tmp));
452 sc->cpu_good_time = tmp;
453 sc->suspend_mode = TEGRA_SUSPEND_NONE;
456 rv = OF_getencprop(node, "nvidia,cpu-pwr-off-time", &tmp, sizeof(tmp));
458 sc->cpu_off_time = tmp;
459 sc->suspend_mode = TEGRA_SUSPEND_NONE;
462 rv = OF_getencprop(node, "nvidia,core-pwr-good-time", tmparr,
464 if (rv == sizeof(tmparr)) {
465 sc->core_osc_time = tmparr[0];
466 sc->core_pmu_time = tmparr[1];
467 sc->suspend_mode = TEGRA_SUSPEND_NONE;
470 rv = OF_getencprop(node, "nvidia,core-pwr-off-time", &tmp, sizeof(tmp));
472 sc->core_off_time = tmp;
473 sc->suspend_mode = TEGRA_SUSPEND_NONE;
477 OF_hasprop(node, "nvidia,core-power-req-active-high");
479 OF_hasprop(node, "nvidia,sys-clock-req-active-high");
481 OF_hasprop(node, "nvidia,combined-power-req");
482 sc->cpu_pwr_good_en =
483 OF_hasprop(node, "nvidia,cpu-pwr-good-en");
485 rv = OF_getencprop(node, "nvidia,lp0-vec", tmparr, sizeof(tmparr));
486 if (rv == sizeof(tmparr)) {
488 sc->lp0_vec_phys = tmparr[0];
489 sc->core_pmu_time = tmparr[1];
490 sc->lp0_vec_size = TEGRA_SUSPEND_NONE;
491 if (sc->suspend_mode == TEGRA_SUSPEND_LP0)
492 sc->suspend_mode = TEGRA_SUSPEND_LP1;
498 tegra210_pmc_check_secure(struct tegra210_pmc_softc *sc)
502 sc->secure_access = false;
505 * If PMC is coverd by secure trust zone, all reads returns 0,
506 * Use scratch0 register acvcess test
508 orig = RD4(sc, PMC_SCRATCH0);
509 WR4(sc, PMC_SCRATCH0, 0xDEADBEEF);
510 if (RD4(sc, PMC_SCRATCH0) == 0) {
511 sc->secure_access = true;
514 WR4(sc, PMC_SCRATCH0, 0xBADC0DE);
515 if (RD4(sc, PMC_SCRATCH0) == 0) {
516 sc->secure_access = true;
519 WR4(sc, PMC_SCRATCH0, orig);
523 tegra210_pmc_probe(device_t dev)
526 if (!ofw_bus_status_okay(dev))
529 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
532 device_set_desc(dev, "Tegra PMC");
533 return (BUS_PROBE_DEFAULT);
537 tegra210_pmc_detach(device_t dev)
540 /* This device is always present. */
545 tegra210_pmc_attach(device_t dev)
547 struct tegra210_pmc_softc *sc;
552 sc = device_get_softc(dev);
554 node = ofw_bus_get_node(dev);
557 rv = tegra210_pmc_parse_fdt(sc, node);
559 device_printf(sc->dev, "Cannot parse FDT data\n");
563 rv = clk_get_by_ofw_name(sc->dev, 0, "pclk", &sc->clk);
565 device_printf(sc->dev, "Cannot get \"pclk\" clock\n");
570 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
572 if (sc->mem_res == NULL) {
573 device_printf(dev, "Cannot allocate memory resources\n");
577 tegra210_pmc_check_secure(sc);
579 /* Enable CPU power request. */
580 reg = RD4(sc, PMC_CNTRL);
581 reg |= PMC_CNTRL_CPU_PWRREQ_OE;
582 WR4(sc, PMC_CNTRL, reg);
584 /* Set sysclk output polarity */
585 reg = RD4(sc, PMC_CNTRL);
586 if (sc->sysclkreq_high)
587 reg &= ~PMC_CNTRL_SYSCLK_POLARITY;
589 reg |= PMC_CNTRL_SYSCLK_POLARITY;
590 WR4(sc, PMC_CNTRL, reg);
592 /* Enable sysclk request. */
593 reg = RD4(sc, PMC_CNTRL);
594 reg |= PMC_CNTRL_SYSCLK_OE;
595 WR4(sc, PMC_CNTRL, reg);
598 * Remove HDMI from deep power down mode.
599 * XXX mote this to HDMI driver
601 reg = RD4(sc, PMC_IO_DPD_STATUS);
602 reg &= ~ PMC_IO_DPD_STATUS_HDMI;
603 WR4(sc, PMC_IO_DPD_STATUS, reg);
605 reg = RD4(sc, PMC_IO_DPD2_STATUS);
606 reg &= ~ PMC_IO_DPD2_STATUS_HV;
607 WR4(sc, PMC_IO_DPD2_STATUS, reg);
610 panic("tegra210_pmc: double driver attach");
615 static device_method_t tegra210_pmc_methods[] = {
616 /* Device interface */
617 DEVMETHOD(device_probe, tegra210_pmc_probe),
618 DEVMETHOD(device_attach, tegra210_pmc_attach),
619 DEVMETHOD(device_detach, tegra210_pmc_detach),
624 static DEFINE_CLASS_0(pmc, tegra210_pmc_driver, tegra210_pmc_methods,
625 sizeof(struct tegra210_pmc_softc));
626 EARLY_DRIVER_MODULE(tegra210_pmc, simplebus, tegra210_pmc_driver, NULL, NULL,