sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/param.h>
  29 #include <sys/systm.h>
  30 #include <sys/bus.h>
  31 #include <sys/kernel.h>
  32 #include <sys/module.h>
  33 #include <sys/malloc.h>
  34 #include <sys/rman.h>
  35
  36 #include <machine/bus.h>
  37
  38 #include <dev/clk/clk.h>
  39 #include <dev/hwreset/hwreset.h>
  40 #include <dev/phy/phy.h>
  41 #include <dev/regulator/regulator.h>
  42 #include <dev/fdt/fdt_common.h>
  43 #include <dev/fdt/fdt_pinctrl.h>
  44 #include <dev/ofw/openfirm.h>
  45 #include <dev/ofw/ofw_bus.h>
  46 #include <dev/ofw/ofw_bus_subr.h>
  47
  48 #include <arm/nvidia/tegra_efuse.h>
  49
  50 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
  51
  52 #include "phynode_if.h"
  53
  54 /* FUSE calibration data. */
  55 #define FUSE_SKU_CALIB_0                        0x0F0
  56 #define   FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(x, i)      (((x) >> (11 + ((i) - 1) * 6)) & 0x3F);
  57 #define   FUSE_SKU_CALIB_0_HS_TERM_RANGE_ADJ(x)         (((x) >>  7) & 0x0F);
  58 #define   FUSE_SKU_CALIB_0_HS_CURR_LEVEL_0(x)           (((x) >>  0) & 0x3F);
  59
  60 #define FUSE_USB_CALIB_EXT_0                    0x250
  61 #define   FUSE_USB_CALIB_EXT_0_RPD_CTRL(x)              (((x) >>  0) & 0x1F);
  62
  63
  64 /* Registers. */
  65 #define XUSB_PADCTL_USB2_PAD_MUX                0x004
  66
  67 #define XUSB_PADCTL_USB2_PORT_CAP               0x008
  68 #define  USB2_PORT_CAP_PORT_REVERSE_ID(p)               (1 << (3 + (p) * 4))
  69 #define  USB2_PORT_CAP_PORT_INTERNAL(p)                 (1 << (2 + (p) * 4))
  70 #define  USB2_PORT_CAP_PORT_CAP(p, x)                   (((x) & 3) << ((p) * 4))
  71 #define   USB2_PORT_CAP_PORT_CAP_OTG                    0x3
  72 #define   USB2_PORT_CAP_PORT_CAP_DEVICE                 0x2
  73 #define   USB2_PORT_CAP_PORT_CAP_HOST                   0x1
  74 #define   USB2_PORT_CAP_PORT_CAP_DISABLED               0x0
  75
  76 #define XUSB_PADCTL_SS_PORT_MAP                 0x014
  77 #define  SS_PORT_MAP_PORT_INTERNAL(p)                   (1 << (3 + (p) * 4))
  78 #define  SS_PORT_MAP_PORT_MAP(p, x)                     (((x) & 7) << ((p) * 4))
  79
  80 #define XUSB_PADCTL_ELPG_PROGRAM1               0x024
  81 #define  ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN           (1 << 31)
  82 #define  ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY       (1 << 30)
  83 #define  ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN             (1 << 29)
  84 #define  ELPG_PROGRAM1_SSP_ELPG_VCORE_DOWN(x)           (1 << (2 + (x) * 3))
  85 #define  ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN_EARLY(x)       (1 << (1 + (x) * 3))
  86 #define  ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN(x)             (1 << (0 + (x) * 3))
  87
  88 #define XUSB_PADCTL_USB3_PAD_MUX                0x028
  89 #define  USB3_PAD_MUX_SATA_IDDQ_DISABLE(x)              (1 << (8 + (x)))
  90 #define  USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x)              (1 << (1 + (x)))
  91
  92 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(x) (0x084 + (x) * 0x40)
  93 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPU_OVRD_VAL (1 << 23)
  94 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPU_OVRD   ( 1 << 22)
  95 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPD_OVRD_VAL (1 << 21)
  96 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPD_OVRD    (1 << 20)
  97 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPU_OVRD_VAL (1 << 19)
  98 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPU_OVRD    (1 << 18)
  99 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPD_OVRD_VAL (1 << 17)
 100 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPD_OVRD    (1 << 16)
 101 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_DYN_DLY(x)   (((x) & 0x3) <<  9)
 102 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(x)       (((x) & 0x3) <<  7)
 103 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18        (1 <<  6)
 104 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_DIV_DET_EN        (1 <<  4)
 105 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_VOP_DIV2P7_DET    (1 <<  3)
 106 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_VOP_DIV2P0_DET    (1 <<  2)
 107 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_VON_DIV2P7_DET    (1 <<  1)
 108 #define  USB2_BATTERY_CHRG_OTGPAD_CTL1_VON_DIV2P0_DET    (1 <<  0)
 109
 110 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0(x)        (0x088 + (x) * 0x40)
 111 #define  USB2_OTG_PAD_CTL0_PD_ZI                        (1 << 29)
 112 #define  USB2_OTG_PAD_CTL0_PD2_OVRD_EN                  (1 << 28)
 113 #define  USB2_OTG_PAD_CTL0_PD2                          (1 << 27)
 114 #define  USB2_OTG_PAD_CTL0_PD                           (1 << 26)
 115 #define  USB2_OTG_PAD_CTL0_TERM_EN                      (1 << 25)
 116 #define  USB2_OTG_PAD_CTL0_LS_FSLEW(x)                  (((x) & 0x0F) << 21)
 117 #define  USB2_OTG_PAD_CTL0_LS_RSLEW(x)                  (((x) & 0x0F) << 17)
 118 #define  USB2_OTG_PAD_CTL0_FS_FSLEW(x)                  (((x) & 0x0F) << 13)
 119 #define  USB2_OTG_PAD_CTL0_FS_RSLEW(x)                  (((x) & 0x0F) <<  9)
 120 #define  USB2_OTG_PAD_CTL0_HS_SLEW(x)                   (((x) & 0x3F) <<  6)
 121 #define  USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(x)             (((x) & 0x3F) <<  0)
 122
 123 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1(x)        (0x08C + (x) * 0x40)
 124 #define  USB2_OTG_PAD_CTL1_RPD_CTRL(x)                  (((x) & 0x1F) <<  26)
 125 #define  USB2_OTG_PAD_CTL1_RPU_STATUS_HIGH              (1 <<  25)
 126 #define  USB2_OTG_PAD_CTL1_RPU_SWITCH_LOW               (1 <<  24)
 127 #define  USB2_OTG_PAD_CTL1_RPU_SWITCH_OVRD              (1 <<  23)
 128 #define  USB2_OTG_PAD_CTL1_HS_LOOPBACK_OVRD_VAL         (1 <<  22)
 129 #define  USB2_OTG_PAD_CTL1_HS_LOOPBACK_OVRD_EN          (1 <<  21)
 130 #define  USB2_OTG_PAD_CTL1_PTERM_RANGE_ADJ(x)           (((x) & 0x0F) << 17)
 131 #define  USB2_OTG_PAD_CTL1_PD_DISC_OVRD_VAL             (1 << 16)
 132 #define  USB2_OTG_PAD_CTL1_PD_CHRP_OVRD_VAL             (1 << 15)
 133 #define  USB2_OTG_PAD_CTL1_RPU_RANGE_ADJ(x)             (((x) & 0x03) << 13)
 134 #define  USB2_OTG_PAD_CTL1_HS_COUP_EN(x)                (((x) & 0x03) << 11)
 135 #define  USB2_OTG_PAD_CTL1_SPARE(x)                     (((x) & 0x0F) <<  7)
 136 #define  USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(x)            (((x) & 0x0F) <<  3)
 137 #define  USB2_OTG_PAD_CTL1_PD_DR                        (1 <<  2)
 138 #define  USB2_OTG_PAD_CTL1_PD_DISC_OVRD                 (1 <<  1)
 139 #define  USB2_OTG_PAD_CTL1_PD_CHRP_OVRD                 (1 <<  0)
 140
 141 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0(x) (0x0C0 + (x) * 0x40)
 142 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0          0x0284
 143 #define  USB2_BIAS_PAD_CTL0_TRK_PWR_ENA                 (1 << 29)
 144 #define  USB2_BIAS_PAD_CTL0_SPARE(x)                    (((x) & 0xF) << 25)
 145 #define  USB2_BIAS_PAD_CTL0_CHG_DIV(x)                  (((x) & 0xF) << 21)
 146 #define  USB2_BIAS_PAD_CTL0_TEMP_COEF(x)                (((x) & 0x7) << 18)
 147 #define  USB2_BIAS_PAD_CTL0_VREF_CTRL(x)                (((x) & 0x7) << 15)
 148 #define  USB2_BIAS_PAD_CTL0_ADJRPU(x)                   (((x) & 0x7) << 12)
 149 #define  USB2_BIAS_PAD_CTL0_PD                          (1 << 11)
 150 #define  USB2_BIAS_PAD_CTL0_TERM_OFFSETL(x)             (((x) & 0x7) <<  8)
 151 #define  USB2_BIAS_PAD_CTL0_HS_CHIRP_LEVEL(x)           (((x) & 0x3) <<  6)
 152 #define  USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(x)          (((x) & 0x7) <<  3)
 153 #define  USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(x)         (((x) & 0x7) <<  0)
 154
 155 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1          0x0288
 156 #define  USB2_BIAS_PAD_CTL1_FORCE_TRK_CLK_EN            (1 << 30)
 157 #define  USB2_BIAS_PAD_CTL1_TRK_SW_OVRD                 (1 << 29)
 158 #define  USB2_BIAS_PAD_CTL1_TRK_DONE                    (1 << 28)
 159 #define  USB2_BIAS_PAD_CTL1_TRK_START                   (1 << 27)
 160 #define  USB2_BIAS_PAD_CTL1_PD_TRK                      (1 << 26)
 161 #define  USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(x)     (((x) & 0x7F) << 19)
 162 #define  USB2_BIAS_PAD_CTL1_TRK_START_TIMER(x)          (((x) & 0x7F) << 12)
 163 #define  USB2_BIAS_PAD_CTL1_PCTRL(x)                    (((x) & 0x3F) <<  6)
 164 #define  USB2_BIAS_PAD_CTL1_TCTRL(x)                    (((x) & 0x3F) <<  0)
 165
 166 #define XUSB_PADCTL_HSIC_PAD_CTL0(x)            (0x300 + (x) * 0x20)
 167 #define  HSIC_PAD_CTL0_RPU_STROBE                       (1 << 18)
 168 #define  HSIC_PAD_CTL0_RPU_DATA1                        (1 << 17)
 169 #define  HSIC_PAD_CTL0_RPU_DATA0                        (1 << 16)
 170 #define  HSIC_PAD_CTL0_RPD_STROBE                       (1 << 15)
 171 #define  HSIC_PAD_CTL0_RPD_DATA1                        (1 << 14)
 172 #define  HSIC_PAD_CTL0_RPD_DATA0                        (1 << 13)
 173 #define  HSIC_PAD_CTL0_LPBK_STROBE                      (1 << 12)
 174 #define  HSIC_PAD_CTL0_LPBK_DATA1                       (1 << 11)
 175 #define  HSIC_PAD_CTL0_LPBK_DATA0                       (1 << 10)
 176 #define  HSIC_PAD_CTL0_PD_ZI_STROBE                     (1 <<  9)
 177 #define  HSIC_PAD_CTL0_PD_ZI_DATA1                      (1 <<  8)
 178 #define  HSIC_PAD_CTL0_PD_ZI_DATA0                      (1 <<  7)
 179 #define  HSIC_PAD_CTL0_PD_RX_STROBE                     (1 <<  6)
 180 #define  HSIC_PAD_CTL0_PD_RX_DATA1                      (1 <<  5)
 181 #define  HSIC_PAD_CTL0_PD_RX_DATA0                      (1 <<  4)
 182 #define  HSIC_PAD_CTL0_PD_TX_STROBE                     (1 <<  3)
 183 #define  HSIC_PAD_CTL0_PD_TX_DATA1                      (1 <<  2)
 184 #define  HSIC_PAD_CTL0_PD_TX_DATA0                      (1 <<  1)
 185 #define  HSIC_PAD_CTL0_IDDQ                             (1 <<  0)
 186
 187 #define XUSB_PADCTL_HSIC_PAD_CTL1(x)            (0x304 + (x) * 0x20)
 188 #define  HSIC_PAD_CTL1_RTERM(x)                         (((x) & 0xF) << 12)
 189 #define  HSIC_PAD_CTL1_HSIC_OPT(x)                      (((x) & 0xF) <<  8)
 190 #define  HSIC_PAD_CTL1_TX_SLEW(x)                       (((x) & 0xF) <<  4)
 191 #define  HSIC_PAD_CTL1_TX_RTUNEP(x)                     (((x) & 0xF) <<  0)
 192
 193 #define XUSB_PADCTL_HSIC_PAD_CTL2(x)            (0x308 + (x) * 0x20)
 194 #define  HSIC_PAD_CTL2_RX_STROBE_TRIM(x)                (((x) & 0xF) <<  8)
 195 #define  HSIC_PAD_CTL2_RX_DATA1_TRIM(x)                 (((x) & 0xF) <<  4)
 196 #define  HSIC_PAD_CTL2_RX_DATA0_TRIM(x)                 (((x) & 0xF) <<  0)
 197
 198 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL            0x340
 199 #define  HSIC_PAD_TRK_CTL_AUTO_RTERM_EN                 (1 << 24)
 200 #define  HSIC_PAD_TRK_CTL_FORCE_TRK_CLK_EN              (1 << 23)
 201 #define  HSIC_PAD_TRK_CTL_TRK_SW_OVRD                   (1 << 22)
 202 #define  HSIC_PAD_TRK_CTL_TRK_DONE                      (1 << 21)
 203 #define  HSIC_PAD_TRK_CTL_TRK_START                     (1 << 20)
 204 #define  HSIC_PAD_TRK_CTL_PD_TRK                        (1 << 19)
 205 #define  HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(x)       (((x) & 0x3F) << 12)
 206 #define  HSIC_PAD_TRK_CTL_TRK_START_TIMER(x)            (((x) & 0x7F) <<  5)
 207 #define  HSIC_PAD_TRK_CTL_RTERM_OUT(x)                  (((x) & 0x1F) <<  0)
 208
 209 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL      0x344
 210
 211 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1            0x360
 212 #define  UPHY_PLL_P0_CTL1_PLL0_FREQ_PSDIV(x)            (((x) & 0x03) << 28)
 213 #define  UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(x)             (((x) & 0xFF) << 20)
 214 #define  UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV(x)             (((x) & 0x03) << 16)
 215 #define  UPHY_PLL_P0_CTL1_PLL0_LOCKDET_STATUS           (1 << 15)
 216 #define  UPHY_PLL_P0_CTL1_PLL0_MODE_GET(x)              (((x) >> 8) & 0x03)
 217 #define  UPHY_PLL_P0_CTL1_PLL0_BYPASS_EN                (1 <<  7)
 218 #define  UPHY_PLL_P0_CTL1_PLL0_FREERUN_EN               (1 <<  6)
 219 #define  UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD                 (1 <<  4)
 220 #define  UPHY_PLL_P0_CTL1_PLL0_ENABLE                   (1 <<  3)
 221 #define  UPHY_PLL_P0_CTL1_PLL0_SLEEP(x)                 (((x) & 0x03) <<  1)
 222 #define  UPHY_PLL_P0_CTL1_PLL0_IDDQ                     (1 << 0)
 223
 224 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2            0x364
 225 #define  UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(x)              (((x) & 0xFFFFFF) << 4)
 226 #define  UPHY_PLL_P0_CTL2_PLL0_CAL_RESET                (1 << 3)
 227 #define  UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD                 (1 << 2)
 228 #define  UPHY_PLL_P0_CTL2_PLL0_CAL_DONE                 (1 << 1)
 229 #define  UPHY_PLL_P0_CTL2_PLL0_CAL_EN                   (1 << 0)
 230
 231 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4            0x36c
 232 #define  UPHY_PLL_P0_CTL4_PLL0_TCLKOUT_EN               (1 << 28)
 233 #define  UPHY_PLL_P0_CTL4_PLL0_CLKDIST_CTRL(x)          (((x) & 0xF) << 20)
 234 #define  UPHY_PLL_P0_CTL4_PLL0_XDIGCLK_EN               (1 << 19)
 235 #define  UPHY_PLL_P0_CTL4_PLL0_XDIGCLK_SEL(x)           (((x) & 0x7) << 16)
 236 #define  UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_EN              (1 << 15)
 237 #define  UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(x)          (((x) & 0x3) << 12)
 238 #define  UPHY_PLL_P0_CTL4_PLL0_FBCLKBUF_EN              (1 <<  9)
 239 #define  UPHY_PLL_P0_CTL4_PLL0_REFCLKBUF_EN             (1 <<  8)
 240 #define  UPHY_PLL_P0_CTL4_PLL0_REFCLK_SEL(x)            (((x) & 0xF) <<  4)
 241 #define  UPHY_PLL_P0_CTL4_PLL0_REFCLK_TERM100           (1 <<  0)
 242
 243 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5            0x370
 244 #define  UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(x)              (((x) & 0xFF) << 16)
 245 #define  UPHY_PLL_P0_CTL5_PLL0_LPF_CTRL(x)              (((x) & 0xFF) <<  8)
 246 #define  UPHY_PLL_P0_CTL5_PLL0_CP_CTRL(x)               (((x) & 0x0F) <<  4)
 247 #define  UPHY_PLL_P0_CTL5_PLL0_PFD_CTRL(x)              (((x) & 0x03) <<  0)
 248
 249 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8            0x37c
 250 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE                (1U << 31)
 251 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_VAL(x)              (((x) & 0x1F) << 24)
 252 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_BYP_EN              (1 << 23)
 253 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_BYP_CODE(x)         (((x) & 0x1F) << 16)
 254 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD                (1 << 15)
 255 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN              (1 << 13)
 256 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_EN                  (1 << 12)
 257 #define  UPHY_PLL_P0_CTL8_PLL0_BGAP_CTRL(x)             (((x) & 0xFFF) <<  0)
 258
 259 #define XUSB_PADCTL_UPHY_MISC_PAD_P_CTL1(x)     (0x460 + (x) * 0x40)
 260 #define XUSB_PADCTL_UPHY_PLL_S0_CTL1            0x860
 261 #define  UPHY_PLL_S0_CTL1_PLL0_FREQ_PSDIV(x)            (((x) & 0x03) << 28)
 262 #define  UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(x)             (((x) & 0xFF) << 20)
 263 #define  UPHY_PLL_S0_CTL1_PLL0_FREQ_MDIV(x)             (((x) & 0x03) << 16)
 264 #define  UPHY_PLL_S0_CTL1_PLL0_LOCKDET_STATUS           (1 << 15)
 265 #define  UPHY_PLL_S0_CTL1_PLL0_MODE_GET(x)              (((x) >> 8) & 0x03)
 266 #define  UPHY_PLL_S0_CTL1_PLL0_BYPASS_EN                (1 <<  7)
 267 #define  UPHY_PLL_S0_CTL1_PLL0_FREERUN_EN               (1 <<  6)
 268 #define  UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD                 (1 <<  4)
 269 #define  UPHY_PLL_S0_CTL1_PLL0_ENABLE                   (1 <<  3)
 270 #define  UPHY_PLL_S0_CTL1_PLL0_SLEEP(x)                 (((x) & 0x03) <<  1)
 271 #define  UPHY_PLL_S0_CTL1_PLL0_IDDQ                     (1 << 0)
 272
 273 #define XUSB_PADCTL_UPHY_PLL_S0_CTL2            0x864
 274 #define  UPHY_PLL_S0_CTL2_PLL0_CAL_CTRL(x)              (((x) & 0xFFFFFF) << 4)
 275 #define  UPHY_PLL_S0_CTL2_PLL0_CAL_RESET                (1 << 3)
 276 #define  UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD                 (1 << 2)
 277 #define  UPHY_PLL_S0_CTL2_PLL0_CAL_DONE                 (1 << 1)
 278 #define  UPHY_PLL_S0_CTL2_PLL0_CAL_EN                   (1 << 0)
 279
 280 #define XUSB_PADCTL_UPHY_PLL_S0_CTL4            0x86c
 281 #define  UPHY_PLL_S0_CTL4_PLL0_TCLKOUT_EN               (1 << 28)
 282 #define  UPHY_PLL_S0_CTL4_PLL0_CLKDIST_CTRL(x)          (((x) & 0xF) << 20)
 283 #define  UPHY_PLL_S0_CTL4_PLL0_XDIGCLK_EN               (1 << 19)
 284 #define  UPHY_PLL_S0_CTL4_PLL0_XDIGCLK_SEL(x)           (((x) & 0x7) << 16)
 285 #define  UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_EN              (1 << 15)
 286 #define  UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(x)          (((x) & 0x3) << 12)
 287 #define  UPHY_PLL_S0_CTL4_PLL0_FBCLKBUF_EN              (1 <<  9)
 288 #define  UPHY_PLL_S0_CTL4_PLL0_REFCLKBUF_EN             (1 <<  8)
 289 #define  UPHY_PLL_S0_CTL4_PLL0_REFCLK_SEL(x)            (((x) & 0xF) <<  4)
 290 #define  UPHY_PLL_S0_CTL4_PLL0_REFCLK_TERM100           (1 <<  0)
 291
 292 #define XUSB_PADCTL_UPHY_PLL_S0_CTL5            0x870
 293 #define  UPHY_PLL_S0_CTL5_PLL0_DCO_CTRL(x)              (((x) & 0xFF) << 16)
 294 #define  UPHY_PLL_S0_CTL5_PLL0_LPF_CTRL(x)              (((x) & 0xFF) <<  8)
 295 #define  UPHY_PLL_S0_CTL5_PLL0_CP_CTRL(x)               (((x) & 0x0F) <<  4)
 296 #define  UPHY_PLL_S0_CTL5_PLL0_PFD_CTRL(x)              (((x) & 0x03) <<  0)
 297
 298 #define XUSB_PADCTL_UPHY_PLL_S0_CTL8            0x87c
 299 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE                (1U << 31)
 300 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_VAL(x)              (((x) & 0x1F) << 24)
 301 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_BYP_EN              (1 << 23)
 302 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_BYP_CODE(x)         (((x) & 0x1F) << 16)
 303 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD                (1 << 15)
 304 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN              (1 << 13)
 305 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_EN                  (1 << 12)
 306 #define  UPHY_PLL_S0_CTL8_PLL0_BGAP_CTRL(x)             (((x) & 0xFFF) <<  0)
 307
 308 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1       0x960
 309 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(x)      (0xa60 + (x) * 0x40)
 310 #define  UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(x)            (((x) & 0x3) << 16)
 311
 312 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(x)      (0xa64 + (x) * 0x40)
 313 #define  UPHY_USB3_PAD_ECTL2_RX_IQ_CTRL(x)              (((x) & 0x000F) << 16)
 314 #define  UPHY_USB3_PAD_ECTL2_RX_CTLE(x)                 (((x) & 0xFFFF) <<  0)
 315
 316 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3(x)      (0xa68 + (x) * 0x40)
 317 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(x)      (0xa6c + (x) * 0x40)
 318 #define  UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(x)             (((x) & 0xFFFF) << 16)
 319 #define  UPHY_USB3_PAD_ECTL4_RX_PI_CTRL(x)              (((x) & 0x00FF) <<  0)
 320
 321 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6(x)      (0xa74 + (x) * 0x40)
 322
 323
 324 #define WR4(_sc, _r, _v)        bus_write_4((_sc)->mem_res, (_r), (_v))
 325 #define RD4(_sc, _r)            bus_read_4((_sc)->mem_res, (_r))
 326
 327
 328 struct padctl_softc {
 329         device_t        dev;
 330         struct resource *mem_res;
 331         hwreset_t       rst;
 332         int             phy_ena_cnt;
 333         int             pcie_ena_cnt;
 334         int             sata_ena_cnt;
 335
 336         /* Fuses calibration data */
 337         /* USB2 */
 338         uint32_t        hs_curr_level[4];
 339         uint32_t        hs_curr_level_offs;     /* Not inited yet, always 0 */
 340         uint32_t        hs_term_range_adj;
 341         uint32_t        rpd_ctrl;
 342
 343         /* HSIC */
 344         uint32_t        rx_strobe_trim;         /* Not inited yet, always 0 */
 345         uint32_t        rx_data0_trim;          /* Not inited yet, always 0 */
 346         uint32_t        rx_data1_trim;          /* Not inited yet, always 0 */
 347         uint32_t        tx_rtune_p;             /* Not inited yet, always 0 */
 348         uint32_t        strobe_trim;            /* Not inited yet, always 0 */
 349 };
 350
 351 static struct ofw_compat_data compat_data[] = {
 352         {"nvidia,tegra210-xusb-padctl", 1},
 353         {NULL,                          0},
 354 };
 355
 356 /* Ports. */
 357 enum padctl_port_type {
 358         PADCTL_PORT_USB2,
 359         PADCTL_PORT_HSIC,
 360         PADCTL_PORT_USB3,
 361 };
 362
 363 struct padctl_lane;
 364 struct padctl_port {
 365         enum padctl_port_type   type;
 366         const char              *name;
 367         const char              *base_name;
 368         int                     idx;
 369         int                     (*init)(struct padctl_softc *sc,
 370                                     struct padctl_port *port);
 371
 372         /* Runtime data. */
 373         phandle_t               xref;
 374         bool                    enabled;
 375         bool                    internal;
 376         uint32_t                companion;
 377         regulator_t             supply_vbus;
 378         struct padctl_lane      *lane;
 379 };
 380
 381 static int usb3_port_init(struct padctl_softc *sc, struct padctl_port *port);
 382
 383 #define PORT(t, n, p, i) {                                              \
 384         .type = t,                                                      \
 385         .name = n "-" #p,                                               \
 386         .base_name = n,                                                 \
 387         .idx = p,                                                       \
 388         .init = i,                                                      \
 389 }
 390 static struct padctl_port ports_tbl[] = {
 391         PORT(PADCTL_PORT_USB2, "usb2", 0, NULL),
 392         PORT(PADCTL_PORT_USB2, "usb2", 1, NULL),
 393         PORT(PADCTL_PORT_USB2, "usb2", 2, NULL),
 394         PORT(PADCTL_PORT_USB2, "usb2", 3, NULL),
 395         PORT(PADCTL_PORT_HSIC, "hsic", 0, NULL),
 396         PORT(PADCTL_PORT_HSIC, "hsic", 1, NULL),
 397         PORT(PADCTL_PORT_USB3, "usb3", 0, usb3_port_init),
 398         PORT(PADCTL_PORT_USB3, "usb3", 1, usb3_port_init),
 399 };
 400
 401 /* Pads - a group of lannes. */
 402 enum padctl_pad_type {
 403         PADCTL_PAD_USB2,
 404         PADCTL_PAD_HSIC,
 405         PADCTL_PAD_PCIE,
 406         PADCTL_PAD_SATA,
 407 };
 408
 409 struct padctl_lane;
 410 struct padctl_pad {
 411         const char              *name;
 412         enum padctl_pad_type    type;
 413         const char              *clock_name;
 414         char                    *reset_name;    /* XXX constify !!!!!! */
 415         int                     (*enable)(struct padctl_softc *sc,
 416                                     struct padctl_lane *lane);
 417         int                     (*disable)(struct padctl_softc *sc,
 418                                     struct padctl_lane *lane);
 419         /* Runtime data. */
 420         bool                    enabled;
 421         clk_t                   clk;
 422         hwreset_t               reset;
 423         int                     nlanes;
 424         struct padctl_lane      *lanes[8];      /* Safe maximum value. */
 425 };
 426
 427 static int usb2_enable(struct padctl_softc *sc, struct padctl_lane *lane);
 428 static int usb2_disable(struct padctl_softc *sc, struct padctl_lane *lane);
 429 static int hsic_enable(struct padctl_softc *sc, struct padctl_lane *lane);
 430 static int hsic_disable(struct padctl_softc *sc, struct padctl_lane *lane);
 431 static int pcie_enable(struct padctl_softc *sc, struct padctl_lane *lane);
 432 static int pcie_disable(struct padctl_softc *sc, struct padctl_lane *lane);
 433 static int sata_enable(struct padctl_softc *sc, struct padctl_lane *lane);
 434 static int sata_disable(struct padctl_softc *sc, struct padctl_lane *lane);
 435
 436 #define PAD(n, t, cn, rn, e, d) {                                               \
 437         .name = n,                                                      \
 438         .type = t,                                                      \
 439         .clock_name = cn,                                               \
 440         .reset_name = rn,                                               \
 441         .enable = e,                                                    \
 442         .disable = d,                                                   \
 443 }
 444 static struct padctl_pad pads_tbl[] = {
 445         PAD("usb2", PADCTL_PAD_USB2, "trk",  NULL, usb2_enable, usb2_disable),
 446         PAD("hsic", PADCTL_PAD_HSIC, "trk",  NULL, hsic_enable, hsic_disable),
 447         PAD("pcie", PADCTL_PAD_PCIE, "pll", "phy", pcie_enable, pcie_disable),
 448         PAD("sata", PADCTL_PAD_SATA, "pll", "phy", sata_enable, sata_disable),
 449 };
 450
 451 /* Lanes. */
 452 static char *usb_mux[] = {"snps", "xusb", "uart", "rsvd"};
 453 static char *hsic_mux[] = {"snps", "xusb"};
 454 static char *pci_mux[] = {"pcie-x1", "usb3-ss", "sata", "pcie-x4"};
 455
 456 struct padctl_lane {
 457         const char              *name;
 458         int                     idx;
 459         bus_size_t              reg;
 460         uint32_t                shift;
 461         uint32_t                mask;
 462         char                    **mux;
 463         int                     nmux;
 464         /* Runtime data. */
 465         bool                    enabled;
 466         phandle_t               xref;
 467         struct padctl_pad       *pad;
 468         struct padctl_port      *port;
 469         int                     mux_idx;
 470
 471 };
 472
 473 #define LANE(n, p, r, s, m, mx) {                                       \
 474         .name = n "-" #p,                                               \
 475         .idx = p,                                                       \
 476         .reg = r,                                                       \
 477         .shift = s,                                                     \
 478         .mask = m,                                                      \
 479         .mux = mx,                                                      \
 480         .nmux = nitems(mx),                                             \
 481 }
 482 static struct padctl_lane lanes_tbl[] = {
 483         LANE("usb2", 0, XUSB_PADCTL_USB2_PAD_MUX,  0, 0x3, usb_mux),
 484         LANE("usb2", 1, XUSB_PADCTL_USB2_PAD_MUX,  2, 0x3, usb_mux),
 485         LANE("usb2", 2, XUSB_PADCTL_USB2_PAD_MUX,  4, 0x3, usb_mux),
 486         LANE("usb2", 3, XUSB_PADCTL_USB2_PAD_MUX,  6, 0x3, usb_mux),
 487         LANE("hsic", 0, XUSB_PADCTL_USB2_PAD_MUX, 14, 0x1, hsic_mux),
 488         LANE("hsic", 1, XUSB_PADCTL_USB2_PAD_MUX, 15, 0x1, hsic_mux),
 489         LANE("pcie", 0, XUSB_PADCTL_USB3_PAD_MUX, 12, 0x3, pci_mux),
 490         LANE("pcie", 1, XUSB_PADCTL_USB3_PAD_MUX, 14, 0x3, pci_mux),
 491         LANE("pcie", 2, XUSB_PADCTL_USB3_PAD_MUX, 16, 0x3, pci_mux),
 492         LANE("pcie", 3, XUSB_PADCTL_USB3_PAD_MUX, 18, 0x3, pci_mux),
 493         LANE("pcie", 4, XUSB_PADCTL_USB3_PAD_MUX, 20, 0x3, pci_mux),
 494         LANE("pcie", 5, XUSB_PADCTL_USB3_PAD_MUX, 22, 0x3, pci_mux),
 495         LANE("pcie", 6, XUSB_PADCTL_USB3_PAD_MUX, 24, 0x3, pci_mux),
 496         LANE("sata", 0, XUSB_PADCTL_USB3_PAD_MUX, 30, 0x3, pci_mux),
 497 };
 498
 499 /* Define all possible mappings for USB3 port lanes */
 500 struct padctl_lane_map {
 501         int                     port_idx;
 502         enum padctl_pad_type    pad_type;
 503         int                     lane_idx;
 504 };
 505
 506 #define LANE_MAP(pi, pt, li) {                                          \
 507         .port_idx = pi,                                                 \
 508         .pad_type = pt,                                                 \
 509         .lane_idx = li,                                                 \
 510 }
 511 static struct padctl_lane_map lane_map_tbl[] = {
 512         LANE_MAP(0, PADCTL_PAD_PCIE, 6),        /* port USB3-0 -> lane PCIE-0 */
 513         LANE_MAP(1, PADCTL_PAD_PCIE, 5),        /* port USB3-1 -> lane PCIE-1 */
 514         LANE_MAP(2, PADCTL_PAD_PCIE, 0),        /* port USB3-2 -> lane PCIE-0 */
 515         LANE_MAP(2, PADCTL_PAD_PCIE, 2),        /* port USB3-2 -> lane PCIE-2 */
 516         LANE_MAP(3, PADCTL_PAD_PCIE, 4),        /* port USB3-3 -> lane PCIE-4 */
 517 };
 518
 519 /* Phy class and methods. */
 520 static int xusbpadctl_phy_enable(struct phynode *phy, bool enable);
 521 static phynode_method_t xusbpadctl_phynode_methods[] = {
 522         PHYNODEMETHOD(phynode_enable,   xusbpadctl_phy_enable),
 523         PHYNODEMETHOD_END
 524
 525 };
 526 DEFINE_CLASS_1(xusbpadctl_phynode, xusbpadctl_phynode_class,
 527     xusbpadctl_phynode_methods, 0, phynode_class);
 528
 529 static struct padctl_port *search_lane_port(struct padctl_softc *sc,
 530     struct padctl_lane *lane);
 531
 532
 533 static void tegra210_xusb_pll_hw_control_enable(void) {}
 534 static void tegra210_xusb_pll_hw_sequence_start(void) {}
 535 static void tegra210_sata_pll_hw_control_enable(void) {}
 536 static void tegra210_sata_pll_hw_sequence_start(void) {}
 537
 538 /* -------------------------------------------------------------------------
 539  *
 540  *   PEX functions
 541  */
 542 static int
 543 uphy_pex_enable(struct padctl_softc *sc, struct padctl_pad *pad)
 544 {
 545         uint32_t reg;
 546         int rv, i;
 547
 548         if (sc->pcie_ena_cnt > 0) {
 549                 sc->pcie_ena_cnt++;
 550                 return (0);
 551         }
 552
 553         /* 22.8.4 UPHY PLLs, Step 4, page 1346 */
 554         /* 1. Deassert PLL/Lane resets. */
 555         rv = clk_enable(pad->clk);
 556         if (rv < 0) {
 557                 device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n",
 558                     pad->name, rv);
 559                 return (rv);
 560         }
 561
 562         rv = hwreset_deassert(pad->reset);
 563         if (rv < 0) {
 564                 device_printf(sc->dev, "Cannot unreset pad '%s': %d\n",
 565                     pad->name, rv);
 566                 clk_disable(pad->clk);
 567                 return (rv);
 568         }
 569
 570         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 571         reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0);
 572         reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136);
 573         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
 574
 575         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
 576         reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0);
 577         reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a);
 578         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg);
 579
 580         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 581         reg |= UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD;
 582         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
 583
 584         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 585         reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD;
 586         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
 587
 588         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 589         reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD;
 590         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
 591
 592         /*
 593          * 2. For the following registers, default values
 594          *    take care of the desired frequency.
 595          */
 596         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 597         reg &= ~UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(~0);
 598         reg &= ~UPHY_PLL_P0_CTL4_PLL0_REFCLK_SEL(~0);
 599         reg |= UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(0x2);
 600         reg |= UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_EN;
 601         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg);
 602
 603         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 604         reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV(~0);
 605         reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(~0);
 606         reg |= UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(0x19);
 607         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
 608
 609         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 610         reg &= ~UPHY_PLL_P0_CTL1_PLL0_IDDQ;
 611         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
 612
 613         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 614         reg &= ~UPHY_PLL_P0_CTL1_PLL0_SLEEP(~0);
 615         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
 616
 617         /* 3. Wait 100 ns. */
 618         DELAY(10);
 619
 620         /* XXX This in not in TRM */
 621         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 622         reg |= UPHY_PLL_P0_CTL4_PLL0_REFCLKBUF_EN;
 623         WR4(sc,  XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg);
 624
 625         /* 4. Calibration. */
 626         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 627         reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_EN;
 628         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
 629         for (i = 30; i > 0; i--) {
 630                 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 631                 if (reg & UPHY_PLL_P0_CTL2_PLL0_CAL_DONE)
 632                         break;
 633                 DELAY(10);
 634         }
 635         if (i <= 0) {
 636                 device_printf(sc->dev, "Timedout in calibration step 1 "
 637                     "for pad '%s' (0x%08X).\n", pad->name, reg);
 638                 rv = ETIMEDOUT;
 639                 goto err;
 640         }
 641
 642         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 643         reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_EN;
 644         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
 645         for (i = 10; i > 0; i--) {
 646                 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 647                 if ((reg & UPHY_PLL_P0_CTL2_PLL0_CAL_DONE) == 0)
 648                         break;
 649                 DELAY(10);
 650         }
 651         if (i <= 0) {
 652                 device_printf(sc->dev, "Timedout in calibration step 2 "
 653                     "for pad '%s'.\n", pad->name);
 654                 rv = ETIMEDOUT;
 655                 goto err;
 656         }
 657
 658         /* 5. Enable the PLL (20 μs Lock time) */
 659         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 660         reg |= UPHY_PLL_P0_CTL1_PLL0_ENABLE;
 661         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
 662         for (i = 10; i > 0; i--) {
 663                 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 664                 if (reg & UPHY_PLL_P0_CTL1_PLL0_LOCKDET_STATUS)
 665                         break;
 666                 DELAY(10);
 667         }
 668         if (i <= 0) {
 669                 device_printf(sc->dev, "Timedout while enabling PLL "
 670                     "for pad '%s'.\n", pad->name);
 671                 rv = ETIMEDOUT;
 672                 goto err;
 673         }
 674
 675         /* 6. RCAL. */
 676         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 677         reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_EN;
 678         reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN;
 679         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
 680
 681         for (i = 10; i > 0; i--) {
 682                 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 683                 if (reg & UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE)
 684                         break;
 685                 DELAY(10);
 686         }
 687         if (i <= 0) {
 688                 device_printf(sc->dev, "Timedout in RX calibration step 1 "
 689                     "for pad '%s'.\n", pad->name);
 690                 rv = ETIMEDOUT;
 691                 goto err;
 692         }
 693
 694         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 695         reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_EN;
 696         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
 697
 698         for (i = 10; i > 0; i--) {
 699                 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 700                 if (!(reg & UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE))
 701                         break;
 702
 703                 DELAY(10);
 704         }
 705         if (i <= 0) {
 706                 device_printf(sc->dev, "Timedout in RX calibration step 2 "
 707                     "for pad '%s'.\n", pad->name);
 708                 rv = ETIMEDOUT;
 709                 goto err;
 710         }
 711
 712         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 713         reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN;
 714         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
 715
 716         /* Enable Hardware Power Sequencer. */
 717         tegra210_xusb_pll_hw_control_enable();
 718
 719         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 720         reg &= ~UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD;
 721         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
 722
 723         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 724         reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD;
 725         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
 726
 727         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 728         reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD;
 729         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
 730
 731         DELAY(50);
 732
 733         tegra210_xusb_pll_hw_sequence_start();
 734
 735         sc->pcie_ena_cnt++;
 736
 737         return (0);
 738
 739 err:
 740         hwreset_deassert(pad->reset);
 741         clk_disable(pad->clk);
 742         return (rv);
 743 }
 744
 745 static void
 746 uphy_pex_disable(struct padctl_softc *sc, struct padctl_pad *pad)
 747 {
 748         int rv;
 749
 750         sc->pcie_ena_cnt--;
 751         if (sc->pcie_ena_cnt <= 0) {
 752                 rv = hwreset_assert(pad->reset);
 753                 if (rv != 0) {
 754                         device_printf(sc->dev, "Cannot reset pad '%s': %d\n",
 755                             pad->name, rv);
 756                 }
 757                 rv = clk_disable(pad->clk);
 758                 if (rv != 0) {
 759                         device_printf(sc->dev,
 760                             "Cannot dicable clock for pad '%s': %d\n",
 761                             pad->name, rv);
 762                 }
 763         }
 764 }
 765
 766 static int
 767 uphy_sata_enable(struct padctl_softc *sc, struct padctl_pad *pad, bool usb)
 768 {
 769         uint32_t reg;
 770         int rv, i;
 771
 772         /* 22.8.4 UPHY PLLs, Step 4, page 1346 */
 773         /* 1. Deassert PLL/Lane resets. */
 774         if (sc->sata_ena_cnt > 0) {
 775                 sc->sata_ena_cnt++;
 776                 return (0);
 777         }
 778
 779         rv = clk_enable(pad->clk);
 780         if (rv < 0) {
 781                 device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n",
 782                     pad->name, rv);
 783                 return (rv);
 784         }
 785
 786         rv = hwreset_deassert(pad->reset);
 787         if (rv < 0) {
 788                 device_printf(sc->dev, "Cannot unreset pad '%s': %d\n",
 789                     pad->name, rv);
 790                 clk_disable(pad->clk);
 791                 return (rv);
 792         }
 793         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 794         reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0);
 795         reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136);
 796         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
 797
 798         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
 799         reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0);
 800         reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a);
 801         WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg);
 802
 803         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 804         reg |= UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD;
 805         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
 806
 807         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 808         reg |= UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD;
 809         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
 810
 811         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 812         reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD;
 813         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
 814
 815         /*
 816          * 2. For the following registers, default values
 817          *    take care of the desired frequency.
 818          */
 819          reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
 820         reg &= ~UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(~0);
 821         reg &= ~UPHY_PLL_S0_CTL4_PLL0_REFCLK_SEL(~0);
 822         reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_EN;
 823
 824         if (usb)
 825                 reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(0x2);
 826         else
 827                 reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(0x0);
 828
 829         /* XXX PLL0_XDIGCLK_EN */
 830         /*
 831         value &= ~(1 << 19);
 832         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4, reg);
 833         */
 834
 835         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 836         reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_MDIV(~0);
 837         reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(~0);
 838         if (usb)
 839                 reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x19);
 840         else
 841                 reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x1e);
 842         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
 843
 844         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 845         reg &= ~UPHY_PLL_S0_CTL1_PLL0_IDDQ;
 846         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
 847
 848         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 849         reg &= ~UPHY_PLL_S0_CTL1_PLL0_SLEEP(~0);
 850         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
 851
 852         /* 3. Wait 100 ns. */
 853         DELAY(1);
 854
 855         /* XXX This in not in TRM */
 856         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
 857         reg |= UPHY_PLL_S0_CTL4_PLL0_REFCLKBUF_EN;
 858         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4, reg);
 859
 860         /* 4. Calibration. */
 861         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 862         reg |= UPHY_PLL_S0_CTL2_PLL0_CAL_EN;
 863         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
 864         for (i = 30; i > 0; i--) {
 865                 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 866                 if (reg & UPHY_PLL_S0_CTL2_PLL0_CAL_DONE)
 867                         break;
 868                 DELAY(10);
 869         }
 870         if (i <= 0) {
 871                 device_printf(sc->dev, "Timedout in calibration step 1 "
 872                     "for pad '%s'.\n", pad->name);
 873                 rv = ETIMEDOUT;
 874                 goto err;
 875         }
 876
 877         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 878         reg &= ~UPHY_PLL_S0_CTL2_PLL0_CAL_EN;
 879         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
 880         for (i = 10; i > 0; i--) {
 881                 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 882                 if ((reg & UPHY_PLL_S0_CTL2_PLL0_CAL_DONE) == 0)
 883                         break;
 884                 DELAY(10);
 885         }
 886         if (i <= 0) {
 887                 device_printf(sc->dev, "Timedout in calibration step 2 "
 888                     "for pad '%s'.\n", pad->name);
 889                 rv = ETIMEDOUT;
 890                 goto err;
 891         }
 892
 893         /* 5. Enable the PLL (20 μs Lock time) */
 894         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 895         reg |= UPHY_PLL_S0_CTL1_PLL0_ENABLE;
 896         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
 897         for (i = 10; i > 0; i--) {
 898                 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 899                 if (reg & UPHY_PLL_S0_CTL1_PLL0_LOCKDET_STATUS)
 900                         break;
 901                 DELAY(10);
 902         }
 903         if (i <= 0) {
 904                 device_printf(sc->dev, "Timedout while enabling PLL "
 905                     "for pad '%s'.\n", pad->name);
 906                 rv = ETIMEDOUT;
 907                 goto err;
 908         }
 909
 910         /* 6. RCAL. */
 911         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 912         reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_EN;
 913         reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN;
 914         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
 915         for (i = 10; i > 0; i--) {
 916                 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 917                 if (reg & UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE)
 918                         break;
 919                 DELAY(10);
 920         }
 921         if (i <= 0) {
 922                 device_printf(sc->dev, "Timedout in RX calibration step 1 "
 923                     "for pad '%s'.\n", pad->name);
 924                 rv = ETIMEDOUT;
 925                 goto err;
 926         }
 927
 928         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 929         reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_EN;
 930         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
 931         for (i = 10; i > 0; i--) {
 932                 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 933                 if (!(reg & UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE))
 934                         break;
 935                 DELAY(10);
 936         }
 937         if (i <= 0) {
 938                 device_printf(sc->dev, "Timedout in RX calibration step 2 "
 939                     "for pad '%s'.\n", pad->name);
 940                 rv = ETIMEDOUT;
 941                 goto err;
 942         }
 943
 944         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 945         reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN;
 946         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
 947
 948         /* Enable Hardware Power Sequencer. */
 949         tegra210_sata_pll_hw_control_enable();
 950
 951         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 952         reg &= ~UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD;
 953         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
 954
 955         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 956         reg &= ~UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD;
 957         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
 958
 959         reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 960         reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD;
 961         WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
 962
 963         DELAY(50);
 964
 965         tegra210_sata_pll_hw_sequence_start();
 966
 967         sc->sata_ena_cnt++;
 968
 969         return (0);
 970
 971 err:
 972         hwreset_deassert(pad->reset);
 973         clk_disable(pad->clk);
 974         return (rv);
 975 }
 976
 977 static void
 978 uphy_sata_disable(struct padctl_softc *sc, struct padctl_pad *pad)
 979 {
 980         int rv;
 981
 982         sc->sata_ena_cnt--;
 983         if (sc->sata_ena_cnt <= 0) {
 984                 rv = hwreset_assert(pad->reset);
 985                 if (rv != 0) {
 986                         device_printf(sc->dev, "Cannot reset pad '%s': %d\n",
 987                             pad->name, rv);
 988                 }
 989                 rv = clk_disable(pad->clk);
 990                 if (rv != 0) {
 991                         device_printf(sc->dev,
 992                             "Cannot dicable clock for pad '%s': %d\n",
 993                             pad->name, rv);
 994                 }
 995         }
 996 }
 997
 998
 999 static int
1000 usb3_port_init(struct padctl_softc *sc, struct padctl_port *port)
1001 {
1002         uint32_t reg;
1003         struct padctl_pad *pad;
1004         int rv;
1005
1006         pad = port->lane->pad;
1007         reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP);
1008         if (port->internal)
1009                 reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx);
1010         else
1011                 reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx);
1012         reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0);
1013         reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion);
1014         WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);
1015
1016         if (port->supply_vbus != NULL) {
1017                 rv = regulator_enable(port->supply_vbus);
1018                 if (rv != 0) {
1019                         device_printf(sc->dev,
1020                             "Cannot enable vbus regulator\n");
1021                         return (rv);
1022                 }
1023         }
1024
1025         reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx));
1026         reg &= ~UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(~0);
1027         reg |= UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(2);
1028         WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx), reg);
1029
1030         reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx));
1031         reg &= ~UPHY_USB3_PAD_ECTL2_RX_CTLE(~0);
1032         reg |= UPHY_USB3_PAD_ECTL2_RX_CTLE(0x00fc);
1033         WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx), reg);
1034
1035         WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3(port->idx), 0xc0077f1f);
1036
1037         reg = RD4(sc,  XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx));
1038         reg &= ~UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(~0);
1039         reg |= UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(0x01c7);
1040         WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx), reg);
1041
1042         WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6(port->idx), 0xfcf01368);
1043
1044         if (pad->type == PADCTL_PAD_SATA)
1045                 rv = uphy_sata_enable(sc, pad, true);
1046         else
1047                 rv = uphy_pex_enable(sc, pad);
1048         if (rv != 0)
1049                 return (rv);
1050
1051         reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1052         reg &= ~ELPG_PROGRAM1_SSP_ELPG_VCORE_DOWN(port->idx);
1053         WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1054         DELAY(100);
1055
1056         reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1057         reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN_EARLY(port->idx);
1058         WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1059         DELAY(100);
1060
1061         reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1062         reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN(port->idx);
1063         WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1064         DELAY(100);
1065
1066         return (0);
1067 }
1068
1069 static int
1070 pcie_enable(struct padctl_softc *sc, struct padctl_lane *lane)
1071 {
1072         uint32_t reg;
1073         int rv;
1074
1075         rv = uphy_pex_enable(sc, lane->pad);
1076         if (rv != 0)
1077                 return (rv);
1078
1079         reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
1080         reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);
1081         WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
1082
1083         return (0);
1084 }
1085
1086 static int
1087 pcie_disable(struct padctl_softc *sc, struct padctl_lane *lane)
1088 {
1089         uint32_t reg;
1090
1091         reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
1092         reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);
1093         WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
1094
1095         uphy_pex_disable(sc, lane->pad);
1096
1097         return (0);
1098
1099 }
1100
1101 static int
1102 sata_enable(struct padctl_softc *sc, struct padctl_lane *lane)
1103 {
1104         uint32_t reg;
1105         int rv;
1106
1107         rv = uphy_sata_enable(sc, lane->pad, false);
1108         if (rv != 0)
1109                 return (rv);
1110
1111         reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
1112         reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx);
1113         WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
1114
1115         return (0);
1116 }
1117
1118 static int
1119 sata_disable(struct padctl_softc *sc, struct padctl_lane *lane)
1120 {
1121         uint32_t reg;
1122
1123         reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
1124         reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx);
1125         WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
1126
1127         uphy_sata_disable(sc, lane->pad);
1128
1129         return (0);
1130 }
1131
1132 static int
1133 hsic_enable(struct padctl_softc *sc, struct padctl_lane *lane)
1134 {
1135         uint32_t reg;
1136         struct padctl_pad *pad;
1137         struct padctl_port *port;
1138         int rv;
1139
1140         port = search_lane_port(sc, lane);
1141         if (port == NULL) {
1142                 device_printf(sc->dev, "Cannot find port for lane: %s\n",
1143                     lane->name);
1144         }
1145         pad = lane->pad;
1146
1147         if (port->supply_vbus != NULL) {
1148                 rv = regulator_enable(port->supply_vbus);
1149                 if (rv != 0) {
1150                         device_printf(sc->dev,
1151                             "Cannot enable vbus regulator\n");
1152                         return (rv);
1153                 }
1154         }
1155
1156         WR4(sc, XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL, sc->strobe_trim);
1157
1158         reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx));
1159         reg &= ~HSIC_PAD_CTL1_TX_RTUNEP(~0);
1160         reg |= HSIC_PAD_CTL1_TX_RTUNEP(sc->tx_rtune_p);
1161         WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg);
1162
1163         reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx));
1164         reg &= ~HSIC_PAD_CTL2_RX_STROBE_TRIM(~0);
1165         reg &= ~HSIC_PAD_CTL2_RX_DATA1_TRIM(~0);
1166         reg &= ~HSIC_PAD_CTL2_RX_DATA0_TRIM(~0);
1167         reg |= HSIC_PAD_CTL2_RX_STROBE_TRIM(sc->rx_strobe_trim);
1168         reg |= HSIC_PAD_CTL2_RX_DATA1_TRIM(sc->rx_data1_trim);
1169         reg |= HSIC_PAD_CTL2_RX_DATA0_TRIM(sc->rx_data0_trim);
1170         WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx), reg);
1171
1172         reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx));
1173         reg &= ~HSIC_PAD_CTL0_RPU_DATA0;
1174         reg &= ~HSIC_PAD_CTL0_RPU_DATA1;
1175         reg &= ~HSIC_PAD_CTL0_RPU_STROBE;
1176         reg &= ~HSIC_PAD_CTL0_PD_RX_DATA0;
1177         reg &= ~HSIC_PAD_CTL0_PD_RX_DATA1;
1178         reg &= ~HSIC_PAD_CTL0_PD_RX_STROBE;
1179         reg &= ~HSIC_PAD_CTL0_PD_ZI_DATA0;
1180         reg &= ~HSIC_PAD_CTL0_PD_ZI_DATA1;
1181         reg &= ~HSIC_PAD_CTL0_PD_ZI_STROBE;
1182         reg &= ~HSIC_PAD_CTL0_PD_TX_DATA0;
1183         reg &= ~HSIC_PAD_CTL0_PD_TX_DATA1;
1184         reg &= ~HSIC_PAD_CTL0_PD_TX_STROBE;
1185         reg |= HSIC_PAD_CTL0_RPD_DATA0;
1186         reg |= HSIC_PAD_CTL0_RPD_DATA1;
1187         reg |= HSIC_PAD_CTL0_RPD_STROBE;
1188         WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx), reg);
1189
1190         rv = clk_enable(pad->clk);
1191         if (rv < 0) {
1192                 device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n",
1193                     pad->name, rv);
1194                 if (port->supply_vbus != NULL)
1195                         regulator_disable(port->supply_vbus);
1196                 return (rv);
1197         }
1198
1199         reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1200         reg &= ~HSIC_PAD_TRK_CTL_TRK_START_TIMER(~0);
1201         reg &= ~HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(~0);
1202         reg |= HSIC_PAD_TRK_CTL_TRK_START_TIMER(0x1e);
1203         reg |= HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(0x0a);
1204         WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg);
1205
1206         DELAY(10);
1207
1208         reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1209         reg &= ~HSIC_PAD_TRK_CTL_PD_TRK;
1210         WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg);
1211
1212         DELAY(50);
1213         clk_disable(pad->clk);
1214         return (0);
1215 }
1216
1217 static int
1218 hsic_disable(struct padctl_softc *sc, struct padctl_lane *lane)
1219 {
1220         uint32_t reg;
1221         struct padctl_port *port;
1222         int rv;
1223
1224         port = search_lane_port(sc, lane);
1225         if (port == NULL) {
1226                 device_printf(sc->dev, "Cannot find port for lane: %s\n",
1227                     lane->name);
1228         }
1229
1230         reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx));
1231         reg |= HSIC_PAD_CTL0_PD_RX_DATA0;
1232         reg |= HSIC_PAD_CTL0_PD_RX_DATA1;
1233         reg |= HSIC_PAD_CTL0_PD_RX_STROBE;
1234         reg |= HSIC_PAD_CTL0_PD_ZI_DATA0;
1235         reg |= HSIC_PAD_CTL0_PD_ZI_DATA1;
1236         reg |= HSIC_PAD_CTL0_PD_ZI_STROBE;
1237         reg |= HSIC_PAD_CTL0_PD_TX_DATA0;
1238         reg |= HSIC_PAD_CTL0_PD_TX_DATA1;
1239         reg |= HSIC_PAD_CTL0_PD_TX_STROBE;
1240         WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg);
1241
1242         if (port->supply_vbus != NULL) {
1243                 rv = regulator_disable(port->supply_vbus);
1244                 if (rv != 0) {
1245                         device_printf(sc->dev,
1246                             "Cannot disable vbus regulator\n");
1247                         return (rv);
1248                 }
1249         }
1250
1251         return (0);
1252 }
1253
1254 static int
1255 usb2_enable(struct padctl_softc *sc, struct padctl_lane *lane)
1256 {
1257         uint32_t reg;
1258         struct padctl_pad *pad;
1259         struct padctl_port *port;
1260         int rv;
1261
1262         port = search_lane_port(sc, lane);
1263         if (port == NULL) {
1264                 device_printf(sc->dev, "Cannot find port for lane: %s\n",
1265                     lane->name);
1266         }
1267         pad = lane->pad;
1268
1269         reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1270         reg &= ~USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(~0);
1271         reg &= ~USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(~0);
1272         reg |= USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(0x7);
1273         WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
1274
1275         reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP);
1276         reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0);
1277         reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST);
1278         WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg);
1279
1280         reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx));
1281         reg &= ~USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(~0);
1282         reg &= ~USB2_OTG_PAD_CTL0_HS_SLEW(~0);
1283         reg &= ~USB2_OTG_PAD_CTL0_PD;
1284         reg &= ~USB2_OTG_PAD_CTL0_PD2;
1285         reg &= ~USB2_OTG_PAD_CTL0_PD_ZI;
1286         reg |= USB2_OTG_PAD_CTL0_HS_SLEW(14);
1287         reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level[lane->idx] +
1288             sc->hs_curr_level_offs);
1289         WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg);
1290
1291         reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx));
1292         reg &= ~USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(~0);
1293         reg &= ~USB2_OTG_PAD_CTL1_RPD_CTRL(~0);
1294         reg &= ~USB2_OTG_PAD_CTL1_PD_DR;
1295         reg &= ~USB2_OTG_PAD_CTL1_PD_CHRP_OVRD;
1296         reg &= ~USB2_OTG_PAD_CTL1_PD_DISC_OVRD;
1297         reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj);
1298         reg |= USB2_OTG_PAD_CTL1_RPD_CTRL(sc->rpd_ctrl);
1299         WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg);
1300
1301         reg = RD4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx));
1302         reg &= ~USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(~0);
1303         reg |= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;
1304         WR4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx), reg);
1305
1306         if (port->supply_vbus != NULL) {
1307                 rv = regulator_enable(port->supply_vbus);
1308                 if (rv != 0) {
1309                         device_printf(sc->dev,
1310                             "Cannot enable vbus regulator\n");
1311                         return (rv);
1312                 }
1313         }
1314         rv = clk_enable(pad->clk);
1315         if (rv < 0) {
1316                 device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n",
1317                     pad->name, rv);
1318                 if (port->supply_vbus != NULL)
1319                         regulator_disable(port->supply_vbus);
1320                 return (rv);
1321         }
1322         reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1323         reg &= ~USB2_BIAS_PAD_CTL1_TRK_START_TIMER(~0);
1324         reg &= ~USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(~0);
1325         reg |= USB2_BIAS_PAD_CTL1_TRK_START_TIMER(0x1e);
1326         reg |= USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(0x0a);
1327         WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, reg);
1328
1329         reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1330         reg &= ~USB2_BIAS_PAD_CTL0_PD;
1331         WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
1332         return (0);
1333 }
1334
1335 static int
1336 usb2_disable(struct padctl_softc *sc, struct padctl_lane *lane)
1337 {
1338         uint32_t reg;
1339         struct padctl_pad *pad;
1340         struct padctl_port *port;
1341         int rv;
1342
1343         port = search_lane_port(sc, lane);
1344         if (port == NULL) {
1345                 device_printf(sc->dev, "Cannot find port for lane: %s\n",
1346                     lane->name);
1347         }
1348         pad = lane->pad;
1349
1350         reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1351         reg |= USB2_BIAS_PAD_CTL0_PD;
1352         WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
1353
1354         if (port->supply_vbus != NULL) {
1355                 rv = regulator_disable(port->supply_vbus);
1356                 if (rv != 0) {
1357                         device_printf(sc->dev,
1358                             "Cannot disable vbus regulator\n");
1359                         return (rv);
1360                 }
1361         }
1362
1363         rv = clk_disable(pad->clk);
1364         if (rv < 0) {
1365                 device_printf(sc->dev, "Cannot disable clock for pad '%s': %d\n",
1366                     pad->name, rv);
1367                 return (rv);
1368         }
1369
1370         return (0);
1371 }
1372
1373
1374 static int
1375 pad_common_enable(struct padctl_softc *sc)
1376 {
1377         uint32_t reg;
1378
1379         reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1380         reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
1381         WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1382         DELAY(100);
1383
1384         reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1385         reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
1386         WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1387         DELAY(100);
1388
1389         reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1390         reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
1391         WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1392         DELAY(100);
1393
1394         return (0);
1395 }
1396
1397 static int
1398 pad_common_disable(struct padctl_softc *sc)
1399 {
1400         uint32_t reg;
1401
1402         reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1403         reg |= ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
1404         WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1405         DELAY(100);
1406
1407         reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1408         reg |= ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
1409         WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1410         DELAY(100);
1411
1412         reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1413         reg |= ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
1414         WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1415         DELAY(100);
1416
1417         return (0);
1418 }
1419
1420 static int
1421 xusbpadctl_phy_enable(struct phynode *phy, bool enable)
1422 {
1423         device_t dev;
1424         intptr_t id;
1425         struct padctl_softc *sc;
1426         struct padctl_lane *lane;
1427         struct padctl_pad *pad;
1428         int rv;
1429
1430         dev = phynode_get_device(phy);
1431         id = phynode_get_id(phy);
1432         sc = device_get_softc(dev);
1433
1434         if (id < 0 || id >= nitems(lanes_tbl)) {
1435                 device_printf(dev, "Unknown phy: %d\n", (int)id);
1436                 return (ENXIO);
1437         }
1438
1439         lane = lanes_tbl + id;
1440         if (!lane->enabled) {
1441                 device_printf(dev, "Lane is not enabled/configured: %s\n",
1442                     lane->name);
1443                 return (ENXIO);
1444         }
1445
1446         pad = lane->pad;
1447         if (enable) {
1448                 if (sc->phy_ena_cnt == 0) {
1449                         rv = pad_common_enable(sc);
1450                         if (rv != 0)
1451                                 return (rv);
1452                 }
1453                 sc->phy_ena_cnt++;
1454         }
1455
1456         if (enable)
1457                 rv = pad->enable(sc, lane);
1458         else
1459                 rv = pad->disable(sc, lane);
1460         if (rv != 0)
1461                 return (rv);
1462
1463         if (!enable) {
1464                  if (sc->phy_ena_cnt == 1) {
1465                         rv = pad_common_disable(sc);
1466                         if (rv != 0)
1467                                 return (rv);
1468                 }
1469                 sc->phy_ena_cnt--;
1470         }
1471
1472         return (0);
1473 }
1474
1475 /* -------------------------------------------------------------------------
1476  *
1477  *   FDT processing
1478  */
1479 static struct padctl_port *
1480 search_port(struct padctl_softc *sc, char *port_name)
1481 {
1482         int i;
1483
1484         for (i = 0; i < nitems(ports_tbl); i++) {
1485                 if (strcmp(port_name, ports_tbl[i].name) == 0)
1486                         return (&ports_tbl[i]);
1487         }
1488         return (NULL);
1489 }
1490
1491 static struct padctl_port *
1492 search_lane_port(struct padctl_softc *sc, struct padctl_lane *lane)
1493 {
1494         int i;
1495
1496         for (i = 0; i < nitems(ports_tbl); i++) {
1497                 if (!ports_tbl[i].enabled)
1498                         continue;
1499                 if (ports_tbl[i].lane == lane)
1500                         return (ports_tbl + i);
1501         }
1502         return (NULL);
1503 }
1504
1505 static struct padctl_lane *
1506 search_lane(struct padctl_softc *sc, char *lane_name)
1507 {
1508         int i;
1509
1510         for (i = 0; i < nitems(lanes_tbl); i++) {
1511                 if (strcmp(lane_name, lanes_tbl[i].name) == 0)
1512                         return  (lanes_tbl + i);
1513         }
1514         return (NULL);
1515 }
1516
1517 static struct padctl_lane *
1518 search_pad_lane(struct padctl_softc *sc, enum padctl_pad_type type, int idx)
1519 {
1520         int i;
1521
1522         for (i = 0; i < nitems(lanes_tbl); i++) {
1523                 if (!lanes_tbl[i].enabled)
1524                         continue;
1525                 if (type == lanes_tbl[i].pad->type && idx == lanes_tbl[i].idx)
1526                         return  (lanes_tbl + i);
1527         }
1528         return (NULL);
1529 }
1530
1531 static struct padctl_lane *
1532 search_usb3_pad_lane(struct padctl_softc *sc, int idx)
1533 {
1534         int i;
1535         struct padctl_lane *lane, *tmp;
1536
1537         lane = NULL;
1538         for (i = 0; i < nitems(lane_map_tbl); i++) {
1539                 if (idx != lane_map_tbl[i].port_idx)
1540                         continue;
1541                 tmp = search_pad_lane(sc, lane_map_tbl[i].pad_type,
1542                     lane_map_tbl[i].lane_idx);
1543                 if (tmp == NULL)
1544                         continue;
1545                 if (strcmp(tmp->mux[tmp->mux_idx], "usb3-ss") != 0)
1546                         continue;
1547                 if (lane != NULL) {
1548                         device_printf(sc->dev, "Duplicated mappings found for"
1549                          " lanes: %s and %s\n", lane->name, tmp->name);
1550                         return (NULL);
1551                 }
1552                 lane = tmp;
1553         }
1554         return (lane);
1555 }
1556
1557 static struct padctl_pad *
1558 search_pad(struct padctl_softc *sc, char *pad_name)
1559 {
1560         int i;
1561
1562         for (i = 0; i < nitems(pads_tbl); i++) {
1563                 if (strcmp(pad_name, pads_tbl[i].name) == 0)
1564                         return  (pads_tbl + i);
1565         }
1566         return (NULL);
1567 }
1568
1569 static int
1570 search_mux(struct padctl_softc *sc, struct padctl_lane *lane, char *fnc_name)
1571 {
1572         int i;
1573
1574         for (i = 0; i < lane->nmux; i++) {
1575                 if (strcmp(fnc_name, lane->mux[i]) == 0)
1576                         return  (i);
1577         }
1578         return (-1);
1579 }
1580
1581 static int
1582 config_lane(struct padctl_softc *sc, struct padctl_lane *lane)
1583 {
1584         uint32_t reg;
1585
1586         reg = RD4(sc, lane->reg);
1587         reg &= ~(lane->mask << lane->shift);
1588         reg |=  (lane->mux_idx & lane->mask) << lane->shift;
1589         WR4(sc, lane->reg, reg);
1590         return (0);
1591 }
1592
1593 static int
1594 process_lane(struct padctl_softc *sc, phandle_t node, struct padctl_pad *pad)
1595 {
1596         struct padctl_lane *lane;
1597         struct phynode *phynode;
1598         struct phynode_init_def phy_init;
1599         char *name;
1600         char *function;
1601         int rv;
1602
1603         name = NULL;
1604         function = NULL;
1605         rv = OF_getprop_alloc(node, "name", (void **)&name);
1606         if (rv <= 0) {
1607                 device_printf(sc->dev, "Cannot read lane name.\n");
1608                 return (ENXIO);
1609         }
1610
1611         lane = search_lane(sc, name);
1612         if (lane == NULL) {
1613                 device_printf(sc->dev, "Unknown lane: %s\n", name);
1614                 rv = ENXIO;
1615                 goto end;
1616         }
1617
1618         /* Read function (mux) settings. */
1619         rv = OF_getprop_alloc(node, "nvidia,function", (void **)&function);
1620         if (rv <= 0) {
1621                 device_printf(sc->dev, "Cannot read lane function.\n");
1622                 rv = ENXIO;
1623                 goto end;
1624         }
1625
1626         lane->mux_idx = search_mux(sc, lane, function);
1627         if (lane->mux_idx == ~0) {
1628                 device_printf(sc->dev, "Unknown function %s for lane %s\n",
1629                     function, name);
1630                 rv = ENXIO;
1631                 goto end;
1632         }
1633
1634         rv = config_lane(sc, lane);
1635         if (rv != 0) {
1636                 device_printf(sc->dev, "Cannot configure lane: %s: %d\n",
1637                     name, rv);
1638                 rv = ENXIO;
1639                 goto end;
1640         }
1641         lane->xref = OF_xref_from_node(node);
1642         lane->pad = pad;
1643         lane->enabled = true;
1644         pad->lanes[pad->nlanes++] = lane;
1645
1646         /* Create and register phy. */
1647         bzero(&phy_init, sizeof(phy_init));
1648         phy_init.id = lane - lanes_tbl;
1649         phy_init.ofw_node = node;
1650         phynode = phynode_create(sc->dev, &xusbpadctl_phynode_class, &phy_init);
1651         if (phynode == NULL) {
1652                 device_printf(sc->dev, "Cannot create phy\n");
1653                 rv = ENXIO;
1654                 goto end;
1655         }
1656         if (phynode_register(phynode) == NULL) {
1657                 device_printf(sc->dev, "Cannot create phy\n");
1658                 return (ENXIO);
1659         }
1660
1661         rv = 0;
1662
1663 end:
1664         if (name != NULL)
1665                 OF_prop_free(name);
1666         if (function != NULL)
1667                 OF_prop_free(function);
1668         return (rv);
1669 }
1670
1671 static int
1672 process_pad(struct padctl_softc *sc, phandle_t node)
1673 {
1674         phandle_t  xref;
1675         struct padctl_pad *pad;
1676         char *name;
1677         int rv;
1678
1679         name = NULL;
1680         rv = OF_getprop_alloc(node, "name", (void **)&name);
1681         if (rv <= 0) {
1682                 device_printf(sc->dev, "Cannot read pad name.\n");
1683                 return (ENXIO);
1684         }
1685
1686         pad = search_pad(sc, name);
1687         if (pad == NULL) {
1688                 device_printf(sc->dev, "Unknown pad: %s\n", name);
1689                 rv = ENXIO;
1690                 goto end;
1691         }
1692
1693         if (pad->clock_name != NULL) {
1694                 rv = clk_get_by_ofw_name(sc->dev, node, pad->clock_name,
1695                     &pad->clk);
1696                 if (rv != 0) {
1697                         device_printf(sc->dev, "Cannot get '%s' clock\n",
1698                             pad->clock_name);
1699                         return (ENXIO);
1700                 }
1701         }
1702
1703         if (pad->reset_name != NULL) {
1704                 rv = hwreset_get_by_ofw_name(sc->dev, node, pad->reset_name,
1705                     &pad->reset);
1706                 if (rv != 0) {
1707                         device_printf(sc->dev, "Cannot get '%s' reset\n",
1708                             pad->reset_name);
1709                         return (ENXIO);
1710                 }
1711         }
1712
1713         /* Read and process associated lanes. */
1714         node = ofw_bus_find_child(node, "lanes");
1715         if (node <= 0) {
1716                 device_printf(sc->dev, "Cannot find 'lanes' subnode\n");
1717                 rv = ENXIO;
1718                 goto end;
1719         }
1720
1721         for (node = OF_child(node); node != 0; node = OF_peer(node)) {
1722                 if (!ofw_bus_node_status_okay(node))
1723                         continue;
1724
1725                 rv = process_lane(sc, node, pad);
1726                 if (rv != 0)
1727                         goto end;
1728
1729                 xref = OF_xref_from_node(node);
1730                 OF_device_register_xref(xref, sc->dev);
1731         }
1732         pad->enabled = true;
1733         rv = 0;
1734 end:
1735         if (name != NULL)
1736                 OF_prop_free(name);
1737         return (rv);
1738 }
1739
1740 static int
1741 process_port(struct padctl_softc *sc, phandle_t node)
1742 {
1743
1744         struct padctl_port *port;
1745         char *name;
1746         int rv;
1747
1748         name = NULL;
1749         rv = OF_getprop_alloc(node, "name", (void **)&name);
1750         if (rv <= 0) {
1751                 device_printf(sc->dev, "Cannot read port name.\n");
1752                 return (ENXIO);
1753         }
1754
1755         port = search_port(sc, name);
1756         if (port == NULL) {
1757                 device_printf(sc->dev, "Unknown port: %s\n", name);
1758                 rv = ENXIO;
1759                 goto end;
1760         }
1761
1762         regulator_get_by_ofw_property(sc->dev, node,
1763             "vbus-supply", &port->supply_vbus);
1764
1765         if (OF_hasprop(node, "nvidia,internal"))
1766                 port->internal = true;
1767
1768         /* Find assigned lane */
1769         if (port->lane == NULL) {
1770                 switch(port->type) {
1771                 /* Routing is fixed for USB2 AND HSIC. */
1772                 case PADCTL_PORT_USB2:
1773                         port->lane = search_pad_lane(sc, PADCTL_PAD_USB2,
1774                             port->idx);
1775                         break;
1776                 case PADCTL_PORT_HSIC:
1777                         port->lane = search_pad_lane(sc, PADCTL_PAD_HSIC,
1778                             port->idx);
1779                         break;
1780                 case PADCTL_PORT_USB3:
1781                         port->lane = search_usb3_pad_lane(sc, port->idx);
1782                         break;
1783                 }
1784         }
1785         if (port->lane == NULL) {
1786                 device_printf(sc->dev, "Cannot find lane for port: %s\n", name);
1787                 rv = ENXIO;
1788                 goto end;
1789         }
1790
1791         if (port->type == PADCTL_PORT_USB3) {
1792                 rv = OF_getencprop(node,  "nvidia,usb2-companion",
1793                    &(port->companion), sizeof(port->companion));
1794                 if (rv <= 0) {
1795                         device_printf(sc->dev,
1796                             "Missing 'nvidia,usb2-companion' property "
1797                             "for port: %s\n", name);
1798                         rv = ENXIO;
1799                         goto end;
1800                 }
1801         }
1802
1803         port->enabled = true;
1804         rv = 0;
1805 end:
1806         if (name != NULL)
1807                 OF_prop_free(name);
1808         return (rv);
1809 }
1810
1811 static int
1812 parse_fdt(struct padctl_softc *sc, phandle_t base_node)
1813 {
1814         phandle_t node;
1815         int rv;
1816
1817         rv = 0;
1818         node = ofw_bus_find_child(base_node, "pads");
1819
1820         if (node <= 0) {
1821                 device_printf(sc->dev, "Cannot find pads subnode.\n");
1822                 return (ENXIO);
1823         }
1824         for (node = OF_child(node); node != 0; node = OF_peer(node)) {
1825                 if (!ofw_bus_node_status_okay(node))
1826                         continue;
1827                 rv = process_pad(sc, node);
1828                 if (rv != 0)
1829                         return (rv);
1830         }
1831
1832         node = ofw_bus_find_child(base_node, "ports");
1833         if (node <= 0) {
1834                 device_printf(sc->dev, "Cannot find ports subnode.\n");
1835                 return (ENXIO);
1836         }
1837         for (node = OF_child(node); node != 0; node = OF_peer(node)) {
1838                 if (!ofw_bus_node_status_okay(node))
1839                         continue;
1840                 rv = process_port(sc, node);
1841                 if (rv != 0)
1842                         return (rv);
1843         }
1844
1845         return (0);
1846 }
1847
1848 static void
1849 load_calibration(struct padctl_softc *sc)
1850 {
1851         uint32_t reg;
1852         int i;
1853
1854         reg = tegra_fuse_read_4(FUSE_SKU_CALIB_0);
1855         sc->hs_curr_level[0] = FUSE_SKU_CALIB_0_HS_CURR_LEVEL_0(reg);
1856         for (i = 1; i < nitems(sc->hs_curr_level); i++) {
1857                 sc->hs_curr_level[i] =
1858                     FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(reg, i);
1859         }
1860         sc->hs_term_range_adj = FUSE_SKU_CALIB_0_HS_TERM_RANGE_ADJ(reg);
1861
1862         tegra_fuse_read_4(FUSE_USB_CALIB_EXT_0);
1863         sc->rpd_ctrl = FUSE_USB_CALIB_EXT_0_RPD_CTRL(reg);
1864 }
1865
1866 /* -------------------------------------------------------------------------
1867  *
1868  *   BUS functions
1869  */
1870 static int
1871 xusbpadctl_probe(device_t dev)
1872 {
1873
1874         if (!ofw_bus_status_okay(dev))
1875                 return (ENXIO);
1876
1877         if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
1878                 return (ENXIO);
1879
1880         device_set_desc(dev, "Tegra XUSB phy");
1881         return (BUS_PROBE_DEFAULT);
1882 }
1883
1884 static int
1885 xusbpadctl_detach(device_t dev)
1886 {
1887
1888         /* This device is always present. */
1889         return (EBUSY);
1890 }
1891
1892 static int
1893 xusbpadctl_attach(device_t dev)
1894 {
1895         struct padctl_softc * sc;
1896         int i, rid, rv;
1897         struct padctl_port *port;
1898         phandle_t node;
1899
1900         sc = device_get_softc(dev);
1901         sc->dev = dev;
1902         node = ofw_bus_get_node(dev);
1903         rid = 0;
1904         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1905             RF_ACTIVE);
1906         if (sc->mem_res == NULL) {
1907                 device_printf(dev, "Cannot allocate memory resources\n");
1908                 return (ENXIO);
1909         }
1910
1911         rv = hwreset_get_by_ofw_name(dev, 0, "padctl", &sc->rst);
1912         if (rv != 0) {
1913                 device_printf(dev, "Cannot get 'padctl' reset: %d\n", rv);
1914                 return (rv);
1915         }
1916         rv = hwreset_deassert(sc->rst);
1917         if (rv != 0) {
1918                 device_printf(dev, "Cannot unreset 'padctl' reset: %d\n", rv);
1919                 return (rv);
1920         }
1921
1922         load_calibration(sc);
1923
1924         rv = parse_fdt(sc, node);
1925         if (rv != 0) {
1926                 device_printf(dev, "Cannot parse fdt configuration: %d\n", rv);
1927                 return (rv);
1928         }
1929         for (i = 0; i < nitems(ports_tbl); i++) {
1930                 port = ports_tbl + i;
1931                 if (!port->enabled)
1932                         continue;
1933                 if (port->init == NULL)
1934                         continue;
1935                 rv = port->init(sc, port);
1936                 if (rv != 0) {
1937                         device_printf(dev, "Cannot init port '%s'\n",
1938                             port->name);
1939                         return (rv);
1940                 }
1941         }
1942         return (0);
1943 }
1944
1945 static device_method_t tegra_xusbpadctl_methods[] = {
1946         /* Device interface */
1947         DEVMETHOD(device_probe,         xusbpadctl_probe),
1948         DEVMETHOD(device_attach,        xusbpadctl_attach),
1949         DEVMETHOD(device_detach,        xusbpadctl_detach),
1950
1951         DEVMETHOD_END
1952 };
1953
1954 static DEFINE_CLASS_0(xusbpadctl, tegra_xusbpadctl_driver,
1955     tegra_xusbpadctl_methods, sizeof(struct padctl_softc));
1956 EARLY_DRIVER_MODULE(tegra_xusbpadctl, simplebus, tegra_xusbpadctl_driver,
1957     NULL, NULL, 73);