sys/arm64/rockchip/clk/rk3399_cru.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
   5  * Copyright (c) 2018 Greg V <greg@unrelenting.technology>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/rman.h>
  38 #include <sys/kernel.h>
  39 #include <sys/module.h>
  40 #include <machine/bus.h>
  41
  42 #include <dev/fdt/simplebus.h>
  43
  44 #include <dev/ofw/ofw_bus.h>
  45 #include <dev/ofw/ofw_bus_subr.h>
  46
  47 #include <dev/extres/clk/clk_div.h>
  48 #include <dev/extres/clk/clk_fixed.h>
  49 #include <dev/extres/clk/clk_mux.h>
  50
  51 #include <arm64/rockchip/clk/rk_cru.h>
  52
  53 /* GATES */
  54
  55 #define PCLK_GPIO2              336
  56 #define PCLK_GPIO3              337
  57 #define PCLK_GPIO4              338
  58 #define PCLK_I2C1               341
  59 #define PCLK_I2C2               342
  60 #define PCLK_I2C3               343
  61 #define PCLK_I2C5               344
  62 #define PCLK_I2C6               345
  63 #define PCLK_I2C7               346
  64 #define HCLK_SDMMC              462
  65
  66 static struct rk_cru_gate rk3399_gates[] = {
  67         /* CRU_CLKGATE_CON0 */
  68         CRU_GATE(0, "clk_core_l_lpll_src", "lpll", 0x300, 0)
  69         CRU_GATE(0, "clk_core_l_bpll_src", "bpll", 0x300, 1)
  70         CRU_GATE(0, "clk_core_l_dpll_src", "dpll", 0x300, 2)
  71         CRU_GATE(0, "clk_core_l_gpll_src", "gpll", 0x300, 3)
  72
  73         /* CRU_CLKGATE_CON1 */
  74         CRU_GATE(0, "clk_core_b_lpll_src", "lpll", 0x304, 0)
  75         CRU_GATE(0, "clk_core_b_bpll_src", "bpll", 0x304, 1)
  76         CRU_GATE(0, "clk_core_b_dpll_src", "dpll", 0x304, 2)
  77         CRU_GATE(0, "clk_core_b_gpll_src", "gpll", 0x304, 3)
  78
  79         /* CRU_CLKGATE_CON5 */
  80         CRU_GATE(0, "cpll_aclk_perihp_src", "cpll", 0x314, 0)
  81         CRU_GATE(0, "gpll_aclk_perihp_src", "gpll", 0x314, 1)
  82
  83         /* CRU_CLKGATE_CON7 */
  84         CRU_GATE(0, "gpll_aclk_perilp0_src", "gpll", 0x31C, 0)
  85         CRU_GATE(0, "cpll_aclk_perilp0_src", "cpll", 0x31C, 1)
  86
  87         /* CRU_CLKGATE_CON8 */
  88         CRU_GATE(0, "hclk_perilp1_cpll_src", "cpll", 0x320, 1)
  89         CRU_GATE(0, "hclk_perilp1_gpll_src", "gpll", 0x320, 0)
  90
  91         /* CRU_CLKGATE_CON22 */
  92         CRU_GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0x358, 5)
  93         CRU_GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0x358, 6)
  94         CRU_GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0x358, 7)
  95         CRU_GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0x358, 8)
  96         CRU_GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0x358, 9)
  97         CRU_GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0x358, 10)
  98
  99         /* CRU_CLKGATE_CON31 */
 100         CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3)
 101         CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4)
 102         CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5)
 103
 104         /* CRU_CLKGATE_CON33 */
 105         CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0x384, 8)
 106 };
 107
 108
 109 /*
 110  * PLLs
 111  */
 112
 113 #define PLL_APLLL                       1
 114 #define PLL_APLLB                       2
 115 #define PLL_DPLL                        3
 116 #define PLL_CPLL                        4
 117 #define PLL_GPLL                        5
 118 #define PLL_NPLL                        6
 119 #define PLL_VPLL                        7
 120
 121 static struct rk_clk_pll_rate rk3399_pll_rates[] = {
 122         {
 123                 .freq = 2208000000,
 124                 .refdiv = 1,
 125                 .fbdiv = 92,
 126                 .postdiv1 = 1,
 127                 .postdiv2 = 1,
 128                 .dsmpd = 1,
 129         },
 130         {
 131                 .freq = 2184000000,
 132                 .refdiv = 1,
 133                 .fbdiv = 91,
 134                 .postdiv1 = 1,
 135                 .postdiv2 = 1,
 136                 .dsmpd = 1,
 137         },
 138         {
 139                 .freq = 2160000000,
 140                 .refdiv = 1,
 141                 .fbdiv = 90,
 142                 .postdiv1 = 1,
 143                 .postdiv2 = 1,
 144                 .dsmpd = 1,
 145         },
 146         {
 147                 .freq = 2136000000,
 148                 .refdiv = 1,
 149                 .fbdiv = 89,
 150                 .postdiv1 = 1,
 151                 .postdiv2 = 1,
 152                 .dsmpd = 1,
 153         },
 154         {
 155                 .freq = 2112000000,
 156                 .refdiv = 1,
 157                 .fbdiv = 88,
 158                 .postdiv1 = 1,
 159                 .postdiv2 = 1,
 160                 .dsmpd = 1,
 161         },
 162         {
 163                 .freq = 2088000000,
 164                 .refdiv = 1,
 165                 .fbdiv = 87,
 166                 .postdiv1 = 1,
 167                 .postdiv2 = 1,
 168                 .dsmpd = 1,
 169         },
 170         {
 171                 .freq = 2064000000,
 172                 .refdiv = 1,
 173                 .fbdiv = 86,
 174                 .postdiv1 = 1,
 175                 .postdiv2 = 1,
 176                 .dsmpd = 1,
 177         },
 178         {
 179                 .freq = 2040000000,
 180                 .refdiv = 1,
 181                 .fbdiv = 85,
 182                 .postdiv1 = 1,
 183                 .postdiv2 = 1,
 184                 .dsmpd = 1,
 185         },
 186         {
 187                 .freq = 2016000000,
 188                 .refdiv = 1,
 189                 .fbdiv = 84,
 190                 .postdiv1 = 1,
 191                 .postdiv2 = 1,
 192                 .dsmpd = 1,
 193         },
 194         {
 195                 .freq = 1992000000,
 196                 .refdiv = 1,
 197                 .fbdiv = 83,
 198                 .postdiv1 = 1,
 199                 .postdiv2 = 1,
 200                 .dsmpd = 1,
 201         },
 202         {
 203                 .freq = 1968000000,
 204                 .refdiv = 1,
 205                 .fbdiv = 82,
 206                 .postdiv1 = 1,
 207                 .postdiv2 = 1,
 208                 .dsmpd = 1,
 209         },
 210         {
 211                 .freq = 1944000000,
 212                 .refdiv = 1,
 213                 .fbdiv = 81,
 214                 .postdiv1 = 1,
 215                 .postdiv2 = 1,
 216                 .dsmpd = 1,
 217         },
 218         {
 219                 .freq = 1920000000,
 220                 .refdiv = 1,
 221                 .fbdiv = 80,
 222                 .postdiv1 = 1,
 223                 .postdiv2 = 1,
 224                 .dsmpd = 1,
 225         },
 226         {
 227                 .freq = 1896000000,
 228                 .refdiv = 1,
 229                 .fbdiv = 79,
 230                 .postdiv1 = 1,
 231                 .postdiv2 = 1,
 232                 .dsmpd = 1,
 233         },
 234         {
 235                 .freq = 1872000000,
 236                 .refdiv = 1,
 237                 .fbdiv = 78,
 238                 .postdiv1 = 1,
 239                 .postdiv2 = 1,
 240                 .dsmpd = 1,
 241         },
 242         {
 243                 .freq = 1848000000,
 244                 .refdiv = 1,
 245                 .fbdiv = 77,
 246                 .postdiv1 = 1,
 247                 .postdiv2 = 1,
 248                 .dsmpd = 1,
 249         },
 250         {
 251                 .freq = 1824000000,
 252                 .refdiv = 1,
 253                 .fbdiv = 76,
 254                 .postdiv1 = 1,
 255                 .postdiv2 = 1,
 256                 .dsmpd = 1,
 257         },
 258         {
 259                 .freq = 1800000000,
 260                 .refdiv = 1,
 261                 .fbdiv = 75,
 262                 .postdiv1 = 1,
 263                 .postdiv2 = 1,
 264                 .dsmpd = 1,
 265         },
 266         {
 267                 .freq = 1776000000,
 268                 .refdiv = 1,
 269                 .fbdiv = 74,
 270                 .postdiv1 = 1,
 271                 .postdiv2 = 1,
 272                 .dsmpd = 1,
 273         },
 274         {
 275                 .freq = 1752000000,
 276                 .refdiv = 1,
 277                 .fbdiv = 73,
 278                 .postdiv1 = 1,
 279                 .postdiv2 = 1,
 280                 .dsmpd = 1,
 281         },
 282         {
 283                 .freq = 1728000000,
 284                 .refdiv = 1,
 285                 .fbdiv = 72,
 286                 .postdiv1 = 1,
 287                 .postdiv2 = 1,
 288                 .dsmpd = 1,
 289         },
 290         {
 291                 .freq = 1704000000,
 292                 .refdiv = 1,
 293                 .fbdiv = 71,
 294                 .postdiv1 = 1,
 295                 .postdiv2 = 1,
 296                 .dsmpd = 1,
 297         },
 298         {
 299                 .freq = 1680000000,
 300                 .refdiv = 1,
 301                 .fbdiv = 70,
 302                 .postdiv1 = 1,
 303                 .postdiv2 = 1,
 304                 .dsmpd = 1,
 305         },
 306         {
 307                 .freq = 1656000000,
 308                 .refdiv = 1,
 309                 .fbdiv = 69,
 310                 .postdiv1 = 1,
 311                 .postdiv2 = 1,
 312                 .dsmpd = 1,
 313         },
 314         {
 315                 .freq = 1632000000,
 316                 .refdiv = 1,
 317                 .fbdiv = 68,
 318                 .postdiv1 = 1,
 319                 .postdiv2 = 1,
 320                 .dsmpd = 1,
 321         },
 322         {
 323                 .freq = 1608000000,
 324                 .refdiv = 1,
 325                 .fbdiv = 67,
 326                 .postdiv1 = 1,
 327                 .postdiv2 = 1,
 328                 .dsmpd = 1,
 329         },
 330         {
 331                 .freq = 1600000000,
 332                 .refdiv = 3,
 333                 .fbdiv = 200,
 334                 .postdiv1 = 1,
 335                 .postdiv2 = 1,
 336                 .dsmpd = 1,
 337         },
 338         {
 339                 .freq = 1584000000,
 340                 .refdiv = 1,
 341                 .fbdiv = 66,
 342                 .postdiv1 = 1,
 343                 .postdiv2 = 1,
 344                 .dsmpd = 1,
 345         },
 346         {
 347                 .freq = 1560000000,
 348                 .refdiv = 1,
 349                 .fbdiv = 65,
 350                 .postdiv1 = 1,
 351                 .postdiv2 = 1,
 352                 .dsmpd = 1,
 353         },
 354         {
 355                 .freq = 1536000000,
 356                 .refdiv = 1,
 357                 .fbdiv = 64,
 358                 .postdiv1 = 1,
 359                 .postdiv2 = 1,
 360                 .dsmpd = 1,
 361         },
 362         {
 363                 .freq = 1512000000,
 364                 .refdiv = 1,
 365                 .fbdiv = 63,
 366                 .postdiv1 = 1,
 367                 .postdiv2 = 1,
 368                 .dsmpd = 1,
 369         },
 370         {
 371                 .freq = 1488000000,
 372                 .refdiv = 1,
 373                 .fbdiv = 62,
 374                 .postdiv1 = 1,
 375                 .postdiv2 = 1,
 376                 .dsmpd = 1,
 377         },
 378         {
 379                 .freq = 1464000000,
 380                 .refdiv = 1,
 381                 .fbdiv = 61,
 382                 .postdiv1 = 1,
 383                 .postdiv2 = 1,
 384                 .dsmpd = 1,
 385         },
 386         {
 387                 .freq = 1440000000,
 388                 .refdiv = 1,
 389                 .fbdiv = 60,
 390                 .postdiv1 = 1,
 391                 .postdiv2 = 1,
 392                 .dsmpd = 1,
 393         },
 394         {
 395                 .freq = 1416000000,
 396                 .refdiv = 1,
 397                 .fbdiv = 59,
 398                 .postdiv1 = 1,
 399                 .postdiv2 = 1,
 400                 .dsmpd = 1,
 401         },
 402         {
 403                 .freq = 1392000000,
 404                 .refdiv = 1,
 405                 .fbdiv = 58,
 406                 .postdiv1 = 1,
 407                 .postdiv2 = 1,
 408                 .dsmpd = 1,
 409         },
 410         {
 411                 .freq = 1368000000,
 412                 .refdiv = 1,
 413                 .fbdiv = 57,
 414                 .postdiv1 = 1,
 415                 .postdiv2 = 1,
 416                 .dsmpd = 1,
 417         },
 418         {
 419                 .freq = 1344000000,
 420                 .refdiv = 1,
 421                 .fbdiv = 56,
 422                 .postdiv1 = 1,
 423                 .postdiv2 = 1,
 424                 .dsmpd = 1,
 425         },
 426         {
 427                 .freq = 1320000000,
 428                 .refdiv = 1,
 429                 .fbdiv = 55,
 430                 .postdiv1 = 1,
 431                 .postdiv2 = 1,
 432                 .dsmpd = 1,
 433         },
 434         {
 435                 .freq = 1296000000,
 436                 .refdiv = 1,
 437                 .fbdiv = 54,
 438                 .postdiv1 = 1,
 439                 .postdiv2 = 1,
 440                 .dsmpd = 1,
 441         },
 442         {
 443                 .freq = 1272000000,
 444                 .refdiv = 1,
 445                 .fbdiv = 53,
 446                 .postdiv1 = 1,
 447                 .postdiv2 = 1,
 448                 .dsmpd = 1,
 449         },
 450         {
 451                 .freq = 1248000000,
 452                 .refdiv = 1,
 453                 .fbdiv = 52,
 454                 .postdiv1 = 1,
 455                 .postdiv2 = 1,
 456                 .dsmpd = 1,
 457         },
 458         {
 459                 .freq = 1200000000,
 460                 .refdiv = 1,
 461                 .fbdiv = 50,
 462                 .postdiv1 = 1,
 463                 .postdiv2 = 1,
 464                 .dsmpd = 1,
 465         },
 466         {
 467                 .freq = 1188000000,
 468                 .refdiv = 2,
 469                 .fbdiv = 99,
 470                 .postdiv1 = 1,
 471                 .postdiv2 = 1,
 472                 .dsmpd = 1,
 473         },
 474         {
 475                 .freq = 1104000000,
 476                 .refdiv = 1,
 477                 .fbdiv = 46,
 478                 .postdiv1 = 1,
 479                 .postdiv2 = 1,
 480                 .dsmpd = 1,
 481         },
 482         {
 483                 .freq = 1100000000,
 484                 .refdiv = 12,
 485                 .fbdiv = 550,
 486                 .postdiv1 = 1,
 487                 .postdiv2 = 1,
 488                 .dsmpd = 1,
 489         },
 490         {
 491                 .freq = 1008000000,
 492                 .refdiv = 1,
 493                 .fbdiv = 84,
 494                 .postdiv1 = 2,
 495                 .postdiv2 = 1,
 496                 .dsmpd = 1,
 497         },
 498         {
 499                 .freq = 1000000000,
 500                 .refdiv = 1,
 501                 .fbdiv = 125,
 502                 .postdiv1 = 3,
 503                 .postdiv2 = 1,
 504                 .dsmpd = 1,
 505         },
 506         {
 507                 .freq = 984000000,
 508                 .refdiv = 1,
 509                 .fbdiv = 82,
 510                 .postdiv1 = 2,
 511                 .postdiv2 = 1,
 512                 .dsmpd = 1,
 513         },
 514         {
 515                 .freq = 960000000,
 516                 .refdiv = 1,
 517                 .fbdiv = 80,
 518                 .postdiv1 = 2,
 519                 .postdiv2 = 1,
 520                 .dsmpd = 1,
 521         },
 522         {
 523                 .freq = 936000000,
 524                 .refdiv = 1,
 525                 .fbdiv = 78,
 526                 .postdiv1 = 2,
 527                 .postdiv2 = 1,
 528                 .dsmpd = 1,
 529         },
 530         {
 531                 .freq = 912000000,
 532                 .refdiv = 1,
 533                 .fbdiv = 76,
 534                 .postdiv1 = 2,
 535                 .postdiv2 = 1,
 536                 .dsmpd = 1,
 537         },
 538         {
 539                 .freq = 900000000,
 540                 .refdiv = 4,
 541                 .fbdiv = 300,
 542                 .postdiv1 = 2,
 543                 .postdiv2 = 1,
 544                 .dsmpd = 1,
 545         },
 546         {
 547                 .freq = 888000000,
 548                 .refdiv = 1,
 549                 .fbdiv = 74,
 550                 .postdiv1 = 2,
 551                 .postdiv2 = 1,
 552                 .dsmpd = 1,
 553         },
 554         {
 555                 .freq = 864000000,
 556                 .refdiv = 1,
 557                 .fbdiv = 72,
 558                 .postdiv1 = 2,
 559                 .postdiv2 = 1,
 560                 .dsmpd = 1,
 561         },
 562         {
 563                 .freq = 840000000,
 564                 .refdiv = 1,
 565                 .fbdiv = 70,
 566                 .postdiv1 = 2,
 567                 .postdiv2 = 1,
 568                 .dsmpd = 1,
 569         },
 570         {
 571                 .freq = 816000000,
 572                 .refdiv = 1,
 573                 .fbdiv = 68,
 574                 .postdiv1 = 2,
 575                 .postdiv2 = 1,
 576                 .dsmpd = 1,
 577         },
 578         {
 579                 .freq = 800000000,
 580                 .refdiv = 1,
 581                 .fbdiv = 100,
 582                 .postdiv1 = 3,
 583                 .postdiv2 = 1,
 584                 .dsmpd = 1,
 585         },
 586         {
 587                 .freq = 700000000,
 588                 .refdiv = 6,
 589                 .fbdiv = 350,
 590                 .postdiv1 = 2,
 591                 .postdiv2 = 1,
 592                 .dsmpd = 1,
 593         },
 594         {
 595                 .freq = 696000000,
 596                 .refdiv = 1,
 597                 .fbdiv = 58,
 598                 .postdiv1 = 2,
 599                 .postdiv2 = 1,
 600                 .dsmpd = 1,
 601         },
 602         {
 603                 .freq = 676000000,
 604                 .refdiv = 3,
 605                 .fbdiv = 169,
 606                 .postdiv1 = 2,
 607                 .postdiv2 = 1,
 608                 .dsmpd = 1,
 609         },
 610         {
 611                 .freq = 600000000,
 612                 .refdiv = 1,
 613                 .fbdiv = 75,
 614                 .postdiv1 = 3,
 615                 .postdiv2 = 1,
 616                 .dsmpd = 1,
 617         },
 618         {
 619                 .freq = 594000000,
 620                 .refdiv = 1,
 621                 .fbdiv = 99,
 622                 .postdiv1 = 4,
 623                 .postdiv2 = 1,
 624                 .dsmpd = 1,
 625         },
 626         {
 627                 .freq = 533250000,
 628                 .refdiv = 8,
 629                 .fbdiv = 711,
 630                 .postdiv1 = 4,
 631                 .postdiv2 = 1,
 632                 .dsmpd = 1,
 633         },
 634         {
 635                 .freq = 504000000,
 636                 .refdiv = 1,
 637                 .fbdiv = 63,
 638                 .postdiv1 = 3,
 639                 .postdiv2 = 1,
 640                 .dsmpd = 1,
 641         },
 642         {
 643                 .freq = 500000000,
 644                 .refdiv = 6,
 645                 .fbdiv = 250,
 646                 .postdiv1 = 2,
 647                 .postdiv2 = 1,
 648                 .dsmpd = 1,
 649         },
 650         {
 651                 .freq = 408000000,
 652                 .refdiv = 1,
 653                 .fbdiv = 68,
 654                 .postdiv1 = 2,
 655                 .postdiv2 = 2,
 656                 .dsmpd = 1,
 657         },
 658         {
 659                 .freq = 312000000,
 660                 .refdiv = 1,
 661                 .fbdiv = 52,
 662                 .postdiv1 = 2,
 663                 .postdiv2 = 2,
 664                 .dsmpd = 1,
 665         },
 666         {
 667                 .freq = 297000000,
 668                 .refdiv = 1,
 669                 .fbdiv = 99,
 670                 .postdiv1 = 4,
 671                 .postdiv2 = 2,
 672                 .dsmpd = 1,
 673         },
 674         {
 675                 .freq = 216000000,
 676                 .refdiv = 1,
 677                 .fbdiv = 72,
 678                 .postdiv1 = 4,
 679                 .postdiv2 = 2,
 680                 .dsmpd = 1,
 681         },
 682         {
 683                 .freq = 148500000,
 684                 .refdiv = 1,
 685                 .fbdiv = 99,
 686                 .postdiv1 = 4,
 687                 .postdiv2 = 4,
 688                 .dsmpd = 1,
 689         },
 690         {
 691                 .freq = 106500000,
 692                 .refdiv = 1,
 693                 .fbdiv = 71,
 694                 .postdiv1 = 4,
 695                 .postdiv2 = 4,
 696                 .dsmpd = 1,
 697         },
 698         {
 699                 .freq = 96000000,
 700                 .refdiv = 1,
 701                 .fbdiv = 64,
 702                 .postdiv1 = 4,
 703                 .postdiv2 = 4,
 704                 .dsmpd = 1,
 705         },
 706         {
 707                 .freq = 74250000,
 708                 .refdiv = 2,
 709                 .fbdiv = 99,
 710                 .postdiv1 = 4,
 711                 .postdiv2 = 4,
 712                 .dsmpd = 1,
 713         },
 714         {
 715                 .freq = 65000000,
 716                 .refdiv = 1,
 717                 .fbdiv = 65,
 718                 .postdiv1 = 6,
 719                 .postdiv2 = 4,
 720                 .dsmpd = 1,
 721         },
 722         {
 723                 .freq = 54000000,
 724                 .refdiv = 1,
 725                 .fbdiv = 54,
 726                 .postdiv1 = 6,
 727                 .postdiv2 = 4,
 728                 .dsmpd = 1,
 729         },
 730         {
 731                 .freq = 27000000,
 732                 .refdiv = 1,
 733                 .fbdiv = 27,
 734                 .postdiv1 = 6,
 735                 .postdiv2 = 4,
 736                 .dsmpd = 1,
 737         },
 738         {},
 739 };
 740
 741 static const char *pll_parents[] = {"xin24m"};
 742
 743 static struct rk_clk_pll_def lpll = {
 744         .clkdef = {
 745                 .id = PLL_APLLL,
 746                 .name = "lpll",
 747                 .parent_names = pll_parents,
 748                 .parent_cnt = nitems(pll_parents),
 749         },
 750         .base_offset = 0x00,
 751         .gate_offset = 0x300,
 752         .gate_shift = 0,
 753         .flags = RK_CLK_PLL_HAVE_GATE,
 754         .rates = rk3399_pll_rates,
 755 };
 756
 757 static struct rk_clk_pll_def bpll = {
 758         .clkdef = {
 759                 .id = PLL_APLLB,
 760                 .name = "bpll",
 761                 .parent_names = pll_parents,
 762                 .parent_cnt = nitems(pll_parents),
 763         },
 764         .base_offset = 0x20,
 765         .gate_offset = 0x300,
 766         .gate_shift = 1,
 767         .flags = RK_CLK_PLL_HAVE_GATE,
 768         .rates = rk3399_pll_rates,
 769 };
 770
 771 static struct rk_clk_pll_def dpll = {
 772         .clkdef = {
 773                 .id = PLL_DPLL,
 774                 .name = "dpll",
 775                 .parent_names = pll_parents,
 776                 .parent_cnt = nitems(pll_parents),
 777         },
 778         .base_offset = 0x40,
 779         .gate_offset = 0x300,
 780         .gate_shift = 2,
 781         .flags = RK_CLK_PLL_HAVE_GATE,
 782         .rates = rk3399_pll_rates,
 783 };
 784
 785
 786 static struct rk_clk_pll_def cpll = {
 787         .clkdef = {
 788                 .id = PLL_CPLL,
 789                 .name = "cpll",
 790                 .parent_names = pll_parents,
 791                 .parent_cnt = nitems(pll_parents),
 792         },
 793         .base_offset = 0x60,
 794         .rates = rk3399_pll_rates,
 795 };
 796
 797 static struct rk_clk_pll_def gpll = {
 798         .clkdef = {
 799                 .id = PLL_GPLL,
 800                 .name = "gpll",
 801                 .parent_names = pll_parents,
 802                 .parent_cnt = nitems(pll_parents),
 803         },
 804         .base_offset = 0x80,
 805         .gate_offset = 0x300,
 806         .gate_shift = 3,
 807         .flags = RK_CLK_PLL_HAVE_GATE,
 808         .rates = rk3399_pll_rates,
 809 };
 810
 811 static struct rk_clk_pll_def npll = {
 812         .clkdef = {
 813                 .id = PLL_NPLL,
 814                 .name = "npll",
 815                 .parent_names = pll_parents,
 816                 .parent_cnt = nitems(pll_parents),
 817         },
 818         .base_offset = 0xa0,
 819         .rates = rk3399_pll_rates,
 820 };
 821
 822 static struct rk_clk_pll_def vpll = {
 823         .clkdef = {
 824                 .id = PLL_VPLL,
 825                 .name = "vpll",
 826                 .parent_names = pll_parents,
 827                 .parent_cnt = nitems(pll_parents),
 828         },
 829         .base_offset = 0xc0,
 830         .rates = rk3399_pll_rates,
 831 };
 832
 833 #define ACLK_PERIHP     192
 834 #define HCLK_PERIHP     448
 835 #define PCLK_PERIHP     320
 836
 837 static const char *aclk_perihp_parents[] = {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src"};
 838
 839 static struct rk_clk_composite_def aclk_perihp = {
 840         .clkdef = {
 841                 .id = ACLK_PERIHP,
 842                 .name = "aclk_perihp",
 843                 .parent_names = aclk_perihp_parents,
 844                 .parent_cnt = nitems(aclk_perihp_parents),
 845         },
 846         /* CRU_CLKSEL_CON14 */
 847         .muxdiv_offset = 0x138,
 848
 849         .mux_shift = 7,
 850         .mux_width = 1,
 851
 852         .div_shift = 0,
 853         .div_width = 5,
 854
 855         /* CRU_CLKGATE_CON5 */
 856         .gate_offset = 0x314,
 857         .gate_shift = 2,
 858
 859         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 860 };
 861
 862 static const char *hclk_pclk_perihp_parents[] = {"aclk_perihp"};
 863
 864 static struct rk_clk_composite_def hclk_perihp = {
 865         .clkdef = {
 866                 .id = HCLK_PERIHP,
 867                 .name = "hclk_perihp",
 868                 .parent_names = hclk_pclk_perihp_parents,
 869                 .parent_cnt = nitems(hclk_pclk_perihp_parents),
 870         },
 871         /* CRU_CLKSEL_CON14 */
 872         .muxdiv_offset = 0x138,
 873
 874         .div_shift = 8,
 875         .div_width = 2,
 876
 877         /* CRU_CLKGATE_CON5 */
 878         .gate_offset = 0x314,
 879         .gate_shift = 3,
 880
 881         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 882 };
 883
 884 static struct rk_clk_composite_def pclk_perihp = {
 885         .clkdef = {
 886                 .id = PCLK_PERIHP,
 887                 .name = "pclk_perihp",
 888                 .parent_names = hclk_pclk_perihp_parents,
 889                 .parent_cnt = nitems(hclk_pclk_perihp_parents),
 890         },
 891         /* CRU_CLKSEL_CON14 */
 892         .muxdiv_offset = 0x138,
 893
 894         .div_shift = 12,
 895         .div_width = 3,
 896
 897         /* CRU_CLKGATE_CON5 */
 898         .gate_offset = 0x314,
 899         .gate_shift = 4,
 900
 901         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 902 };
 903
 904 #define ACLK_PERILP0    194
 905 #define HCLK_PERILP0    449
 906 #define PCLK_PERILP0    322
 907
 908 static const char *aclk_perilp0_parents[] = {"cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src"};
 909
 910 static struct rk_clk_composite_def aclk_perilp0 = {
 911         .clkdef = {
 912                 .id = ACLK_PERILP0,
 913                 .name = "aclk_perilp0",
 914                 .parent_names = aclk_perilp0_parents,
 915                 .parent_cnt = nitems(aclk_perilp0_parents),
 916         },
 917         /* CRU_CLKSEL_CON14 */
 918         .muxdiv_offset = 0x15C,
 919
 920         .mux_shift = 7,
 921         .mux_width = 1,
 922
 923         .div_shift = 0,
 924         .div_width = 5,
 925
 926         /* CRU_CLKGATE_CON7 */
 927         .gate_offset = 0x31C,
 928         .gate_shift = 2,
 929
 930         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 931 };
 932
 933 static const char *hclk_pclk_perilp0_parents[] = {"aclk_perilp0"};
 934
 935 static struct rk_clk_composite_def hclk_perilp0 = {
 936         .clkdef = {
 937                 .id = HCLK_PERILP0,
 938                 .name = "hclk_perilp0",
 939                 .parent_names = hclk_pclk_perilp0_parents,
 940                 .parent_cnt = nitems(hclk_pclk_perilp0_parents),
 941         },
 942         /* CRU_CLKSEL_CON23 */
 943         .muxdiv_offset = 0x15C,
 944
 945         .div_shift = 8,
 946         .div_width = 2,
 947
 948         /* CRU_CLKGATE_CON7 */
 949         .gate_offset = 0x31C,
 950         .gate_shift = 3,
 951
 952         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 953 };
 954
 955 static struct rk_clk_composite_def pclk_perilp0 = {
 956         .clkdef = {
 957                 .id = PCLK_PERILP0,
 958                 .name = "pclk_perilp0",
 959                 .parent_names = hclk_pclk_perilp0_parents,
 960                 .parent_cnt = nitems(hclk_pclk_perilp0_parents),
 961         },
 962         /* CRU_CLKSEL_CON23 */
 963         .muxdiv_offset = 0x15C,
 964
 965         .div_shift = 12,
 966         .div_width = 3,
 967
 968         /* CRU_CLKGATE_CON7 */
 969         .gate_offset = 0x31C,
 970         .gate_shift = 4,
 971
 972         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 973 };
 974
 975 /*
 976  * misc
 977  */
 978 #define PCLK_ALIVE              390
 979
 980 static const char *alive_parents[] = {"gpll"};
 981
 982 static struct rk_clk_composite_def pclk_alive = {
 983         .clkdef = {
 984                 .id = PCLK_ALIVE,
 985                 .name = "pclk_alive",
 986                 .parent_names = alive_parents,
 987                 .parent_cnt = nitems(alive_parents),
 988         },
 989         /* CRU_CLKSEL_CON57 */
 990         .muxdiv_offset = 0x01e4,
 991
 992         .div_shift = 0,
 993         .div_width = 5,
 994 };
 995
 996 #define HCLK_PERILP1            450
 997 #define PCLK_PERILP1            323
 998
 999 static const char *hclk_perilp1_parents[] = {"cpll", "gpll"};
1000
1001 static struct rk_clk_composite_def hclk_perilp1 = {
1002         .clkdef = {
1003                 .id = HCLK_PERILP1,
1004                 .name = "hclk_perilp1",
1005                 .parent_names = hclk_perilp1_parents,
1006                 .parent_cnt = nitems(hclk_perilp1_parents),
1007         },
1008         /* CRU_CLKSEL_CON25 */
1009         .muxdiv_offset = 0x164,
1010         .mux_shift = 7,
1011         .mux_width = 1,
1012
1013         .div_shift = 0,
1014         .div_width = 5,
1015
1016         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1017 };
1018
1019 static const char *pclk_perilp1_parents[] = {"hclk_perilp1"};
1020
1021 static struct rk_clk_composite_def pclk_perilp1 = {
1022         .clkdef = {
1023                 .id = PCLK_PERILP1,
1024                 .name = "pclk_perilp1",
1025                 .parent_names = pclk_perilp1_parents,
1026                 .parent_cnt = nitems(pclk_perilp1_parents),
1027         },
1028         /* CRU_CLKSEL_CON25 */
1029         .muxdiv_offset = 0x164,
1030
1031         .div_shift = 8,
1032         .div_width = 3,
1033
1034         /* CRU_CLKGATE_CON8 */
1035         .gate_offset = 0x320,
1036         .gate_shift = 2,
1037
1038         .flags = RK_CLK_COMPOSITE_HAVE_GATE,
1039 };
1040
1041 /*
1042  * i2c
1043  */
1044 static const char *i2c_parents[] = {"cpll", "gpll"};
1045
1046 #define SCLK_I2C1       65
1047 #define SCLK_I2C2       66
1048 #define SCLK_I2C3       67
1049 #define SCLK_I2C5       68
1050 #define SCLK_I2C6       69
1051 #define SCLK_I2C7       70
1052
1053 static struct rk_clk_composite_def i2c1 = {
1054         .clkdef = {
1055                 .id = SCLK_I2C1,
1056                 .name = "clk_i2c1",
1057                 .parent_names = i2c_parents,
1058                 .parent_cnt = nitems(i2c_parents),
1059         },
1060         /* CRU_CLKSEL_CON61 */
1061         .muxdiv_offset = 0x01f4,
1062         .mux_shift = 7,
1063         .mux_width = 1,
1064
1065         .div_shift = 0,
1066         .div_width = 7,
1067
1068         /* CRU_CLKGATE_CON10 */
1069         .gate_offset = 0x0328,
1070         .gate_shift = 0,
1071
1072         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1073 };
1074
1075 static struct rk_clk_composite_def i2c2 = {
1076         .clkdef = {
1077                 .id = SCLK_I2C2,
1078                 .name = "clk_i2c2",
1079                 .parent_names = i2c_parents,
1080                 .parent_cnt = nitems(i2c_parents),
1081         },
1082         /* CRU_CLKSEL_CON62 */
1083         .muxdiv_offset = 0x01f8,
1084         .mux_shift = 7,
1085         .mux_width = 1,
1086
1087         .div_shift = 0,
1088         .div_width = 7,
1089
1090         /* CRU_CLKGATE_CON10 */
1091         .gate_offset = 0x0328,
1092         .gate_shift = 2,
1093
1094         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1095 };
1096
1097 static struct rk_clk_composite_def i2c3 = {
1098         .clkdef = {
1099                 .id = SCLK_I2C3,
1100                 .name = "clk_i2c3",
1101                 .parent_names = i2c_parents,
1102                 .parent_cnt = nitems(i2c_parents),
1103         },
1104         /* CRU_CLKSEL_CON63 */
1105         .muxdiv_offset = 0x01fc,
1106         .mux_shift = 7,
1107         .mux_width = 1,
1108
1109         .div_shift = 0,
1110         .div_width = 7,
1111
1112         /* CRU_CLKGATE_CON10 */
1113         .gate_offset = 0x0328,
1114         .gate_shift = 4,
1115
1116         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1117 };
1118
1119 static struct rk_clk_composite_def i2c5 = {
1120         .clkdef = {
1121                 .id = SCLK_I2C5,
1122                 .name = "clk_i2c5",
1123                 .parent_names = i2c_parents,
1124                 .parent_cnt = nitems(i2c_parents),
1125         },
1126         /* CRU_CLKSEL_CON61 */
1127         .muxdiv_offset = 0x01f4,
1128         .mux_shift = 15,
1129         .mux_width = 1,
1130
1131         .div_shift = 8,
1132         .div_width = 7,
1133
1134         /* CRU_CLKGATE_CON10 */
1135         .gate_offset = 0x0328,
1136         .gate_shift = 1,
1137
1138         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1139 };
1140
1141 static struct rk_clk_composite_def i2c6 = {
1142         .clkdef = {
1143                 .id = SCLK_I2C6,
1144                 .name = "clk_i2c6",
1145                 .parent_names = i2c_parents,
1146                 .parent_cnt = nitems(i2c_parents),
1147         },
1148         /* CRU_CLKSEL_CON62 */
1149         .muxdiv_offset = 0x01f8,
1150         .mux_shift = 15,
1151         .mux_width = 1,
1152
1153         .div_shift = 8,
1154         .div_width = 7,
1155
1156         /* CRU_CLKGATE_CON10 */
1157         .gate_offset = 0x0328,
1158         .gate_shift = 3,
1159
1160         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1161 };
1162
1163 static struct rk_clk_composite_def i2c7 = {
1164         .clkdef = {
1165                 .id = SCLK_I2C7,
1166                 .name = "clk_i2c7",
1167                 .parent_names = i2c_parents,
1168                 .parent_cnt = nitems(i2c_parents),
1169         },
1170         /* CRU_CLKSEL_CON63 */
1171         .muxdiv_offset = 0x01fc,
1172         .mux_shift = 15,
1173         .mux_width = 1,
1174
1175         .div_shift = 8,
1176         .div_width = 7,
1177
1178         /* CRU_CLKGATE_CON10 */
1179         .gate_offset = 0x0328,
1180         .gate_shift = 5,
1181
1182         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1183 };
1184
1185 /*
1186  * ARM CPU clocks (LITTLE and big)
1187  */
1188 #define ARMCLKL                         8
1189 #define ARMCLKB                         9
1190
1191 static const char *armclk_parents[] = {"lpll", "bpll", "dpll", "gpll"};
1192
1193 static struct rk_clk_armclk_rates rk3399_armclkl_rates[] = {
1194         {
1195                 .freq = 1800000000,
1196                 .div = 1,
1197         },
1198         {
1199                 .freq = 1704000000,
1200                 .div = 1,
1201         },
1202         {
1203                 .freq = 1608000000,
1204                 .div = 1,
1205         },
1206         {
1207                 .freq = 1512000000,
1208                 .div = 1,
1209         },
1210         {
1211                 .freq = 1488000000,
1212                 .div = 1,
1213         },
1214         {
1215                 .freq = 1416000000,
1216                 .div = 1,
1217         },
1218         {
1219                 .freq = 1200000000,
1220                 .div = 1,
1221         },
1222         {
1223                 .freq = 1008000000,
1224                 .div = 1,
1225         },
1226         {
1227                 .freq = 816000000,
1228                 .div = 1,
1229         },
1230         {
1231                 .freq = 696000000,
1232                 .div = 1,
1233         },
1234         {
1235                 .freq = 600000000,
1236                 .div = 1,
1237         },
1238         {
1239                 .freq = 408000000,
1240                 .div = 1,
1241         },
1242         {
1243                 .freq = 312000000,
1244                 .div = 1,
1245         },
1246         {
1247                 .freq = 216000000,
1248                 .div = 1,
1249         },
1250         {
1251                 .freq = 96000000,
1252                 .div = 1,
1253         },
1254 };
1255
1256 static struct rk_clk_armclk_def armclk_l = {
1257         .clkdef = {
1258                 .id = ARMCLKL,
1259                 .name = "armclkl",
1260                 .parent_names = armclk_parents,
1261                 .parent_cnt = nitems(armclk_parents),
1262         },
1263         /* CRU_CLKSEL_CON0 */
1264         .muxdiv_offset = 0x100,
1265         .mux_shift = 6,
1266         .mux_width = 2,
1267
1268         .div_shift = 0,
1269         .div_width = 5,
1270
1271         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1272         .main_parent = 0,
1273         .alt_parent = 3,
1274
1275         .rates = rk3399_armclkl_rates,
1276         .nrates = nitems(rk3399_armclkl_rates),
1277 };
1278
1279 static struct rk_clk_armclk_rates rk3399_armclkb_rates[] = {
1280         {
1281                 .freq = 2208000000,
1282                 .div = 1,
1283         },
1284         {
1285                 .freq = 2184000000,
1286                 .div = 1,
1287         },
1288         {
1289                 .freq = 2088000000,
1290                 .div = 1,
1291         },
1292         {
1293                 .freq = 2040000000,
1294                 .div = 1,
1295         },
1296         {
1297                 .freq = 2016000000,
1298                 .div = 1,
1299         },
1300         {
1301                 .freq = 1992000000,
1302                 .div = 1,
1303         },
1304         {
1305                 .freq = 1896000000,
1306                 .div = 1,
1307         },
1308         {
1309                 .freq = 1800000000,
1310                 .div = 1,
1311         },
1312         {
1313                 .freq = 1704000000,
1314                 .div = 1,
1315         },
1316         {
1317                 .freq = 1608000000,
1318                 .div = 1,
1319         },
1320         {
1321                 .freq = 1512000000,
1322                 .div = 1,
1323         },
1324         {
1325                 .freq = 1488000000,
1326                 .div = 1,
1327         },
1328         {
1329                 .freq = 1416000000,
1330                 .div = 1,
1331         },
1332         {
1333                 .freq = 1200000000,
1334                 .div = 1,
1335         },
1336         {
1337                 .freq = 1008000000,
1338                 .div = 1,
1339         },
1340         {
1341                 .freq = 816000000,
1342                 .div = 1,
1343         },
1344         {
1345                 .freq = 696000000,
1346                 .div = 1,
1347         },
1348         {
1349                 .freq = 600000000,
1350                 .div = 1,
1351         },
1352         {
1353                 .freq = 408000000,
1354                 .div = 1,
1355         },
1356         {
1357                 .freq = 312000000,
1358                 .div = 1,
1359         },
1360         {
1361                 .freq = 216000000,
1362                 .div = 1,
1363         },
1364         {
1365                 .freq = 96000000,
1366                 .div = 1,
1367         },
1368 };
1369
1370 static struct rk_clk_armclk_def armclk_b = {
1371         .clkdef = {
1372                 .id = ARMCLKB,
1373                 .name = "armclkb",
1374                 .parent_names = armclk_parents,
1375                 .parent_cnt = nitems(armclk_parents),
1376         },
1377         .muxdiv_offset = 0x108,
1378         .mux_shift = 6,
1379         .mux_width = 2,
1380
1381         .div_shift = 0,
1382         .div_width = 5,
1383
1384         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1385         .main_parent = 1,
1386         .alt_parent = 3,
1387
1388         .rates = rk3399_armclkb_rates,
1389         .nrates = nitems(rk3399_armclkb_rates),
1390 };
1391
1392 /*
1393  * sdmmc
1394  */
1395
1396 #define HCLK_SD         461
1397
1398 static const char *hclk_sd_parents[] = {"cpll", "gpll"};
1399
1400 static struct rk_clk_composite_def hclk_sd = {
1401         .clkdef = {
1402                 .id = HCLK_SD,
1403                 .name = "hclk_sd",
1404                 .parent_names = hclk_sd_parents,
1405                 .parent_cnt = nitems(hclk_sd_parents),
1406         },
1407
1408         .muxdiv_offset = 0x134,
1409         .mux_shift = 15,
1410         .mux_width = 1,
1411
1412         .div_shift = 8,
1413         .div_width = 5,
1414
1415         .gate_offset = 0x330,
1416         .gate_shift = 13,
1417
1418         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1419 };
1420
1421 #define SCLK_SDMMC              76
1422
1423 static const char *sclk_sdmmc_parents[] = {"cpll", "gpll", "npll", "ppll"};
1424
1425 static struct rk_clk_composite_def sclk_sdmmc = {
1426         .clkdef = {
1427                 .id = SCLK_SDMMC,
1428                 .name = "sclk_sdmmc",
1429                 .parent_names = sclk_sdmmc_parents,
1430                 .parent_cnt = nitems(sclk_sdmmc_parents),
1431         },
1432
1433         .muxdiv_offset = 0x140,
1434         .mux_shift = 8,
1435         .mux_width = 3,
1436
1437         .div_shift = 0,
1438         .div_width = 7,
1439
1440         .gate_offset = 0x318,
1441         .gate_shift = 1,
1442
1443         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1444 };
1445
1446 static struct rk_clk rk3399_clks[] = {
1447         {
1448                 .type = RK3399_CLK_PLL,
1449                 .clk.pll = &lpll
1450         },
1451         {
1452                 .type = RK3399_CLK_PLL,
1453                 .clk.pll = &bpll
1454         },
1455         {
1456                 .type = RK3399_CLK_PLL,
1457                 .clk.pll = &dpll
1458         },
1459         {
1460                 .type = RK3399_CLK_PLL,
1461                 .clk.pll = &cpll
1462         },
1463         {
1464                 .type = RK3399_CLK_PLL,
1465                 .clk.pll = &gpll
1466         },
1467         {
1468                 .type = RK3399_CLK_PLL,
1469                 .clk.pll = &npll
1470         },
1471         {
1472                 .type = RK3399_CLK_PLL,
1473                 .clk.pll = &vpll
1474         },
1475
1476         {
1477                 .type = RK_CLK_COMPOSITE,
1478                 .clk.composite = &aclk_perihp,
1479         },
1480         {
1481                 .type = RK_CLK_COMPOSITE,
1482                 .clk.composite = &hclk_perihp,
1483         },
1484         {
1485                 .type = RK_CLK_COMPOSITE,
1486                 .clk.composite = &pclk_perihp,
1487         },
1488         {
1489                 .type = RK_CLK_COMPOSITE,
1490                 .clk.composite = &aclk_perilp0,
1491         },
1492         {
1493                 .type = RK_CLK_COMPOSITE,
1494                 .clk.composite = &hclk_perilp0,
1495         },
1496         {
1497                 .type = RK_CLK_COMPOSITE,
1498                 .clk.composite = &pclk_perilp0,
1499         },
1500         {
1501                 .type = RK_CLK_COMPOSITE,
1502                 .clk.composite = &pclk_alive,
1503         },
1504         {
1505                 .type = RK_CLK_COMPOSITE,
1506                 .clk.composite = &hclk_perilp1,
1507         },
1508         {
1509                 .type = RK_CLK_COMPOSITE,
1510                 .clk.composite = &pclk_perilp1,
1511         },
1512         {
1513                 .type = RK_CLK_COMPOSITE,
1514                 .clk.composite = &i2c1,
1515         },
1516         {
1517                 .type = RK_CLK_COMPOSITE,
1518                 .clk.composite = &i2c2,
1519         },
1520         {
1521                 .type = RK_CLK_COMPOSITE,
1522                 .clk.composite = &i2c3,
1523         },
1524         {
1525                 .type = RK_CLK_COMPOSITE,
1526                 .clk.composite = &i2c5,
1527         },
1528         {
1529                 .type = RK_CLK_COMPOSITE,
1530                 .clk.composite = &i2c6,
1531         },
1532         {
1533                 .type = RK_CLK_COMPOSITE,
1534                 .clk.composite = &i2c7,
1535         },
1536
1537         {
1538                 .type = RK_CLK_ARMCLK,
1539                 .clk.armclk = &armclk_l,
1540         },
1541         {
1542                 .type = RK_CLK_ARMCLK,
1543                 .clk.armclk = &armclk_b,
1544         },
1545
1546         {
1547                 .type = RK_CLK_COMPOSITE,
1548                 .clk.composite = &hclk_sd,
1549         },
1550         {
1551                 .type = RK_CLK_COMPOSITE,
1552                 .clk.composite = &sclk_sdmmc,
1553         },
1554 };
1555
1556 static int
1557 rk3399_cru_probe(device_t dev)
1558 {
1559
1560         if (!ofw_bus_status_okay(dev))
1561                 return (ENXIO);
1562
1563         if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) {
1564                 device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit");
1565                 return (BUS_PROBE_DEFAULT);
1566         }
1567
1568         return (ENXIO);
1569 }
1570
1571 static int
1572 rk3399_cru_attach(device_t dev)
1573 {
1574         struct rk_cru_softc *sc;
1575
1576         sc = device_get_softc(dev);
1577         sc->dev = dev;
1578
1579         sc->gates = rk3399_gates;
1580         sc->ngates = nitems(rk3399_gates);
1581
1582         sc->clks = rk3399_clks;
1583         sc->nclks = nitems(rk3399_clks);
1584
1585         return (rk_cru_attach(dev));
1586 }
1587
1588 static device_method_t rk3399_cru_methods[] = {
1589         /* Device interface */
1590         DEVMETHOD(device_probe,         rk3399_cru_probe),
1591         DEVMETHOD(device_attach,        rk3399_cru_attach),
1592
1593         DEVMETHOD_END
1594 };
1595
1596 static devclass_t rk3399_cru_devclass;
1597
1598 DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods,
1599   sizeof(struct rk_cru_softc), rk_cru_driver);
1600
1601 EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver,
1602     rk3399_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);