sys/arm64/rockchip/clk/rk3399_cru.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
   5  * Copyright (c) 2018 Greg V <greg@unrelenting.technology>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/rman.h>
  38 #include <sys/kernel.h>
  39 #include <sys/module.h>
  40 #include <machine/bus.h>
  41
  42 #include <dev/fdt/simplebus.h>
  43
  44 #include <dev/ofw/ofw_bus.h>
  45 #include <dev/ofw/ofw_bus_subr.h>
  46
  47 #include <dev/extres/clk/clk_div.h>
  48 #include <dev/extres/clk/clk_fixed.h>
  49 #include <dev/extres/clk/clk_mux.h>
  50
  51 #include <arm64/rockchip/clk/rk_cru.h>
  52
  53 /* GATES */
  54
  55 #define ACLK_EMMC_CORE          241
  56 #define ACLK_EMMC_NOC           242
  57 #define ACLK_EMMC_GRF           243
  58 #define PCLK_GPIO2              336
  59 #define PCLK_GPIO3              337
  60 #define PCLK_GPIO4              338
  61 #define PCLK_I2C1               341
  62 #define PCLK_I2C2               342
  63 #define PCLK_I2C3               343
  64 #define PCLK_I2C5               344
  65 #define PCLK_I2C6               345
  66 #define PCLK_I2C7               346
  67 #define HCLK_SDMMC              462
  68
  69 static struct rk_cru_gate rk3399_gates[] = {
  70         /* CRU_CLKGATE_CON0 */
  71         CRU_GATE(0, "clk_core_l_lpll_src", "lpll", 0x300, 0)
  72         CRU_GATE(0, "clk_core_l_bpll_src", "bpll", 0x300, 1)
  73         CRU_GATE(0, "clk_core_l_dpll_src", "dpll", 0x300, 2)
  74         CRU_GATE(0, "clk_core_l_gpll_src", "gpll", 0x300, 3)
  75
  76         /* CRU_CLKGATE_CON1 */
  77         CRU_GATE(0, "clk_core_b_lpll_src", "lpll", 0x304, 0)
  78         CRU_GATE(0, "clk_core_b_bpll_src", "bpll", 0x304, 1)
  79         CRU_GATE(0, "clk_core_b_dpll_src", "dpll", 0x304, 2)
  80         CRU_GATE(0, "clk_core_b_gpll_src", "gpll", 0x304, 3)
  81
  82         /* CRU_CLKGATE_CON5 */
  83         CRU_GATE(0, "cpll_aclk_perihp_src", "cpll", 0x314, 0)
  84         CRU_GATE(0, "gpll_aclk_perihp_src", "gpll", 0x314, 1)
  85
  86         /* CRU_CLKGATE_CON6 */
  87         CRU_GATE(0, "gpll_aclk_emmc_src", "gpll", 0x318, 12)
  88         CRU_GATE(0, "cpll_aclk_emmc_src", "cpll", 0x318, 13)
  89
  90         /* CRU_CLKGATE_CON7 */
  91         CRU_GATE(0, "gpll_aclk_perilp0_src", "gpll", 0x31C, 0)
  92         CRU_GATE(0, "cpll_aclk_perilp0_src", "cpll", 0x31C, 1)
  93
  94         /* CRU_CLKGATE_CON8 */
  95         CRU_GATE(0, "hclk_perilp1_cpll_src", "cpll", 0x320, 1)
  96         CRU_GATE(0, "hclk_perilp1_gpll_src", "gpll", 0x320, 0)
  97
  98         /* CRU_CLKGATE_CON22 */
  99         CRU_GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0x358, 5)
 100         CRU_GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0x358, 6)
 101         CRU_GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0x358, 7)
 102         CRU_GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0x358, 8)
 103         CRU_GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0x358, 9)
 104         CRU_GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0x358, 10)
 105
 106         /* CRU_CLKGATE_CON31 */
 107         CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3)
 108         CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4)
 109         CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5)
 110
 111         /* CRU_CLKGATE_CON32 */
 112         CRU_GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 0x380, 8)
 113         CRU_GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 0x380, 9)
 114         CRU_GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 0x380, 10)
 115
 116         /* CRU_CLKGATE_CON33 */
 117         CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0x384, 8)
 118 };
 119
 120
 121 /*
 122  * PLLs
 123  */
 124
 125 #define PLL_APLLL                       1
 126 #define PLL_APLLB                       2
 127 #define PLL_DPLL                        3
 128 #define PLL_CPLL                        4
 129 #define PLL_GPLL                        5
 130 #define PLL_NPLL                        6
 131 #define PLL_VPLL                        7
 132
 133 static struct rk_clk_pll_rate rk3399_pll_rates[] = {
 134         {
 135                 .freq = 2208000000,
 136                 .refdiv = 1,
 137                 .fbdiv = 92,
 138                 .postdiv1 = 1,
 139                 .postdiv2 = 1,
 140                 .dsmpd = 1,
 141         },
 142         {
 143                 .freq = 2184000000,
 144                 .refdiv = 1,
 145                 .fbdiv = 91,
 146                 .postdiv1 = 1,
 147                 .postdiv2 = 1,
 148                 .dsmpd = 1,
 149         },
 150         {
 151                 .freq = 2160000000,
 152                 .refdiv = 1,
 153                 .fbdiv = 90,
 154                 .postdiv1 = 1,
 155                 .postdiv2 = 1,
 156                 .dsmpd = 1,
 157         },
 158         {
 159                 .freq = 2136000000,
 160                 .refdiv = 1,
 161                 .fbdiv = 89,
 162                 .postdiv1 = 1,
 163                 .postdiv2 = 1,
 164                 .dsmpd = 1,
 165         },
 166         {
 167                 .freq = 2112000000,
 168                 .refdiv = 1,
 169                 .fbdiv = 88,
 170                 .postdiv1 = 1,
 171                 .postdiv2 = 1,
 172                 .dsmpd = 1,
 173         },
 174         {
 175                 .freq = 2088000000,
 176                 .refdiv = 1,
 177                 .fbdiv = 87,
 178                 .postdiv1 = 1,
 179                 .postdiv2 = 1,
 180                 .dsmpd = 1,
 181         },
 182         {
 183                 .freq = 2064000000,
 184                 .refdiv = 1,
 185                 .fbdiv = 86,
 186                 .postdiv1 = 1,
 187                 .postdiv2 = 1,
 188                 .dsmpd = 1,
 189         },
 190         {
 191                 .freq = 2040000000,
 192                 .refdiv = 1,
 193                 .fbdiv = 85,
 194                 .postdiv1 = 1,
 195                 .postdiv2 = 1,
 196                 .dsmpd = 1,
 197         },
 198         {
 199                 .freq = 2016000000,
 200                 .refdiv = 1,
 201                 .fbdiv = 84,
 202                 .postdiv1 = 1,
 203                 .postdiv2 = 1,
 204                 .dsmpd = 1,
 205         },
 206         {
 207                 .freq = 1992000000,
 208                 .refdiv = 1,
 209                 .fbdiv = 83,
 210                 .postdiv1 = 1,
 211                 .postdiv2 = 1,
 212                 .dsmpd = 1,
 213         },
 214         {
 215                 .freq = 1968000000,
 216                 .refdiv = 1,
 217                 .fbdiv = 82,
 218                 .postdiv1 = 1,
 219                 .postdiv2 = 1,
 220                 .dsmpd = 1,
 221         },
 222         {
 223                 .freq = 1944000000,
 224                 .refdiv = 1,
 225                 .fbdiv = 81,
 226                 .postdiv1 = 1,
 227                 .postdiv2 = 1,
 228                 .dsmpd = 1,
 229         },
 230         {
 231                 .freq = 1920000000,
 232                 .refdiv = 1,
 233                 .fbdiv = 80,
 234                 .postdiv1 = 1,
 235                 .postdiv2 = 1,
 236                 .dsmpd = 1,
 237         },
 238         {
 239                 .freq = 1896000000,
 240                 .refdiv = 1,
 241                 .fbdiv = 79,
 242                 .postdiv1 = 1,
 243                 .postdiv2 = 1,
 244                 .dsmpd = 1,
 245         },
 246         {
 247                 .freq = 1872000000,
 248                 .refdiv = 1,
 249                 .fbdiv = 78,
 250                 .postdiv1 = 1,
 251                 .postdiv2 = 1,
 252                 .dsmpd = 1,
 253         },
 254         {
 255                 .freq = 1848000000,
 256                 .refdiv = 1,
 257                 .fbdiv = 77,
 258                 .postdiv1 = 1,
 259                 .postdiv2 = 1,
 260                 .dsmpd = 1,
 261         },
 262         {
 263                 .freq = 1824000000,
 264                 .refdiv = 1,
 265                 .fbdiv = 76,
 266                 .postdiv1 = 1,
 267                 .postdiv2 = 1,
 268                 .dsmpd = 1,
 269         },
 270         {
 271                 .freq = 1800000000,
 272                 .refdiv = 1,
 273                 .fbdiv = 75,
 274                 .postdiv1 = 1,
 275                 .postdiv2 = 1,
 276                 .dsmpd = 1,
 277         },
 278         {
 279                 .freq = 1776000000,
 280                 .refdiv = 1,
 281                 .fbdiv = 74,
 282                 .postdiv1 = 1,
 283                 .postdiv2 = 1,
 284                 .dsmpd = 1,
 285         },
 286         {
 287                 .freq = 1752000000,
 288                 .refdiv = 1,
 289                 .fbdiv = 73,
 290                 .postdiv1 = 1,
 291                 .postdiv2 = 1,
 292                 .dsmpd = 1,
 293         },
 294         {
 295                 .freq = 1728000000,
 296                 .refdiv = 1,
 297                 .fbdiv = 72,
 298                 .postdiv1 = 1,
 299                 .postdiv2 = 1,
 300                 .dsmpd = 1,
 301         },
 302         {
 303                 .freq = 1704000000,
 304                 .refdiv = 1,
 305                 .fbdiv = 71,
 306                 .postdiv1 = 1,
 307                 .postdiv2 = 1,
 308                 .dsmpd = 1,
 309         },
 310         {
 311                 .freq = 1680000000,
 312                 .refdiv = 1,
 313                 .fbdiv = 70,
 314                 .postdiv1 = 1,
 315                 .postdiv2 = 1,
 316                 .dsmpd = 1,
 317         },
 318         {
 319                 .freq = 1656000000,
 320                 .refdiv = 1,
 321                 .fbdiv = 69,
 322                 .postdiv1 = 1,
 323                 .postdiv2 = 1,
 324                 .dsmpd = 1,
 325         },
 326         {
 327                 .freq = 1632000000,
 328                 .refdiv = 1,
 329                 .fbdiv = 68,
 330                 .postdiv1 = 1,
 331                 .postdiv2 = 1,
 332                 .dsmpd = 1,
 333         },
 334         {
 335                 .freq = 1608000000,
 336                 .refdiv = 1,
 337                 .fbdiv = 67,
 338                 .postdiv1 = 1,
 339                 .postdiv2 = 1,
 340                 .dsmpd = 1,
 341         },
 342         {
 343                 .freq = 1600000000,
 344                 .refdiv = 3,
 345                 .fbdiv = 200,
 346                 .postdiv1 = 1,
 347                 .postdiv2 = 1,
 348                 .dsmpd = 1,
 349         },
 350         {
 351                 .freq = 1584000000,
 352                 .refdiv = 1,
 353                 .fbdiv = 66,
 354                 .postdiv1 = 1,
 355                 .postdiv2 = 1,
 356                 .dsmpd = 1,
 357         },
 358         {
 359                 .freq = 1560000000,
 360                 .refdiv = 1,
 361                 .fbdiv = 65,
 362                 .postdiv1 = 1,
 363                 .postdiv2 = 1,
 364                 .dsmpd = 1,
 365         },
 366         {
 367                 .freq = 1536000000,
 368                 .refdiv = 1,
 369                 .fbdiv = 64,
 370                 .postdiv1 = 1,
 371                 .postdiv2 = 1,
 372                 .dsmpd = 1,
 373         },
 374         {
 375                 .freq = 1512000000,
 376                 .refdiv = 1,
 377                 .fbdiv = 63,
 378                 .postdiv1 = 1,
 379                 .postdiv2 = 1,
 380                 .dsmpd = 1,
 381         },
 382         {
 383                 .freq = 1488000000,
 384                 .refdiv = 1,
 385                 .fbdiv = 62,
 386                 .postdiv1 = 1,
 387                 .postdiv2 = 1,
 388                 .dsmpd = 1,
 389         },
 390         {
 391                 .freq = 1464000000,
 392                 .refdiv = 1,
 393                 .fbdiv = 61,
 394                 .postdiv1 = 1,
 395                 .postdiv2 = 1,
 396                 .dsmpd = 1,
 397         },
 398         {
 399                 .freq = 1440000000,
 400                 .refdiv = 1,
 401                 .fbdiv = 60,
 402                 .postdiv1 = 1,
 403                 .postdiv2 = 1,
 404                 .dsmpd = 1,
 405         },
 406         {
 407                 .freq = 1416000000,
 408                 .refdiv = 1,
 409                 .fbdiv = 59,
 410                 .postdiv1 = 1,
 411                 .postdiv2 = 1,
 412                 .dsmpd = 1,
 413         },
 414         {
 415                 .freq = 1392000000,
 416                 .refdiv = 1,
 417                 .fbdiv = 58,
 418                 .postdiv1 = 1,
 419                 .postdiv2 = 1,
 420                 .dsmpd = 1,
 421         },
 422         {
 423                 .freq = 1368000000,
 424                 .refdiv = 1,
 425                 .fbdiv = 57,
 426                 .postdiv1 = 1,
 427                 .postdiv2 = 1,
 428                 .dsmpd = 1,
 429         },
 430         {
 431                 .freq = 1344000000,
 432                 .refdiv = 1,
 433                 .fbdiv = 56,
 434                 .postdiv1 = 1,
 435                 .postdiv2 = 1,
 436                 .dsmpd = 1,
 437         },
 438         {
 439                 .freq = 1320000000,
 440                 .refdiv = 1,
 441                 .fbdiv = 55,
 442                 .postdiv1 = 1,
 443                 .postdiv2 = 1,
 444                 .dsmpd = 1,
 445         },
 446         {
 447                 .freq = 1296000000,
 448                 .refdiv = 1,
 449                 .fbdiv = 54,
 450                 .postdiv1 = 1,
 451                 .postdiv2 = 1,
 452                 .dsmpd = 1,
 453         },
 454         {
 455                 .freq = 1272000000,
 456                 .refdiv = 1,
 457                 .fbdiv = 53,
 458                 .postdiv1 = 1,
 459                 .postdiv2 = 1,
 460                 .dsmpd = 1,
 461         },
 462         {
 463                 .freq = 1248000000,
 464                 .refdiv = 1,
 465                 .fbdiv = 52,
 466                 .postdiv1 = 1,
 467                 .postdiv2 = 1,
 468                 .dsmpd = 1,
 469         },
 470         {
 471                 .freq = 1200000000,
 472                 .refdiv = 1,
 473                 .fbdiv = 50,
 474                 .postdiv1 = 1,
 475                 .postdiv2 = 1,
 476                 .dsmpd = 1,
 477         },
 478         {
 479                 .freq = 1188000000,
 480                 .refdiv = 2,
 481                 .fbdiv = 99,
 482                 .postdiv1 = 1,
 483                 .postdiv2 = 1,
 484                 .dsmpd = 1,
 485         },
 486         {
 487                 .freq = 1104000000,
 488                 .refdiv = 1,
 489                 .fbdiv = 46,
 490                 .postdiv1 = 1,
 491                 .postdiv2 = 1,
 492                 .dsmpd = 1,
 493         },
 494         {
 495                 .freq = 1100000000,
 496                 .refdiv = 12,
 497                 .fbdiv = 550,
 498                 .postdiv1 = 1,
 499                 .postdiv2 = 1,
 500                 .dsmpd = 1,
 501         },
 502         {
 503                 .freq = 1008000000,
 504                 .refdiv = 1,
 505                 .fbdiv = 84,
 506                 .postdiv1 = 2,
 507                 .postdiv2 = 1,
 508                 .dsmpd = 1,
 509         },
 510         {
 511                 .freq = 1000000000,
 512                 .refdiv = 1,
 513                 .fbdiv = 125,
 514                 .postdiv1 = 3,
 515                 .postdiv2 = 1,
 516                 .dsmpd = 1,
 517         },
 518         {
 519                 .freq = 984000000,
 520                 .refdiv = 1,
 521                 .fbdiv = 82,
 522                 .postdiv1 = 2,
 523                 .postdiv2 = 1,
 524                 .dsmpd = 1,
 525         },
 526         {
 527                 .freq = 960000000,
 528                 .refdiv = 1,
 529                 .fbdiv = 80,
 530                 .postdiv1 = 2,
 531                 .postdiv2 = 1,
 532                 .dsmpd = 1,
 533         },
 534         {
 535                 .freq = 936000000,
 536                 .refdiv = 1,
 537                 .fbdiv = 78,
 538                 .postdiv1 = 2,
 539                 .postdiv2 = 1,
 540                 .dsmpd = 1,
 541         },
 542         {
 543                 .freq = 912000000,
 544                 .refdiv = 1,
 545                 .fbdiv = 76,
 546                 .postdiv1 = 2,
 547                 .postdiv2 = 1,
 548                 .dsmpd = 1,
 549         },
 550         {
 551                 .freq = 900000000,
 552                 .refdiv = 4,
 553                 .fbdiv = 300,
 554                 .postdiv1 = 2,
 555                 .postdiv2 = 1,
 556                 .dsmpd = 1,
 557         },
 558         {
 559                 .freq = 888000000,
 560                 .refdiv = 1,
 561                 .fbdiv = 74,
 562                 .postdiv1 = 2,
 563                 .postdiv2 = 1,
 564                 .dsmpd = 1,
 565         },
 566         {
 567                 .freq = 864000000,
 568                 .refdiv = 1,
 569                 .fbdiv = 72,
 570                 .postdiv1 = 2,
 571                 .postdiv2 = 1,
 572                 .dsmpd = 1,
 573         },
 574         {
 575                 .freq = 840000000,
 576                 .refdiv = 1,
 577                 .fbdiv = 70,
 578                 .postdiv1 = 2,
 579                 .postdiv2 = 1,
 580                 .dsmpd = 1,
 581         },
 582         {
 583                 .freq = 816000000,
 584                 .refdiv = 1,
 585                 .fbdiv = 68,
 586                 .postdiv1 = 2,
 587                 .postdiv2 = 1,
 588                 .dsmpd = 1,
 589         },
 590         {
 591                 .freq = 800000000,
 592                 .refdiv = 1,
 593                 .fbdiv = 100,
 594                 .postdiv1 = 3,
 595                 .postdiv2 = 1,
 596                 .dsmpd = 1,
 597         },
 598         {
 599                 .freq = 700000000,
 600                 .refdiv = 6,
 601                 .fbdiv = 350,
 602                 .postdiv1 = 2,
 603                 .postdiv2 = 1,
 604                 .dsmpd = 1,
 605         },
 606         {
 607                 .freq = 696000000,
 608                 .refdiv = 1,
 609                 .fbdiv = 58,
 610                 .postdiv1 = 2,
 611                 .postdiv2 = 1,
 612                 .dsmpd = 1,
 613         },
 614         {
 615                 .freq = 676000000,
 616                 .refdiv = 3,
 617                 .fbdiv = 169,
 618                 .postdiv1 = 2,
 619                 .postdiv2 = 1,
 620                 .dsmpd = 1,
 621         },
 622         {
 623                 .freq = 600000000,
 624                 .refdiv = 1,
 625                 .fbdiv = 75,
 626                 .postdiv1 = 3,
 627                 .postdiv2 = 1,
 628                 .dsmpd = 1,
 629         },
 630         {
 631                 .freq = 594000000,
 632                 .refdiv = 1,
 633                 .fbdiv = 99,
 634                 .postdiv1 = 4,
 635                 .postdiv2 = 1,
 636                 .dsmpd = 1,
 637         },
 638         {
 639                 .freq = 533250000,
 640                 .refdiv = 8,
 641                 .fbdiv = 711,
 642                 .postdiv1 = 4,
 643                 .postdiv2 = 1,
 644                 .dsmpd = 1,
 645         },
 646         {
 647                 .freq = 504000000,
 648                 .refdiv = 1,
 649                 .fbdiv = 63,
 650                 .postdiv1 = 3,
 651                 .postdiv2 = 1,
 652                 .dsmpd = 1,
 653         },
 654         {
 655                 .freq = 500000000,
 656                 .refdiv = 6,
 657                 .fbdiv = 250,
 658                 .postdiv1 = 2,
 659                 .postdiv2 = 1,
 660                 .dsmpd = 1,
 661         },
 662         {
 663                 .freq = 408000000,
 664                 .refdiv = 1,
 665                 .fbdiv = 68,
 666                 .postdiv1 = 2,
 667                 .postdiv2 = 2,
 668                 .dsmpd = 1,
 669         },
 670         {
 671                 .freq = 312000000,
 672                 .refdiv = 1,
 673                 .fbdiv = 52,
 674                 .postdiv1 = 2,
 675                 .postdiv2 = 2,
 676                 .dsmpd = 1,
 677         },
 678         {
 679                 .freq = 297000000,
 680                 .refdiv = 1,
 681                 .fbdiv = 99,
 682                 .postdiv1 = 4,
 683                 .postdiv2 = 2,
 684                 .dsmpd = 1,
 685         },
 686         {
 687                 .freq = 216000000,
 688                 .refdiv = 1,
 689                 .fbdiv = 72,
 690                 .postdiv1 = 4,
 691                 .postdiv2 = 2,
 692                 .dsmpd = 1,
 693         },
 694         {
 695                 .freq = 148500000,
 696                 .refdiv = 1,
 697                 .fbdiv = 99,
 698                 .postdiv1 = 4,
 699                 .postdiv2 = 4,
 700                 .dsmpd = 1,
 701         },
 702         {
 703                 .freq = 106500000,
 704                 .refdiv = 1,
 705                 .fbdiv = 71,
 706                 .postdiv1 = 4,
 707                 .postdiv2 = 4,
 708                 .dsmpd = 1,
 709         },
 710         {
 711                 .freq = 96000000,
 712                 .refdiv = 1,
 713                 .fbdiv = 64,
 714                 .postdiv1 = 4,
 715                 .postdiv2 = 4,
 716                 .dsmpd = 1,
 717         },
 718         {
 719                 .freq = 74250000,
 720                 .refdiv = 2,
 721                 .fbdiv = 99,
 722                 .postdiv1 = 4,
 723                 .postdiv2 = 4,
 724                 .dsmpd = 1,
 725         },
 726         {
 727                 .freq = 65000000,
 728                 .refdiv = 1,
 729                 .fbdiv = 65,
 730                 .postdiv1 = 6,
 731                 .postdiv2 = 4,
 732                 .dsmpd = 1,
 733         },
 734         {
 735                 .freq = 54000000,
 736                 .refdiv = 1,
 737                 .fbdiv = 54,
 738                 .postdiv1 = 6,
 739                 .postdiv2 = 4,
 740                 .dsmpd = 1,
 741         },
 742         {
 743                 .freq = 27000000,
 744                 .refdiv = 1,
 745                 .fbdiv = 27,
 746                 .postdiv1 = 6,
 747                 .postdiv2 = 4,
 748                 .dsmpd = 1,
 749         },
 750         {},
 751 };
 752
 753 static const char *pll_parents[] = {"xin24m"};
 754
 755 static struct rk_clk_pll_def lpll = {
 756         .clkdef = {
 757                 .id = PLL_APLLL,
 758                 .name = "lpll",
 759                 .parent_names = pll_parents,
 760                 .parent_cnt = nitems(pll_parents),
 761         },
 762         .base_offset = 0x00,
 763         .gate_offset = 0x300,
 764         .gate_shift = 0,
 765         .flags = RK_CLK_PLL_HAVE_GATE,
 766         .rates = rk3399_pll_rates,
 767 };
 768
 769 static struct rk_clk_pll_def bpll = {
 770         .clkdef = {
 771                 .id = PLL_APLLB,
 772                 .name = "bpll",
 773                 .parent_names = pll_parents,
 774                 .parent_cnt = nitems(pll_parents),
 775         },
 776         .base_offset = 0x20,
 777         .gate_offset = 0x300,
 778         .gate_shift = 1,
 779         .flags = RK_CLK_PLL_HAVE_GATE,
 780         .rates = rk3399_pll_rates,
 781 };
 782
 783 static struct rk_clk_pll_def dpll = {
 784         .clkdef = {
 785                 .id = PLL_DPLL,
 786                 .name = "dpll",
 787                 .parent_names = pll_parents,
 788                 .parent_cnt = nitems(pll_parents),
 789         },
 790         .base_offset = 0x40,
 791         .gate_offset = 0x300,
 792         .gate_shift = 2,
 793         .flags = RK_CLK_PLL_HAVE_GATE,
 794         .rates = rk3399_pll_rates,
 795 };
 796
 797
 798 static struct rk_clk_pll_def cpll = {
 799         .clkdef = {
 800                 .id = PLL_CPLL,
 801                 .name = "cpll",
 802                 .parent_names = pll_parents,
 803                 .parent_cnt = nitems(pll_parents),
 804         },
 805         .base_offset = 0x60,
 806         .rates = rk3399_pll_rates,
 807 };
 808
 809 static struct rk_clk_pll_def gpll = {
 810         .clkdef = {
 811                 .id = PLL_GPLL,
 812                 .name = "gpll",
 813                 .parent_names = pll_parents,
 814                 .parent_cnt = nitems(pll_parents),
 815         },
 816         .base_offset = 0x80,
 817         .gate_offset = 0x300,
 818         .gate_shift = 3,
 819         .flags = RK_CLK_PLL_HAVE_GATE,
 820         .rates = rk3399_pll_rates,
 821 };
 822
 823 static struct rk_clk_pll_def npll = {
 824         .clkdef = {
 825                 .id = PLL_NPLL,
 826                 .name = "npll",
 827                 .parent_names = pll_parents,
 828                 .parent_cnt = nitems(pll_parents),
 829         },
 830         .base_offset = 0xa0,
 831         .rates = rk3399_pll_rates,
 832 };
 833
 834 static struct rk_clk_pll_def vpll = {
 835         .clkdef = {
 836                 .id = PLL_VPLL,
 837                 .name = "vpll",
 838                 .parent_names = pll_parents,
 839                 .parent_cnt = nitems(pll_parents),
 840         },
 841         .base_offset = 0xc0,
 842         .rates = rk3399_pll_rates,
 843 };
 844
 845 #define ACLK_PERIHP     192
 846 #define HCLK_PERIHP     448
 847 #define PCLK_PERIHP     320
 848
 849 static const char *aclk_perihp_parents[] = {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src"};
 850
 851 static struct rk_clk_composite_def aclk_perihp = {
 852         .clkdef = {
 853                 .id = ACLK_PERIHP,
 854                 .name = "aclk_perihp",
 855                 .parent_names = aclk_perihp_parents,
 856                 .parent_cnt = nitems(aclk_perihp_parents),
 857         },
 858         /* CRU_CLKSEL_CON14 */
 859         .muxdiv_offset = 0x138,
 860
 861         .mux_shift = 7,
 862         .mux_width = 1,
 863
 864         .div_shift = 0,
 865         .div_width = 5,
 866
 867         /* CRU_CLKGATE_CON5 */
 868         .gate_offset = 0x314,
 869         .gate_shift = 2,
 870
 871         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 872 };
 873
 874 static const char *hclk_pclk_perihp_parents[] = {"aclk_perihp"};
 875
 876 static struct rk_clk_composite_def hclk_perihp = {
 877         .clkdef = {
 878                 .id = HCLK_PERIHP,
 879                 .name = "hclk_perihp",
 880                 .parent_names = hclk_pclk_perihp_parents,
 881                 .parent_cnt = nitems(hclk_pclk_perihp_parents),
 882         },
 883         /* CRU_CLKSEL_CON14 */
 884         .muxdiv_offset = 0x138,
 885
 886         .div_shift = 8,
 887         .div_width = 2,
 888
 889         /* CRU_CLKGATE_CON5 */
 890         .gate_offset = 0x314,
 891         .gate_shift = 3,
 892
 893         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 894 };
 895
 896 static struct rk_clk_composite_def pclk_perihp = {
 897         .clkdef = {
 898                 .id = PCLK_PERIHP,
 899                 .name = "pclk_perihp",
 900                 .parent_names = hclk_pclk_perihp_parents,
 901                 .parent_cnt = nitems(hclk_pclk_perihp_parents),
 902         },
 903         /* CRU_CLKSEL_CON14 */
 904         .muxdiv_offset = 0x138,
 905
 906         .div_shift = 12,
 907         .div_width = 3,
 908
 909         /* CRU_CLKGATE_CON5 */
 910         .gate_offset = 0x314,
 911         .gate_shift = 4,
 912
 913         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 914 };
 915
 916 #define ACLK_PERILP0    194
 917 #define HCLK_PERILP0    449
 918 #define PCLK_PERILP0    322
 919
 920 static const char *aclk_perilp0_parents[] = {"cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src"};
 921
 922 static struct rk_clk_composite_def aclk_perilp0 = {
 923         .clkdef = {
 924                 .id = ACLK_PERILP0,
 925                 .name = "aclk_perilp0",
 926                 .parent_names = aclk_perilp0_parents,
 927                 .parent_cnt = nitems(aclk_perilp0_parents),
 928         },
 929         /* CRU_CLKSEL_CON14 */
 930         .muxdiv_offset = 0x15C,
 931
 932         .mux_shift = 7,
 933         .mux_width = 1,
 934
 935         .div_shift = 0,
 936         .div_width = 5,
 937
 938         /* CRU_CLKGATE_CON7 */
 939         .gate_offset = 0x31C,
 940         .gate_shift = 2,
 941
 942         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 943 };
 944
 945 static const char *hclk_pclk_perilp0_parents[] = {"aclk_perilp0"};
 946
 947 static struct rk_clk_composite_def hclk_perilp0 = {
 948         .clkdef = {
 949                 .id = HCLK_PERILP0,
 950                 .name = "hclk_perilp0",
 951                 .parent_names = hclk_pclk_perilp0_parents,
 952                 .parent_cnt = nitems(hclk_pclk_perilp0_parents),
 953         },
 954         /* CRU_CLKSEL_CON23 */
 955         .muxdiv_offset = 0x15C,
 956
 957         .div_shift = 8,
 958         .div_width = 2,
 959
 960         /* CRU_CLKGATE_CON7 */
 961         .gate_offset = 0x31C,
 962         .gate_shift = 3,
 963
 964         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 965 };
 966
 967 static struct rk_clk_composite_def pclk_perilp0 = {
 968         .clkdef = {
 969                 .id = PCLK_PERILP0,
 970                 .name = "pclk_perilp0",
 971                 .parent_names = hclk_pclk_perilp0_parents,
 972                 .parent_cnt = nitems(hclk_pclk_perilp0_parents),
 973         },
 974         /* CRU_CLKSEL_CON23 */
 975         .muxdiv_offset = 0x15C,
 976
 977         .div_shift = 12,
 978         .div_width = 3,
 979
 980         /* CRU_CLKGATE_CON7 */
 981         .gate_offset = 0x31C,
 982         .gate_shift = 4,
 983
 984         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 985 };
 986
 987 /*
 988  * misc
 989  */
 990 #define PCLK_ALIVE              390
 991
 992 static const char *alive_parents[] = {"gpll"};
 993
 994 static struct rk_clk_composite_def pclk_alive = {
 995         .clkdef = {
 996                 .id = PCLK_ALIVE,
 997                 .name = "pclk_alive",
 998                 .parent_names = alive_parents,
 999                 .parent_cnt = nitems(alive_parents),
1000         },
1001         /* CRU_CLKSEL_CON57 */
1002         .muxdiv_offset = 0x01e4,
1003
1004         .div_shift = 0,
1005         .div_width = 5,
1006 };
1007
1008 #define HCLK_PERILP1            450
1009 #define PCLK_PERILP1            323
1010
1011 static const char *hclk_perilp1_parents[] = {"cpll", "gpll"};
1012
1013 static struct rk_clk_composite_def hclk_perilp1 = {
1014         .clkdef = {
1015                 .id = HCLK_PERILP1,
1016                 .name = "hclk_perilp1",
1017                 .parent_names = hclk_perilp1_parents,
1018                 .parent_cnt = nitems(hclk_perilp1_parents),
1019         },
1020         /* CRU_CLKSEL_CON25 */
1021         .muxdiv_offset = 0x164,
1022         .mux_shift = 7,
1023         .mux_width = 1,
1024
1025         .div_shift = 0,
1026         .div_width = 5,
1027
1028         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1029 };
1030
1031 static const char *pclk_perilp1_parents[] = {"hclk_perilp1"};
1032
1033 static struct rk_clk_composite_def pclk_perilp1 = {
1034         .clkdef = {
1035                 .id = PCLK_PERILP1,
1036                 .name = "pclk_perilp1",
1037                 .parent_names = pclk_perilp1_parents,
1038                 .parent_cnt = nitems(pclk_perilp1_parents),
1039         },
1040         /* CRU_CLKSEL_CON25 */
1041         .muxdiv_offset = 0x164,
1042
1043         .div_shift = 8,
1044         .div_width = 3,
1045
1046         /* CRU_CLKGATE_CON8 */
1047         .gate_offset = 0x320,
1048         .gate_shift = 2,
1049
1050         .flags = RK_CLK_COMPOSITE_HAVE_GATE,
1051 };
1052
1053 /*
1054  * i2c
1055  */
1056 static const char *i2c_parents[] = {"cpll", "gpll"};
1057
1058 #define SCLK_I2C1       65
1059 #define SCLK_I2C2       66
1060 #define SCLK_I2C3       67
1061 #define SCLK_I2C5       68
1062 #define SCLK_I2C6       69
1063 #define SCLK_I2C7       70
1064
1065 static struct rk_clk_composite_def i2c1 = {
1066         .clkdef = {
1067                 .id = SCLK_I2C1,
1068                 .name = "clk_i2c1",
1069                 .parent_names = i2c_parents,
1070                 .parent_cnt = nitems(i2c_parents),
1071         },
1072         /* CRU_CLKSEL_CON61 */
1073         .muxdiv_offset = 0x01f4,
1074         .mux_shift = 7,
1075         .mux_width = 1,
1076
1077         .div_shift = 0,
1078         .div_width = 7,
1079
1080         /* CRU_CLKGATE_CON10 */
1081         .gate_offset = 0x0328,
1082         .gate_shift = 0,
1083
1084         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1085 };
1086
1087 static struct rk_clk_composite_def i2c2 = {
1088         .clkdef = {
1089                 .id = SCLK_I2C2,
1090                 .name = "clk_i2c2",
1091                 .parent_names = i2c_parents,
1092                 .parent_cnt = nitems(i2c_parents),
1093         },
1094         /* CRU_CLKSEL_CON62 */
1095         .muxdiv_offset = 0x01f8,
1096         .mux_shift = 7,
1097         .mux_width = 1,
1098
1099         .div_shift = 0,
1100         .div_width = 7,
1101
1102         /* CRU_CLKGATE_CON10 */
1103         .gate_offset = 0x0328,
1104         .gate_shift = 2,
1105
1106         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1107 };
1108
1109 static struct rk_clk_composite_def i2c3 = {
1110         .clkdef = {
1111                 .id = SCLK_I2C3,
1112                 .name = "clk_i2c3",
1113                 .parent_names = i2c_parents,
1114                 .parent_cnt = nitems(i2c_parents),
1115         },
1116         /* CRU_CLKSEL_CON63 */
1117         .muxdiv_offset = 0x01fc,
1118         .mux_shift = 7,
1119         .mux_width = 1,
1120
1121         .div_shift = 0,
1122         .div_width = 7,
1123
1124         /* CRU_CLKGATE_CON10 */
1125         .gate_offset = 0x0328,
1126         .gate_shift = 4,
1127
1128         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1129 };
1130
1131 static struct rk_clk_composite_def i2c5 = {
1132         .clkdef = {
1133                 .id = SCLK_I2C5,
1134                 .name = "clk_i2c5",
1135                 .parent_names = i2c_parents,
1136                 .parent_cnt = nitems(i2c_parents),
1137         },
1138         /* CRU_CLKSEL_CON61 */
1139         .muxdiv_offset = 0x01f4,
1140         .mux_shift = 15,
1141         .mux_width = 1,
1142
1143         .div_shift = 8,
1144         .div_width = 7,
1145
1146         /* CRU_CLKGATE_CON10 */
1147         .gate_offset = 0x0328,
1148         .gate_shift = 1,
1149
1150         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1151 };
1152
1153 static struct rk_clk_composite_def i2c6 = {
1154         .clkdef = {
1155                 .id = SCLK_I2C6,
1156                 .name = "clk_i2c6",
1157                 .parent_names = i2c_parents,
1158                 .parent_cnt = nitems(i2c_parents),
1159         },
1160         /* CRU_CLKSEL_CON62 */
1161         .muxdiv_offset = 0x01f8,
1162         .mux_shift = 15,
1163         .mux_width = 1,
1164
1165         .div_shift = 8,
1166         .div_width = 7,
1167
1168         /* CRU_CLKGATE_CON10 */
1169         .gate_offset = 0x0328,
1170         .gate_shift = 3,
1171
1172         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1173 };
1174
1175 static struct rk_clk_composite_def i2c7 = {
1176         .clkdef = {
1177                 .id = SCLK_I2C7,
1178                 .name = "clk_i2c7",
1179                 .parent_names = i2c_parents,
1180                 .parent_cnt = nitems(i2c_parents),
1181         },
1182         /* CRU_CLKSEL_CON63 */
1183         .muxdiv_offset = 0x01fc,
1184         .mux_shift = 15,
1185         .mux_width = 1,
1186
1187         .div_shift = 8,
1188         .div_width = 7,
1189
1190         /* CRU_CLKGATE_CON10 */
1191         .gate_offset = 0x0328,
1192         .gate_shift = 5,
1193
1194         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1195 };
1196
1197 /*
1198  * ARM CPU clocks (LITTLE and big)
1199  */
1200 #define ARMCLKL                         8
1201 #define ARMCLKB                         9
1202
1203 static const char *armclk_parents[] = {"lpll", "bpll", "dpll", "gpll"};
1204
1205 static struct rk_clk_armclk_rates rk3399_armclkl_rates[] = {
1206         {
1207                 .freq = 1800000000,
1208                 .div = 1,
1209         },
1210         {
1211                 .freq = 1704000000,
1212                 .div = 1,
1213         },
1214         {
1215                 .freq = 1608000000,
1216                 .div = 1,
1217         },
1218         {
1219                 .freq = 1512000000,
1220                 .div = 1,
1221         },
1222         {
1223                 .freq = 1488000000,
1224                 .div = 1,
1225         },
1226         {
1227                 .freq = 1416000000,
1228                 .div = 1,
1229         },
1230         {
1231                 .freq = 1200000000,
1232                 .div = 1,
1233         },
1234         {
1235                 .freq = 1008000000,
1236                 .div = 1,
1237         },
1238         {
1239                 .freq = 816000000,
1240                 .div = 1,
1241         },
1242         {
1243                 .freq = 696000000,
1244                 .div = 1,
1245         },
1246         {
1247                 .freq = 600000000,
1248                 .div = 1,
1249         },
1250         {
1251                 .freq = 408000000,
1252                 .div = 1,
1253         },
1254         {
1255                 .freq = 312000000,
1256                 .div = 1,
1257         },
1258         {
1259                 .freq = 216000000,
1260                 .div = 1,
1261         },
1262         {
1263                 .freq = 96000000,
1264                 .div = 1,
1265         },
1266 };
1267
1268 static struct rk_clk_armclk_def armclk_l = {
1269         .clkdef = {
1270                 .id = ARMCLKL,
1271                 .name = "armclkl",
1272                 .parent_names = armclk_parents,
1273                 .parent_cnt = nitems(armclk_parents),
1274         },
1275         /* CRU_CLKSEL_CON0 */
1276         .muxdiv_offset = 0x100,
1277         .mux_shift = 6,
1278         .mux_width = 2,
1279
1280         .div_shift = 0,
1281         .div_width = 5,
1282
1283         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1284         .main_parent = 0,
1285         .alt_parent = 3,
1286
1287         .rates = rk3399_armclkl_rates,
1288         .nrates = nitems(rk3399_armclkl_rates),
1289 };
1290
1291 static struct rk_clk_armclk_rates rk3399_armclkb_rates[] = {
1292         {
1293                 .freq = 2208000000,
1294                 .div = 1,
1295         },
1296         {
1297                 .freq = 2184000000,
1298                 .div = 1,
1299         },
1300         {
1301                 .freq = 2088000000,
1302                 .div = 1,
1303         },
1304         {
1305                 .freq = 2040000000,
1306                 .div = 1,
1307         },
1308         {
1309                 .freq = 2016000000,
1310                 .div = 1,
1311         },
1312         {
1313                 .freq = 1992000000,
1314                 .div = 1,
1315         },
1316         {
1317                 .freq = 1896000000,
1318                 .div = 1,
1319         },
1320         {
1321                 .freq = 1800000000,
1322                 .div = 1,
1323         },
1324         {
1325                 .freq = 1704000000,
1326                 .div = 1,
1327         },
1328         {
1329                 .freq = 1608000000,
1330                 .div = 1,
1331         },
1332         {
1333                 .freq = 1512000000,
1334                 .div = 1,
1335         },
1336         {
1337                 .freq = 1488000000,
1338                 .div = 1,
1339         },
1340         {
1341                 .freq = 1416000000,
1342                 .div = 1,
1343         },
1344         {
1345                 .freq = 1200000000,
1346                 .div = 1,
1347         },
1348         {
1349                 .freq = 1008000000,
1350                 .div = 1,
1351         },
1352         {
1353                 .freq = 816000000,
1354                 .div = 1,
1355         },
1356         {
1357                 .freq = 696000000,
1358                 .div = 1,
1359         },
1360         {
1361                 .freq = 600000000,
1362                 .div = 1,
1363         },
1364         {
1365                 .freq = 408000000,
1366                 .div = 1,
1367         },
1368         {
1369                 .freq = 312000000,
1370                 .div = 1,
1371         },
1372         {
1373                 .freq = 216000000,
1374                 .div = 1,
1375         },
1376         {
1377                 .freq = 96000000,
1378                 .div = 1,
1379         },
1380 };
1381
1382 static struct rk_clk_armclk_def armclk_b = {
1383         .clkdef = {
1384                 .id = ARMCLKB,
1385                 .name = "armclkb",
1386                 .parent_names = armclk_parents,
1387                 .parent_cnt = nitems(armclk_parents),
1388         },
1389         .muxdiv_offset = 0x108,
1390         .mux_shift = 6,
1391         .mux_width = 2,
1392
1393         .div_shift = 0,
1394         .div_width = 5,
1395
1396         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1397         .main_parent = 1,
1398         .alt_parent = 3,
1399
1400         .rates = rk3399_armclkb_rates,
1401         .nrates = nitems(rk3399_armclkb_rates),
1402 };
1403
1404 /*
1405  * sdmmc
1406  */
1407
1408 #define HCLK_SD         461
1409
1410 static const char *hclk_sd_parents[] = {"cpll", "gpll"};
1411
1412 static struct rk_clk_composite_def hclk_sd = {
1413         .clkdef = {
1414                 .id = HCLK_SD,
1415                 .name = "hclk_sd",
1416                 .parent_names = hclk_sd_parents,
1417                 .parent_cnt = nitems(hclk_sd_parents),
1418         },
1419
1420         .muxdiv_offset = 0x134,
1421         .mux_shift = 15,
1422         .mux_width = 1,
1423
1424         .div_shift = 8,
1425         .div_width = 5,
1426
1427         .gate_offset = 0x330,
1428         .gate_shift = 13,
1429
1430         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1431 };
1432
1433 #define SCLK_SDMMC              76
1434
1435 static const char *sclk_sdmmc_parents[] = {"cpll", "gpll", "npll", "ppll"};
1436
1437 static struct rk_clk_composite_def sclk_sdmmc = {
1438         .clkdef = {
1439                 .id = SCLK_SDMMC,
1440                 .name = "sclk_sdmmc",
1441                 .parent_names = sclk_sdmmc_parents,
1442                 .parent_cnt = nitems(sclk_sdmmc_parents),
1443         },
1444
1445         .muxdiv_offset = 0x140,
1446         .mux_shift = 8,
1447         .mux_width = 3,
1448
1449         .div_shift = 0,
1450         .div_width = 7,
1451
1452         .gate_offset = 0x318,
1453         .gate_shift = 1,
1454
1455         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1456 };
1457
1458 /*
1459  * emmc
1460  */
1461
1462 #define SCLK_EMMC               78
1463
1464 static const char *sclk_emmc_parents[] = {"cpll", "gpll", "npll"};
1465
1466 static struct rk_clk_composite_def sclk_emmc = {
1467         .clkdef = {
1468                 .id = SCLK_EMMC,
1469                 .name = "sclk_emmc",
1470                 .parent_names = sclk_emmc_parents,
1471                 .parent_cnt = nitems(sclk_emmc_parents),
1472         },
1473
1474         .muxdiv_offset = 0x158,
1475         .mux_shift = 8,
1476         .mux_width = 3,
1477
1478         .div_shift = 0,
1479         .div_width = 7,
1480
1481         .gate_offset = 0x318,
1482         .gate_shift = 14,
1483
1484         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1485 };
1486
1487 #define ACLK_EMMC               240
1488
1489 static const char *aclk_emmc_parents[] = {
1490         "cpll_aclk_emmc_src",
1491         "gpll_aclk_emmc_src"
1492 };
1493
1494 static struct rk_clk_composite_def aclk_emmc = {
1495         .clkdef = {
1496                 .id = ACLK_EMMC,
1497                 .name = "aclk_emmc",
1498                 .parent_names = aclk_emmc_parents,
1499                 .parent_cnt = nitems(aclk_emmc_parents),
1500         },
1501
1502         .muxdiv_offset = 0x154,
1503         .mux_shift = 7,
1504         .mux_width = 1,
1505
1506         .div_shift = 0,
1507         .div_width = 5,
1508
1509         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1510 };
1511
1512 static struct rk_clk rk3399_clks[] = {
1513         {
1514                 .type = RK3399_CLK_PLL,
1515                 .clk.pll = &lpll
1516         },
1517         {
1518                 .type = RK3399_CLK_PLL,
1519                 .clk.pll = &bpll
1520         },
1521         {
1522                 .type = RK3399_CLK_PLL,
1523                 .clk.pll = &dpll
1524         },
1525         {
1526                 .type = RK3399_CLK_PLL,
1527                 .clk.pll = &cpll
1528         },
1529         {
1530                 .type = RK3399_CLK_PLL,
1531                 .clk.pll = &gpll
1532         },
1533         {
1534                 .type = RK3399_CLK_PLL,
1535                 .clk.pll = &npll
1536         },
1537         {
1538                 .type = RK3399_CLK_PLL,
1539                 .clk.pll = &vpll
1540         },
1541
1542         {
1543                 .type = RK_CLK_COMPOSITE,
1544                 .clk.composite = &aclk_perihp,
1545         },
1546         {
1547                 .type = RK_CLK_COMPOSITE,
1548                 .clk.composite = &hclk_perihp,
1549         },
1550         {
1551                 .type = RK_CLK_COMPOSITE,
1552                 .clk.composite = &pclk_perihp,
1553         },
1554         {
1555                 .type = RK_CLK_COMPOSITE,
1556                 .clk.composite = &aclk_perilp0,
1557         },
1558         {
1559                 .type = RK_CLK_COMPOSITE,
1560                 .clk.composite = &hclk_perilp0,
1561         },
1562         {
1563                 .type = RK_CLK_COMPOSITE,
1564                 .clk.composite = &pclk_perilp0,
1565         },
1566         {
1567                 .type = RK_CLK_COMPOSITE,
1568                 .clk.composite = &pclk_alive,
1569         },
1570         {
1571                 .type = RK_CLK_COMPOSITE,
1572                 .clk.composite = &hclk_perilp1,
1573         },
1574         {
1575                 .type = RK_CLK_COMPOSITE,
1576                 .clk.composite = &pclk_perilp1,
1577         },
1578         {
1579                 .type = RK_CLK_COMPOSITE,
1580                 .clk.composite = &i2c1,
1581         },
1582         {
1583                 .type = RK_CLK_COMPOSITE,
1584                 .clk.composite = &i2c2,
1585         },
1586         {
1587                 .type = RK_CLK_COMPOSITE,
1588                 .clk.composite = &i2c3,
1589         },
1590         {
1591                 .type = RK_CLK_COMPOSITE,
1592                 .clk.composite = &i2c5,
1593         },
1594         {
1595                 .type = RK_CLK_COMPOSITE,
1596                 .clk.composite = &i2c6,
1597         },
1598         {
1599                 .type = RK_CLK_COMPOSITE,
1600                 .clk.composite = &i2c7,
1601         },
1602
1603         {
1604                 .type = RK_CLK_ARMCLK,
1605                 .clk.armclk = &armclk_l,
1606         },
1607         {
1608                 .type = RK_CLK_ARMCLK,
1609                 .clk.armclk = &armclk_b,
1610         },
1611
1612         {
1613                 .type = RK_CLK_COMPOSITE,
1614                 .clk.composite = &hclk_sd,
1615         },
1616         {
1617                 .type = RK_CLK_COMPOSITE,
1618                 .clk.composite = &sclk_sdmmc,
1619         },
1620
1621         {
1622                 .type = RK_CLK_COMPOSITE,
1623                 .clk.composite = &sclk_emmc,
1624         },
1625         {
1626                 .type = RK_CLK_COMPOSITE,
1627                 .clk.composite = &aclk_emmc,
1628         },
1629 };
1630
1631 static int
1632 rk3399_cru_probe(device_t dev)
1633 {
1634
1635         if (!ofw_bus_status_okay(dev))
1636                 return (ENXIO);
1637
1638         if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) {
1639                 device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit");
1640                 return (BUS_PROBE_DEFAULT);
1641         }
1642
1643         return (ENXIO);
1644 }
1645
1646 static int
1647 rk3399_cru_attach(device_t dev)
1648 {
1649         struct rk_cru_softc *sc;
1650
1651         sc = device_get_softc(dev);
1652         sc->dev = dev;
1653
1654         sc->gates = rk3399_gates;
1655         sc->ngates = nitems(rk3399_gates);
1656
1657         sc->clks = rk3399_clks;
1658         sc->nclks = nitems(rk3399_clks);
1659
1660         return (rk_cru_attach(dev));
1661 }
1662
1663 static device_method_t rk3399_cru_methods[] = {
1664         /* Device interface */
1665         DEVMETHOD(device_probe,         rk3399_cru_probe),
1666         DEVMETHOD(device_attach,        rk3399_cru_attach),
1667
1668         DEVMETHOD_END
1669 };
1670
1671 static devclass_t rk3399_cru_devclass;
1672
1673 DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods,
1674   sizeof(struct rk_cru_softc), rk_cru_driver);
1675
1676 EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver,
1677     rk3399_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);