2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
5 * Copyright (c) 2018 Greg V <greg@unrelenting.technology>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <machine/bus.h>
42 #include <dev/fdt/simplebus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
47 #include <dev/extres/clk/clk_div.h>
48 #include <dev/extres/clk/clk_fixed.h>
49 #include <dev/extres/clk/clk_mux.h>
51 #include <arm64/rockchip/clk/rk_cru.h>
56 #define PCLK_GPIO0_PMU 23
57 #define PCLK_GPIO1_PMU 24
58 #define PCLK_I2C0_PMU 27
59 #define PCLK_I2C4_PMU 28
60 #define PCLK_I2C8_PMU 29
62 static struct rk_cru_gate rk3399_pmu_gates[] = {
63 /* PMUCRU_CLKGATE_CON1 */
64 CRU_GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", 0x104, 0)
65 CRU_GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0x104, 3)
66 CRU_GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0x104, 4)
67 CRU_GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0x104, 7)
68 CRU_GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0x104, 8)
69 CRU_GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0x104, 9)
79 static struct rk_clk_pll_rate rk3399_pll_rates[] = {
699 static const char *pll_parents[] = {"xin24m"};
701 static struct rk_clk_pll_def ppll = {
705 .parent_names = pll_parents,
706 .parent_cnt = nitems(pll_parents),
710 .rates = rk3399_pll_rates,
713 static const char *pmu_parents[] = {"ppll"};
715 #define PCLK_PMU_SRC 19
717 static struct rk_clk_composite_def pclk_pmu_src = {
720 .name = "pclk_pmu_src",
721 .parent_names = pmu_parents,
722 .parent_cnt = nitems(pmu_parents),
724 /* PMUCRU_CLKSEL_CON0 */
725 .muxdiv_offset = 0x80,
732 #define SCLK_I2C0_PMU 9
733 #define SCLK_I2C4_PMU 10
734 #define SCLK_I2C8_PMU 11
736 static struct rk_clk_composite_def i2c0 = {
739 .name = "clk_i2c0_pmu",
740 .parent_names = pmu_parents,
741 .parent_cnt = nitems(pmu_parents),
743 /* PMUCRU_CLKSEL_CON2 */
744 .muxdiv_offset = 0x88,
749 /* PMUCRU_CLKGATE_CON0 */
750 .gate_offset = 0x100,
753 .flags = RK_CLK_COMPOSITE_HAVE_GATE,
756 static struct rk_clk_composite_def i2c8 = {
759 .name = "clk_i2c8_pmu",
760 .parent_names = pmu_parents,
761 .parent_cnt = nitems(pmu_parents),
763 /* PMUCRU_CLKSEL_CON2 */
764 .muxdiv_offset = 0x88,
769 /* PMUCRU_CLKGATE_CON0 */
770 .gate_offset = 0x100,
773 .flags = RK_CLK_COMPOSITE_HAVE_GATE,
776 static struct rk_clk_composite_def i2c4 = {
779 .name = "clk_i2c4_pmu",
780 .parent_names = pmu_parents,
781 .parent_cnt = nitems(pmu_parents),
783 /* PMUCRU_CLKSEL_CON3 */
784 .muxdiv_offset = 0x8c,
789 /* PMUCRU_CLKGATE_CON0 */
790 .gate_offset = 0x100,
793 .flags = RK_CLK_COMPOSITE_HAVE_GATE,
796 static struct rk_clk rk3399_pmu_clks[] = {
798 .type = RK3399_CLK_PLL,
803 .type = RK_CLK_COMPOSITE,
804 .clk.composite = &pclk_pmu_src
807 .type = RK_CLK_COMPOSITE,
808 .clk.composite = &i2c0
811 .type = RK_CLK_COMPOSITE,
812 .clk.composite = &i2c4
815 .type = RK_CLK_COMPOSITE,
816 .clk.composite = &i2c8
821 rk3399_pmucru_probe(device_t dev)
824 if (!ofw_bus_status_okay(dev))
827 if (ofw_bus_is_compatible(dev, "rockchip,rk3399-pmucru")) {
828 device_set_desc(dev, "Rockchip RK3399 PMU Clock and Reset Unit");
829 return (BUS_PROBE_DEFAULT);
836 rk3399_pmucru_attach(device_t dev)
838 struct rk_cru_softc *sc;
840 sc = device_get_softc(dev);
843 sc->gates = rk3399_pmu_gates;
844 sc->ngates = nitems(rk3399_pmu_gates);
846 sc->clks = rk3399_pmu_clks;
847 sc->nclks = nitems(rk3399_pmu_clks);
849 return (rk_cru_attach(dev));
852 static device_method_t rk3399_pmucru_methods[] = {
853 /* Device interface */
854 DEVMETHOD(device_probe, rk3399_pmucru_probe),
855 DEVMETHOD(device_attach, rk3399_pmucru_attach),
860 static devclass_t rk3399_pmucru_devclass;
862 DEFINE_CLASS_1(rk3399_pmucru, rk3399_pmucru_driver, rk3399_pmucru_methods,
863 sizeof(struct rk_cru_softc), rk_cru_driver);
865 EARLY_DRIVER_MODULE(rk3399_pmucru, simplebus, rk3399_pmucru_driver,
866 rk3399_pmucru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);