sys/arm64/rockchip/rk3568_combphy.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  */
  28
  29 #include <sys/param.h>
  30 #include <sys/bus.h>
  31 #include <sys/kernel.h>
  32 #include <sys/module.h>
  33 #include <sys/mutex.h>
  34 #include <sys/rman.h>
  35 #include <machine/bus.h>
  36
  37 #include <dev/ofw/openfirm.h>
  38 #include <dev/ofw/ofw_bus.h>
  39 #include <dev/ofw/ofw_bus_subr.h>
  40
  41 #include <dev/fdt/simple_mfd.h>
  42
  43 #include <dev/clk/clk.h>
  44 #include <dev/hwreset/hwreset.h>
  45 #include <dev/regulator/regulator.h>
  46 #include <dev/syscon/syscon.h>
  47 #include <dev/phy/phy.h>
  48
  49 #include <contrib/device-tree/include/dt-bindings/phy/phy.h>
  50
  51 #include "syscon_if.h"
  52 #include "phydev_if.h"
  53 #include "phynode_if.h"
  54
  55
  56 static struct ofw_compat_data compat_data[] = {
  57         {"rockchip,rk3568-naneng-combphy",      1},
  58         {NULL, 0}
  59 };
  60
  61 struct rk3568_combphy_softc {
  62         device_t        dev;
  63         phandle_t       node;
  64         struct resource *mem;
  65         struct phynode  *phynode;
  66         struct syscon   *pipe_grf;
  67         struct syscon   *pipe_phy_grf;
  68         clk_t           ref_clk;
  69         clk_t           apb_clk;
  70         clk_t           pipe_clk;
  71         hwreset_t       phy_reset;
  72         int             mode;
  73 };
  74
  75 #define PHYREG6                         0x14
  76 #define  PHYREG6_PLL_DIV_MASK                   0xc0
  77 #define  PHYREG6_PLL_DIV_2                      (1 << 6)
  78 #define PHYREG7                         0x18
  79 #define  PHYREG7_TX_RTERM_50OHM                 (8 << 4)
  80 #define  PHYREG7_RX_RTERM_44OHM                 (15 << 0)
  81 #define PHYREG8                         0x1c
  82 #define  PHYREG8_SSC_EN                 0x10
  83 #define PHYREG11                        0x28
  84 #define  PHYREG11_SU_TRIM_0_7                   0xf0
  85 #define PHYREG12                        0x2c
  86 #define  PHYREG12_PLL_LPF_ADJ_VALUE             4
  87 #define PHYREG15                        0x38
  88 #define  PHYREG15_CTLE_EN                       0x01
  89 #define  PHYREG15_SSC_CNT_MASK                  0xc0
  90 #define  PHYREG15_SSC_CNT_VALUE                 (1 << 6)
  91 #define PHYREG16                        0x3c
  92 #define  PHYREG16_SSC_CNT_VALUE                 0x5f
  93 #define PHYREG18                        0x44
  94 #define  PHYREG18_PLL_LOOP                      0x32
  95 #define PHYREG32                        0x7c
  96 #define  PHYREG32_SSC_MASK                      0xf0
  97 #define  PHYREG32_SSC_UPWARD                    (0 << 4)
  98 #define  PHYREG32_SSC_DOWNWARD                  (1 << 4)
  99 #define  PHYREG32_SSC_OFFSET_500PPM             (1 << 6)
 100 #define PHYREG33                        0x80
 101 #define  PHYREG33_PLL_KVCO_MASK                 0x1c
 102 #define  PHYREG33_PLL_KVCO_VALUE                (2 << 2)
 103
 104 #define PIPE_MASK_ALL                   (0xffff << 16)
 105 #define PIPE_PHY_GRF_PIPE_CON0          0x00
 106 #define  PIPE_DATABUSWIDTH_MASK                 0x3
 107 #define  PIPE_DATABUSWIDTH_32BIT                0
 108 #define  PIPE_DATABUSWIDTH_16BIT                1
 109 #define  PIPE_PHYMODE_MASK                      (3 << 2)
 110 #define  PIPE_PHYMODE_PCIE                      (0 << 2)
 111 #define  PIPE_PHYMODE_USB3                      (1 << 2)
 112 #define  PIPE_PHYMODE_SATA                      (2 << 2)
 113 #define  PIPE_RATE_MASK                         (3 << 4)
 114 #define  PIPE_RATE_PCIE_2_5GBPS                 (0 << 4)
 115 #define  PIPE_RATE_PCIE_5GBPS                   (1 << 4)
 116 #define  PIPE_RATE_USB3_5GBPS                   (0 << 4)
 117 #define  PIPE_RATE_SATA_1GBPS5                  (0 << 4)
 118 #define  PIPE_RATE_SATA_3GBPS                   (1 << 4)
 119 #define  PIPE_RATE_SATA_6GBPS                   (2 << 4)
 120 #define  PIPE_MAC_PCLKREQ_N                     (1 << 8)
 121 #define  PIPE_L1SUB_ENTREQ                      (1 << 9)
 122 #define  PIPE_RXTERM                            (1 << 12)
 123 #define PIPE_PHY_GRF_PIPE_CON1          0x04
 124 #define  PHY_CLK_SEL_MASK                       (3 << 13)
 125 #define  PHY_CLK_SEL_24M                        (0 << 13)
 126 #define  PHY_CLK_SEL_25M                        (1 << 13)
 127 #define  PHY_CLK_SEL_100M                       (2 << 13)
 128 #define PIPE_PHY_GRF_PIPE_CON2          0x08
 129 #define  SEL_PIPE_TXCOMPLIANCE_I                (1 << 15)
 130 #define  SEL_PIPE_TXELECIDLE                    (1 << 12)
 131 #define  SEL_PIPE_RXTERM                        (1 << 8)
 132 #define  SEL_PIPE_BYPASS_CODEC                  (1 << 7)
 133 #define  SEL_PIPE_PIPE_EBUF                     (1 << 6)
 134 #define  SEL_PIPE_PIPE_PHYMODE                  (1 << 1)
 135 #define  SEL_PIPE_DATABUSWIDTH                  (1 << 0)
 136 #define PIPE_PHY_GRF_PIPE_CON3          0x0c
 137 #define  PIPE_SEL_MASK                          (3 << 13)
 138 #define  PIPE_SEL_PCIE                          (0 << 13)
 139 #define  PIPE_SEL_USB3                          (1 << 13)
 140 #define  PIPE_SEL_SATA                          (2 << 13)
 141 #define  PIPE_CLK_REF_SRC_I_MASK                (3 << 8)
 142 #define  PIPE_CLK_REF_SRC_I_PLL_CKREF_INNER     (2 << 8)
 143 #define  PIPE_RXELECIDLE                        (1 << 10)
 144 #define  PIPE_FROM_PCIE_IO                      (1 << 11)
 145
 146 #define PIPE_GRF_PIPE_CON0              0x00
 147 #define  SATA2_PHY_SPDMODE_1GBPS5               (0 << 12)
 148 #define  SATA2_PHY_SPDMODE_3GBPS                (1 << 12)
 149 #define  SATA2_PHY_SPDMODE_6GBPS                (2 << 12)
 150 #define  SATA1_PHY_SPDMODE_1GBPS5               (0 << 8)
 151 #define  SATA1_PHY_SPDMODE_3GBPS                (1 << 8)
 152 #define  SATA1_PHY_SPDMODE_6GBPS                (2 << 8)
 153 #define  SATA0_PHY_SPDMODE_1GBPS5               (0 << 4)
 154 #define  SATA0_PHY_SPDMODE_3GBPS                (1 << 4)
 155 #define  SATA0_PHY_SPDMODE_6GBPS                (2 << 4)
 156
 157 #define PIPE_GRF_SATA_CON0              0x10
 158 #define PIPE_GRF_SATA_CON1              0x14
 159 #define PIPE_GRF_SATA_CON2              0x18
 160 #define PIPE_GRF_XPCS_CON0              0x40
 161
 162
 163 /* PHY class and methods */
 164 static int
 165 rk3568_combphy_enable(struct phynode *phynode, bool enable)
 166 {
 167         device_t dev = phynode_get_device(phynode);
 168         struct rk3568_combphy_softc *sc = device_get_softc(dev);
 169         uint64_t rate;
 170
 171         if (enable == false)
 172                 return (0);
 173
 174         switch (sc->mode) {
 175         case PHY_TYPE_SATA:
 176                 device_printf(dev, "configuring for SATA");
 177
 178                 /* tx_rterm 50 ohm & rx_rterm 44 ohm */
 179                 bus_write_4(sc->mem, PHYREG7,
 180                     PHYREG7_TX_RTERM_50OHM | PHYREG7_RX_RTERM_44OHM);
 181
 182                 /* Adaptive CTLE */
 183                 bus_write_4(sc->mem, PHYREG15,
 184                     bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN);
 185
 186                 /* config grf_pipe for PCIe */
 187                 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3,
 188                     PIPE_MASK_ALL | PIPE_SEL_SATA | PIPE_RXELECIDLE | 0x7);
 189
 190                 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON2,
 191                     PIPE_MASK_ALL | SEL_PIPE_TXCOMPLIANCE_I |
 192                     SEL_PIPE_DATABUSWIDTH | 0xc3);
 193
 194                 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON0,
 195                     PIPE_MASK_ALL | PIPE_RXTERM | PIPE_DATABUSWIDTH_16BIT |
 196                     PIPE_RATE_SATA_3GBPS | PIPE_PHYMODE_SATA);
 197
 198                 SYSCON_WRITE_4(sc->pipe_grf, PIPE_GRF_PIPE_CON0,
 199                     PIPE_MASK_ALL | SATA0_PHY_SPDMODE_6GBPS |
 200                     SATA1_PHY_SPDMODE_6GBPS | SATA2_PHY_SPDMODE_6GBPS);
 201                 break;
 202
 203         case PHY_TYPE_PCIE:
 204                 device_printf(dev, "configuring for PCIe");
 205
 206                 /* Set SSC downward spread spectrum */
 207                 bus_write_4(sc->mem, PHYREG32,
 208                     (bus_read_4(sc->mem, PHYREG32) & PHYREG32_SSC_MASK) |
 209                     PHYREG32_SSC_DOWNWARD);
 210
 211                 /* config grf_pipe for PCIe */
 212                 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3,
 213                     PIPE_MASK_ALL | PIPE_SEL_PCIE |
 214                     PIPE_CLK_REF_SRC_I_PLL_CKREF_INNER);
 215                 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON2,
 216                     PIPE_MASK_ALL | SEL_PIPE_RXTERM | SEL_PIPE_DATABUSWIDTH);
 217                 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON0,
 218                     PIPE_MASK_ALL | PIPE_RXTERM | PIPE_DATABUSWIDTH_32BIT |
 219                     PIPE_RATE_PCIE_2_5GBPS | PIPE_PHYMODE_PCIE);
 220                 break;
 221
 222         case PHY_TYPE_USB3:
 223                 device_printf(dev, "configuring for USB3");
 224
 225                 /* Set SSC downward spread spectrum */
 226                 bus_write_4(sc->mem, PHYREG32,
 227                     (bus_read_4(sc->mem, PHYREG32) & PHYREG32_SSC_MASK) |
 228                     PHYREG32_SSC_DOWNWARD);
 229
 230                 /* Adaptive CTLE */
 231                 bus_write_4(sc->mem, PHYREG15,
 232                     bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN);
 233
 234                 /* Set PLL KVCO fine tuning signals */
 235                 bus_write_4(sc->mem, PHYREG33,
 236                     (bus_read_4(sc->mem, PHYREG33) & PHYREG33_PLL_KVCO_MASK) |
 237                     PHYREG33_PLL_KVCO_VALUE);
 238
 239                 /* Enable controlling random jitter. */
 240                 bus_write_4(sc->mem, PHYREG12, PHYREG12_PLL_LPF_ADJ_VALUE);
 241
 242                 /* Set PLL input clock divider 1/2 */
 243                 bus_write_4(sc->mem, PHYREG6,
 244                     (bus_read_4(sc->mem, PHYREG6) & PHYREG6_PLL_DIV_MASK) |
 245                     PHYREG6_PLL_DIV_2);
 246
 247                 /* Set PLL loop divider */
 248                 bus_write_4(sc->mem, PHYREG18, PHYREG18_PLL_LOOP);
 249
 250                 /* Set PLL LPF R1 to su_trim[0:7] */
 251                 bus_write_4(sc->mem, PHYREG11, PHYREG11_SU_TRIM_0_7);
 252
 253                 /* config grf_pipe for USB3 */
 254                 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3,
 255                     PIPE_MASK_ALL | PIPE_SEL_USB3);
 256                 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON2,
 257                     PIPE_MASK_ALL);
 258                 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON0,
 259                     PIPE_MASK_ALL | PIPE_DATABUSWIDTH_16BIT |
 260                     PIPE_PHYMODE_USB3 | PIPE_RATE_USB3_5GBPS);
 261                 break;
 262
 263         default:
 264                 printf("Unsupported mode=%d\n", sc->mode);
 265                 return (-1);
 266         }
 267
 268         clk_get_freq(sc->ref_clk, &rate);
 269         printf(" ref_clk=%lu\n", rate);
 270
 271         switch (rate) {
 272         case 24000000:
 273                 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON1,
 274                     (PHY_CLK_SEL_MASK << 16) | PHY_CLK_SEL_24M);
 275
 276                 if (sc->mode == PHY_TYPE_USB3 || sc->mode == PHY_TYPE_SATA) {
 277                         /* Adaptive CTLE */
 278                         bus_write_4(sc->mem, PHYREG15,
 279                             (bus_read_4(sc->mem, PHYREG15) &
 280                             PHYREG15_SSC_CNT_MASK) | PHYREG15_SSC_CNT_VALUE);
 281
 282                         /* SSC control period */
 283                         bus_write_4(sc->mem, PHYREG16, PHYREG16_SSC_CNT_VALUE);
 284                 }
 285                 break;
 286
 287         case 25000000:
 288                 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON1,
 289                     (PHY_CLK_SEL_MASK << 16) | PHY_CLK_SEL_25M);
 290                 break;
 291
 292         case 100000000:
 293                 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON1,
 294                     (PHY_CLK_SEL_MASK << 16) | PHY_CLK_SEL_100M);
 295
 296                 if (sc->mode == PHY_TYPE_PCIE) {
 297                         /* Set PLL KVCO fine tuning signals */
 298                         bus_write_4(sc->mem, PHYREG33,
 299                             (bus_read_4(sc->mem, PHYREG33) &
 300                             PHYREG33_PLL_KVCO_MASK) | PHYREG33_PLL_KVCO_VALUE);
 301
 302                         /* Enable controlling random jitter. */
 303                         bus_write_4(sc->mem, PHYREG12,
 304                             PHYREG12_PLL_LPF_ADJ_VALUE);
 305
 306                         /* Set PLL input clock divider 1/2 */
 307                         bus_write_4(sc->mem, PHYREG6,
 308                             (bus_read_4(sc->mem, PHYREG6) &
 309                             PHYREG6_PLL_DIV_MASK) | PHYREG6_PLL_DIV_2);
 310
 311                         /* Set PLL loop divider */
 312                         bus_write_4(sc->mem, PHYREG18, PHYREG18_PLL_LOOP);
 313
 314                         /* Set PLL LPF R1 to su_trim[0:7] */
 315                         bus_write_4(sc->mem, PHYREG11, PHYREG11_SU_TRIM_0_7);
 316                 }
 317                 if (sc->mode == PHY_TYPE_SATA) {
 318                         /* Set SSC downward spread spectrum */
 319                         bus_write_4(sc->mem, PHYREG32,
 320                             (bus_read_4(sc->mem, PHYREG32) & ~0x000000f0) |
 321                             PHYREG32_SSC_DOWNWARD | PHYREG32_SSC_OFFSET_500PPM);
 322                 }
 323                 break;
 324
 325         default:
 326                 device_printf(dev, "unknown ref rate=%lu\n", rate);
 327                 break;
 328         }
 329
 330         if (OF_hasprop(sc->node, "rockchip,ext-refclk")) {
 331                 device_printf(dev, "UNSUPPORTED rockchip,ext-refclk\n");
 332         }
 333         if (OF_hasprop(sc->node, "rockchip,enable-ssc")) {
 334                 device_printf(dev, "setting rockchip,enable-ssc\n");
 335                 bus_write_4(sc->mem, PHYREG8,
 336                     bus_read_4(sc->mem, PHYREG8) | PHYREG8_SSC_EN);
 337         }
 338
 339         if (hwreset_deassert(sc->phy_reset))
 340                 device_printf(dev, "phy_reset failed to clear\n");
 341
 342         return (0);
 343 }
 344
 345 static phynode_method_t rk3568_combphy_phynode_methods[] = {
 346         PHYNODEMETHOD(phynode_enable,   rk3568_combphy_enable),
 347
 348         PHYNODEMETHOD_END
 349 };
 350 DEFINE_CLASS_1(rk3568_combphy_phynode, rk3568_combphy_phynode_class,
 351     rk3568_combphy_phynode_methods, 0, phynode_class);
 352
 353
 354 /* Device class and methods */
 355 static int
 356 rk3568_combphy_probe(device_t dev)
 357 {
 358
 359         if (!ofw_bus_status_okay(dev))
 360                 return (ENXIO);
 361         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
 362                 return (ENXIO);
 363         device_set_desc(dev, "RockChip combo PHY");
 364         return (BUS_PROBE_DEFAULT);
 365 }
 366
 367 static int
 368 rk3568_combphy_attach(device_t dev)
 369 {
 370         struct rk3568_combphy_softc *sc = device_get_softc(dev);
 371         struct phynode_init_def phy_init;
 372         struct phynode *phynode;
 373         int rid = 0;
 374
 375         sc->dev = dev;
 376         sc->node = ofw_bus_get_node(dev);
 377
 378         /* Get memory resource */
 379         if (!(sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 380             &rid, RF_ACTIVE))) {
 381                 device_printf(dev, "Cannot allocate memory resources\n");
 382                 return (ENXIO);
 383         }
 384
 385         /* Get syncons handles */
 386         if (OF_hasprop(sc->node, "rockchip,pipe-grf") &&
 387             syscon_get_by_ofw_property(dev, sc->node, "rockchip,pipe-grf",
 388             &sc->pipe_grf))
 389                 return (ENXIO);
 390         if (OF_hasprop(sc->node, "rockchip,pipe-phy-grf") &&
 391             syscon_get_by_ofw_property(dev, sc->node, "rockchip,pipe-phy-grf",
 392             &sc->pipe_phy_grf))
 393                 return (ENXIO);
 394
 395         /* Get & enable clocks */
 396         if (clk_get_by_ofw_name(dev, 0, "ref", &sc->ref_clk)) {
 397                 device_printf(dev, "getting ref failed\n");
 398                 return (ENXIO);
 399         }
 400         if (clk_enable(sc->ref_clk))
 401                 device_printf(dev, "enable ref failed\n");
 402         if (clk_get_by_ofw_name(dev, 0, "apb", &sc->apb_clk)) {
 403                 device_printf(dev, "getting apb failed\n");
 404                 return (ENXIO);
 405         }
 406         if (clk_enable(sc->apb_clk))
 407                 device_printf(dev, "enable apb failed\n");
 408         if (clk_get_by_ofw_name(dev, 0, "pipe", &sc->pipe_clk)) {
 409                 device_printf(dev, "getting pipe failed\n");
 410                 return (ENXIO);
 411         }
 412         if (clk_enable(sc->pipe_clk))
 413                 device_printf(dev, "enable pipe failed\n");
 414
 415         /* get & assert reset */
 416         if (hwreset_get_by_ofw_idx(dev, sc->node, 0, &sc->phy_reset)) {
 417                 device_printf(dev, "Cannot get reset\n");
 418                 return (ENXIO);
 419         }
 420         hwreset_assert(sc->phy_reset);
 421
 422         bzero(&phy_init, sizeof(phy_init));
 423         phy_init.id = 0;
 424         phy_init.ofw_node = sc->node;
 425         if (!(phynode = phynode_create(dev, &rk3568_combphy_phynode_class,
 426             &phy_init))) {
 427                 device_printf(dev, "failed to create combphy PHY\n");
 428                 return (ENXIO);
 429         }
 430         if (!phynode_register(phynode)) {
 431                 device_printf(dev, "failed to register combphy PHY\n");
 432                 return (ENXIO);
 433         }
 434         sc->phynode = phynode;
 435         sc->mode = 0;
 436
 437         return (0);
 438 }
 439
 440 static int
 441 rk3568_combphy_map(device_t dev, phandle_t xref, int ncells, pcell_t *cells,
 442     intptr_t *id)
 443 {
 444         struct rk3568_combphy_softc *sc = device_get_softc(dev);
 445
 446         if (phydev_default_ofw_map(dev, xref, ncells, cells, id))
 447                 return (ERANGE);
 448
 449         /* Store the phy mode that is handed to us in id */
 450         sc->mode = *id;
 451
 452         /* Set our id to 0 so the std phy_get_*() works as usual */
 453         *id = 0;
 454
 455         return (0);
 456 }
 457
 458 static device_method_t rk3568_combphy_methods[] = {
 459         DEVMETHOD(device_probe,         rk3568_combphy_probe),
 460         DEVMETHOD(device_attach,        rk3568_combphy_attach),
 461         DEVMETHOD(phydev_map,           rk3568_combphy_map),
 462
 463         DEVMETHOD_END
 464 };
 465
 466 DEFINE_CLASS_1(rk3568_combphy, rk3568_combphy_driver, rk3568_combphy_methods,
 467     sizeof(struct simple_mfd_softc), simple_mfd_driver);
 468 EARLY_DRIVER_MODULE(rk3568_combphy, simplebus, rk3568_combphy_driver,
 469     0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE);