2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
41 #include <sys/mutex.h>
44 #include <machine/bus.h>
45 #include <machine/resource.h>
46 #include <machine/intr.h>
48 #include <dev/gpio/gpiobusvar.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51 #include <dev/extres/clk/clk.h>
55 #define RK_GPIO_SWPORTA_DR 0x00 /* Data register */
56 #define RK_GPIO_SWPORTA_DDR 0x04 /* Data direction register */
58 #define RK_GPIO_INTEN 0x30 /* Interrupt enable register */
59 #define RK_GPIO_INTMASK 0x34 /* Interrupt mask register */
60 #define RK_GPIO_INTTYPE_LEVEL 0x38 /* Interrupt level register */
61 #define RK_GPIO_INT_POLARITY 0x3C /* Interrupt polarity register */
62 #define RK_GPIO_INT_STATUS 0x40 /* Interrupt status register */
63 #define RK_GPIO_INT_RAWSTATUS 0x44 /* Raw Interrupt status register */
65 #define RK_GPIO_DEBOUNCE 0x48 /* Debounce enable register */
67 #define RK_GPIO_PORTA_EOI 0x4C /* Clear interrupt register */
68 #define RK_GPIO_EXT_PORTA 0x50 /* External port register */
70 #define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */
72 struct rk_gpio_softc {
76 struct resource *sc_res[2];
77 bus_space_tag_t sc_bst;
78 bus_space_handle_t sc_bsh;
82 static struct ofw_compat_data compat_data[] = {
83 {"rockchip,gpio-bank", 1},
87 static struct resource_spec rk_gpio_spec[] = {
88 { SYS_RES_MEMORY, 0, RF_ACTIVE },
89 { SYS_RES_IRQ, 0, RF_ACTIVE },
93 static int rk_gpio_detach(device_t dev);
95 #define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
96 #define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
97 #define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
99 #define RK_GPIO_WRITE(_sc, _off, _val) \
100 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
101 #define RK_GPIO_READ(_sc, _off) \
102 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
105 rk_gpio_probe(device_t dev)
108 if (!ofw_bus_status_okay(dev))
111 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
114 device_set_desc(dev, "RockChip GPIO Bank controller");
115 return (BUS_PROBE_DEFAULT);
119 rk_gpio_attach(device_t dev)
121 struct rk_gpio_softc *sc;
125 sc = device_get_softc(dev);
128 node = ofw_bus_get_node(sc->sc_dev);
129 if (!OF_hasprop(node, "gpio-controller"))
132 mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN);
134 if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) {
135 device_printf(dev, "could not allocate resources\n");
136 bus_release_resources(dev, rk_gpio_spec, sc->sc_res);
137 mtx_destroy(&sc->sc_mtx);
141 sc->sc_bst = rman_get_bustag(sc->sc_res[0]);
142 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]);
144 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) {
145 device_printf(dev, "Cannot get clock\n");
149 err = clk_enable(sc->clk);
151 device_printf(dev, "Could not enable clock %s\n",
152 clk_get_name(sc->clk));
157 sc->sc_busdev = gpiobus_attach_bus(dev);
158 if (sc->sc_busdev == NULL) {
167 rk_gpio_detach(device_t dev)
169 struct rk_gpio_softc *sc;
171 sc = device_get_softc(dev);
174 gpiobus_detach_bus(dev);
175 bus_release_resources(dev, rk_gpio_spec, sc->sc_res);
176 mtx_destroy(&sc->sc_mtx);
177 clk_disable(sc->clk);
183 rk_gpio_get_bus(device_t dev)
185 struct rk_gpio_softc *sc;
187 sc = device_get_softc(dev);
189 return (sc->sc_busdev);
193 rk_gpio_pin_max(device_t dev, int *maxpin)
196 /* Each bank have always 32 pins */
203 rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
205 struct rk_gpio_softc *sc;
207 sc = device_get_softc(dev);
213 snprintf(name, GPIOMAXNAME, "gpio%d", pin);
220 rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
222 struct rk_gpio_softc *sc;
225 sc = device_get_softc(dev);
227 /* XXX Combine this with parent (pinctrl) */
229 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR);
232 if (reg & (1 << pin))
233 *flags = GPIO_PIN_OUTPUT;
235 *flags = GPIO_PIN_INPUT;
241 rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
244 /* Caps are managed by the pinctrl device */
245 /* XXX Pass this to parent (pinctrl) */
251 rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
253 struct rk_gpio_softc *sc;
256 sc = device_get_softc(dev);
258 /* XXX Combine this with parent (pinctrl) */
261 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR);
262 if (flags & GPIO_PIN_INPUT)
264 else if (flags & GPIO_PIN_OUTPUT)
267 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg);
274 rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
276 struct rk_gpio_softc *sc;
279 sc = device_get_softc(dev);
282 reg = RK_GPIO_READ(sc, RK_GPIO_EXT_PORTA);
285 *val = reg & (1 << pin) ? 1 : 0;
291 rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
293 struct rk_gpio_softc *sc;
296 sc = device_get_softc(dev);
299 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR);
304 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg);
311 rk_gpio_pin_toggle(device_t dev, uint32_t pin)
313 struct rk_gpio_softc *sc;
316 sc = device_get_softc(dev);
319 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR);
320 if (reg & (1 << pin))
324 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg);
331 rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
332 uint32_t change_pins, uint32_t *orig_pins)
334 struct rk_gpio_softc *sc;
337 sc = device_get_softc(dev);
340 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR);
344 if ((clear_pins | change_pins) != 0) {
345 reg = (reg & ~clear_pins) ^ change_pins;
346 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg);
354 rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
357 struct rk_gpio_softc *sc;
358 uint32_t reg, set, mask, flags;
361 sc = device_get_softc(dev);
363 if (first_pin != 0 || num_pins > 32)
368 for (i = 0; i < num_pins; i++) {
369 mask = (mask << 1) | 1;
370 flags = pin_flags[i];
371 if (flags & GPIO_PIN_INPUT) {
373 } else if (flags & GPIO_PIN_OUTPUT) {
379 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR);
382 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg);
389 rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
390 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
393 /* The gpios are mapped as <pin flags> */
400 rk_gpio_get_node(device_t bus, device_t dev)
403 /* We only have one child, the GPIO bus, which needs our own node. */
404 return (ofw_bus_get_node(bus));
407 static device_method_t rk_gpio_methods[] = {
408 /* Device interface */
409 DEVMETHOD(device_probe, rk_gpio_probe),
410 DEVMETHOD(device_attach, rk_gpio_attach),
411 DEVMETHOD(device_detach, rk_gpio_detach),
414 DEVMETHOD(gpio_get_bus, rk_gpio_get_bus),
415 DEVMETHOD(gpio_pin_max, rk_gpio_pin_max),
416 DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname),
417 DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags),
418 DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps),
419 DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags),
420 DEVMETHOD(gpio_pin_get, rk_gpio_pin_get),
421 DEVMETHOD(gpio_pin_set, rk_gpio_pin_set),
422 DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle),
423 DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32),
424 DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32),
425 DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios),
427 /* ofw_bus interface */
428 DEVMETHOD(ofw_bus_get_node, rk_gpio_get_node),
433 static driver_t rk_gpio_driver = {
436 sizeof(struct rk_gpio_softc),
439 static devclass_t rk_gpio_devclass;
442 * GPIO driver is always a child of rk_pinctrl driver and should be probed
443 * and attached within rk_pinctrl_attach function. Due to this, bus pass order
444 * must be same as bus pass order of rk_pinctrl driver.
446 EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver,
447 rk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);