2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
5 * Copyright (c) 2021 Soren Schmidt <sos@deepcore.dk>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
42 #include <sys/mutex.h>
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <machine/intr.h>
49 #include <dev/gpio/gpiobusvar.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dev/extres/clk/clk.h>
57 #include "fdt_pinctrl_if.h"
60 RK_GPIO_SWPORTA_DR = 1, /* Data register */
61 RK_GPIO_SWPORTA_DDR, /* Data direction register */
62 RK_GPIO_INTEN, /* Interrupt enable register */
63 RK_GPIO_INTMASK, /* Interrupt mask register */
64 RK_GPIO_INTTYPE_LEVEL, /* Interrupt level register */
65 RK_GPIO_INTTYPE_BOTH, /* Both rise and falling edge */
66 RK_GPIO_INT_POLARITY, /* Interrupt polarity register */
67 RK_GPIO_INT_STATUS, /* Interrupt status register */
68 RK_GPIO_INT_RAWSTATUS, /* Raw Interrupt status register */
69 RK_GPIO_DEBOUNCE, /* Debounce enable register */
70 RK_GPIO_PORTA_EOI, /* Clear interrupt register */
71 RK_GPIO_EXT_PORTA, /* External port register */
75 #define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */
77 #define RK_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
78 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_EDGE_BOTH | \
79 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | \
80 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_LEVEL_LOW)
82 #define GPIO_FLAGS_PINCTRL GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN
83 #define RK_GPIO_MAX_PINS 32
90 struct rk_pin_irqsrc {
91 struct intr_irqsrc isrc;
96 struct rk_gpio_softc {
100 struct resource *sc_res[2];
101 bus_space_tag_t sc_bst;
102 bus_space_handle_t sc_bsh;
106 uint32_t swporta_ddr;
108 struct pin_cached pin_cached[RK_GPIO_MAX_PINS];
109 uint8_t regs[RK_GPIO_REGNUM];
111 struct rk_pin_irqsrc isrcs[RK_GPIO_MAX_PINS];
114 static struct ofw_compat_data compat_data[] = {
115 {"rockchip,gpio-bank", 1},
119 static struct resource_spec rk_gpio_spec[] = {
120 { SYS_RES_MEMORY, 0, RF_ACTIVE },
121 { SYS_RES_IRQ, 0, RF_ACTIVE },
125 #define RK_GPIO_VERSION 0x78
126 #define RK_GPIO_TYPE_V1 0x00000000
127 #define RK_GPIO_TYPE_V2 0x01000c2b
128 #define RK_GPIO_ISRC(sc, irq) (&(sc->isrcs[irq].isrc))
130 static int rk_gpio_detach(device_t dev);
132 #define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
133 #define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
134 #define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
136 #define RK_GPIO_WRITE(_sc, _off, _val) \
137 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
138 #define RK_GPIO_READ(_sc, _off) \
139 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
142 rk_gpio_read_bit(struct rk_gpio_softc *sc, int reg, int bit)
144 int offset = sc->regs[reg];
147 if (sc->version == RK_GPIO_TYPE_V1) {
148 value = RK_GPIO_READ(sc, offset);
151 value = RK_GPIO_READ(sc, bit > 15 ? offset + 4 : offset);
152 value >>= (bit % 16);
158 rk_gpio_write_bit(struct rk_gpio_softc *sc, int reg, int bit, int data)
160 int offset = sc->regs[reg];
163 if (sc->version == RK_GPIO_TYPE_V1) {
164 value = RK_GPIO_READ(sc, offset);
168 value &= ~(1 << bit);
169 RK_GPIO_WRITE(sc, offset, value);
172 value = (1 << (bit % 16));
175 value |= (1 << ((bit % 16) + 16));
176 RK_GPIO_WRITE(sc, bit > 15 ? offset + 4 : offset, value);
181 rk_gpio_read_4(struct rk_gpio_softc *sc, int reg)
183 int offset = sc->regs[reg];
186 if (sc->version == RK_GPIO_TYPE_V1)
187 value = RK_GPIO_READ(sc, offset);
189 value = (RK_GPIO_READ(sc, offset) & 0xffff) |
190 (RK_GPIO_READ(sc, offset + 4) << 16);
195 rk_gpio_write_4(struct rk_gpio_softc *sc, int reg, uint32_t value)
197 int offset = sc->regs[reg];
199 if (sc->version == RK_GPIO_TYPE_V1)
200 RK_GPIO_WRITE(sc, offset, value);
202 RK_GPIO_WRITE(sc, offset, (value & 0xffff) | 0xffff0000);
203 RK_GPIO_WRITE(sc, offset + 4, (value >> 16) | 0xffff0000);
208 rk_gpio_intr(void *arg)
210 struct rk_gpio_softc *sc = (struct rk_gpio_softc *)arg;;
211 struct trapframe *tf = curthread->td_intr_frame;
215 status = rk_gpio_read_4(sc, RK_GPIO_INT_STATUS);
216 rk_gpio_write_4(sc, RK_GPIO_PORTA_EOI, status);
220 int pin = ffs(status) - 1;
222 status &= ~(1 << pin);
223 if (intr_isrc_dispatch(RK_GPIO_ISRC(sc, pin), tf)) {
224 device_printf(sc->sc_dev, "Interrupt pin=%d unhandled\n",
229 if ((sc->version == RK_GPIO_TYPE_V1) &&
230 (sc->isrcs[pin].mode & GPIO_INTR_EDGE_BOTH)) {
232 if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin))
233 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY,
236 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY,
241 return (FILTER_HANDLED);
245 rk_gpio_probe(device_t dev)
248 if (!ofw_bus_status_okay(dev))
251 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
254 device_set_desc(dev, "RockChip GPIO Bank controller");
255 return (BUS_PROBE_DEFAULT);
259 rk_gpio_attach(device_t dev)
261 struct rk_gpio_softc *sc;
262 phandle_t parent_node, node;
265 sc = device_get_softc(dev);
267 sc->pinctrl = device_get_parent(dev);
268 parent_node = ofw_bus_get_node(sc->pinctrl);
270 node = ofw_bus_get_node(sc->sc_dev);
271 if (!OF_hasprop(node, "gpio-controller"))
274 mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN);
276 if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) {
277 device_printf(dev, "could not allocate resources\n");
278 bus_release_resources(dev, rk_gpio_spec, sc->sc_res);
279 mtx_destroy(&sc->sc_mtx);
283 sc->sc_bst = rman_get_bustag(sc->sc_res[0]);
284 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]);
286 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) {
287 device_printf(dev, "Cannot get clock\n");
291 err = clk_enable(sc->clk);
293 device_printf(dev, "Could not enable clock %s\n",
294 clk_get_name(sc->clk));
299 if ((err = bus_setup_intr(dev, sc->sc_res[1],
300 INTR_TYPE_MISC | INTR_MPSAFE, rk_gpio_intr, NULL,
301 sc, &sc->ihandle))) {
302 device_printf(dev, "Can not setup IRQ\n");
308 * RK3568 has GPIO_VER_ID register, however both
309 * RK3328 and RK3399 doesn't have. So choose the
310 * version based on parent's compat string.
312 if (ofw_bus_node_is_compatible(parent_node, "rockchip,rk3568-pinctrl"))
313 sc->version = RK_GPIO_TYPE_V2;
315 sc->version = RK_GPIO_TYPE_V1;
317 switch (sc->version) {
318 case RK_GPIO_TYPE_V1:
319 sc->regs[RK_GPIO_SWPORTA_DR] = 0x00;
320 sc->regs[RK_GPIO_SWPORTA_DDR] = 0x04;
321 sc->regs[RK_GPIO_INTEN] = 0x30;
322 sc->regs[RK_GPIO_INTMASK] = 0x34;
323 sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x38;
324 sc->regs[RK_GPIO_INT_POLARITY] = 0x3c;
325 sc->regs[RK_GPIO_INT_STATUS] = 0x40;
326 sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x44;
327 sc->regs[RK_GPIO_DEBOUNCE] = 0x48;
328 sc->regs[RK_GPIO_PORTA_EOI] = 0x4c;
329 sc->regs[RK_GPIO_EXT_PORTA] = 0x50;
331 case RK_GPIO_TYPE_V2:
332 sc->regs[RK_GPIO_SWPORTA_DR] = 0x00;
333 sc->regs[RK_GPIO_SWPORTA_DDR] = 0x08;
334 sc->regs[RK_GPIO_INTEN] = 0x10;
335 sc->regs[RK_GPIO_INTMASK] = 0x18;
336 sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x20;
337 sc->regs[RK_GPIO_INTTYPE_BOTH] = 0x30;
338 sc->regs[RK_GPIO_INT_POLARITY] = 0x28;
339 sc->regs[RK_GPIO_INT_STATUS] = 0x50;
340 sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x58;
341 sc->regs[RK_GPIO_DEBOUNCE] = 0x38;
342 sc->regs[RK_GPIO_PORTA_EOI] = 0x60;
343 sc->regs[RK_GPIO_EXT_PORTA] = 0x70;
346 device_printf(dev, "Unknown gpio version %08x\n", sc->version);
351 for (i = 0; i < RK_GPIO_MAX_PINS; i++) {
352 sc->isrcs[i].irq = i;
353 sc->isrcs[i].mode = GPIO_INTR_CONFORM;
354 if ((err = intr_isrc_register(RK_GPIO_ISRC(sc, i),
355 dev, 0, "%s", device_get_nameunit(dev)))) {
356 device_printf(dev, "Can not register isrc %d\n", err);
362 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) {
363 device_printf(dev, "Can not register pic\n");
368 sc->sc_busdev = gpiobus_attach_bus(dev);
369 if (sc->sc_busdev == NULL) {
374 /* Set the cached value to unknown */
375 for (i = 0; i < RK_GPIO_MAX_PINS; i++)
376 sc->pin_cached[i].is_gpio = 2;
379 sc->swporta = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR);
380 sc->swporta_ddr = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR);
387 rk_gpio_detach(device_t dev)
389 struct rk_gpio_softc *sc;
391 sc = device_get_softc(dev);
394 gpiobus_detach_bus(dev);
395 bus_release_resources(dev, rk_gpio_spec, sc->sc_res);
396 mtx_destroy(&sc->sc_mtx);
397 clk_disable(sc->clk);
403 rk_gpio_get_bus(device_t dev)
405 struct rk_gpio_softc *sc;
407 sc = device_get_softc(dev);
409 return (sc->sc_busdev);
413 rk_gpio_pin_max(device_t dev, int *maxpin)
416 /* Each bank have always 32 pins */
423 rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
425 struct rk_gpio_softc *sc;
428 sc = device_get_softc(dev);
434 pin = pin - (bank * 8);
436 snprintf(name, GPIOMAXNAME, "P%c%d", bank + 'A', pin);
443 rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
445 struct rk_gpio_softc *sc;
448 sc = device_get_softc(dev);
450 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) {
451 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio);
454 if (sc->pin_cached[pin].is_gpio == 0)
458 rv = FDT_PINCTRL_GET_FLAGS(sc->pinctrl, dev, pin, flags);
461 sc->pin_cached[pin].flags = *flags;
463 if (sc->swporta_ddr & (1 << pin))
464 *flags |= GPIO_PIN_OUTPUT;
466 *flags |= GPIO_PIN_INPUT;
472 rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
475 if (pin >= RK_GPIO_MAX_PINS)
478 *caps = RK_GPIO_DEFAULT_CAPS;
483 rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
485 struct rk_gpio_softc *sc;
488 sc = device_get_softc(dev);
490 if (pin >= RK_GPIO_MAX_PINS)
493 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) {
494 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio);
497 if (sc->pin_cached[pin].is_gpio == 0)
501 if (__predict_false((flags & GPIO_PIN_INPUT) && ((flags & GPIO_FLAGS_PINCTRL) != sc->pin_cached[pin].flags))) {
502 rv = FDT_PINCTRL_SET_FLAGS(sc->pinctrl, dev, pin, flags);
503 sc->pin_cached[pin].flags = flags & GPIO_FLAGS_PINCTRL;
509 if (flags & GPIO_PIN_INPUT)
510 sc->swporta_ddr &= ~(1 << pin);
511 else if (flags & GPIO_PIN_OUTPUT)
512 sc->swporta_ddr |= (1 << pin);
514 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, sc->swporta_ddr);
521 rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
523 struct rk_gpio_softc *sc;
525 sc = device_get_softc(dev);
527 if (pin >= RK_GPIO_MAX_PINS)
531 *val = rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin);
538 rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
540 struct rk_gpio_softc *sc;
542 sc = device_get_softc(dev);
544 if (pin >= RK_GPIO_MAX_PINS)
549 sc->swporta |= (1 << pin);
551 sc->swporta &= ~(1 << pin);
552 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta);
559 rk_gpio_pin_toggle(device_t dev, uint32_t pin)
561 struct rk_gpio_softc *sc;
563 sc = device_get_softc(dev);
565 if (pin >= RK_GPIO_MAX_PINS)
569 if (sc->swporta & (1 << pin))
570 sc->swporta &= ~(1 << pin);
572 sc->swporta |= (1 << pin);
573 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta);
580 rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
581 uint32_t change_pins, uint32_t *orig_pins)
583 struct rk_gpio_softc *sc;
586 sc = device_get_softc(dev);
589 reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR);
594 if ((clear_pins | change_pins) != 0) {
595 reg = (reg & ~clear_pins) ^ change_pins;
596 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, reg);
604 rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
607 struct rk_gpio_softc *sc;
608 uint32_t reg, set, mask, flags;
611 sc = device_get_softc(dev);
613 if (first_pin != 0 || num_pins > 32)
618 for (i = 0; i < num_pins; i++) {
619 mask = (mask << 1) | 1;
620 flags = pin_flags[i];
621 if (flags & GPIO_PIN_INPUT) {
623 } else if (flags & GPIO_PIN_OUTPUT) {
629 reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR);
632 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, reg);
633 sc->swporta_ddr = reg;
640 rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
641 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
644 /* The gpios are mapped as <pin flags> */
651 rk_gpio_get_node(device_t bus, device_t dev)
654 /* We only have one child, the GPIO bus, which needs our own node. */
655 return (ofw_bus_get_node(bus));
659 rk_pic_map_intr(device_t dev, struct intr_map_data *data,
660 struct intr_irqsrc **isrcp)
662 struct rk_gpio_softc *sc = device_get_softc(dev);
663 struct intr_map_data_gpio *gdata;
666 if (data->type != INTR_MAP_DATA_GPIO) {
667 device_printf(dev, "Wrong type\n");
670 gdata = (struct intr_map_data_gpio *)data;
671 irq = gdata->gpio_pin_num;
672 if (irq >= RK_GPIO_MAX_PINS) {
673 device_printf(dev, "Invalid interrupt %u\n", irq);
676 *isrcp = RK_GPIO_ISRC(sc, irq);
681 rk_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
682 struct resource *res, struct intr_map_data *data)
684 struct rk_gpio_softc *sc = device_get_softc(dev);
685 struct rk_pin_irqsrc *rkisrc = (struct rk_pin_irqsrc *)isrc;
686 struct intr_map_data_gpio *gdata;
691 device_printf(dev, "No map data\n");
694 gdata = (struct intr_map_data_gpio *)data;
695 mode = gdata->gpio_intr_mode;
696 pin = gdata->gpio_pin_num;
698 if (rkisrc->irq != gdata->gpio_pin_num) {
699 device_printf(dev, "Interrupts don't match\n");
703 if (isrc->isrc_handlers != 0) {
704 device_printf(dev, "Handler already attached\n");
705 return (rkisrc->mode == mode ? 0 : EINVAL);
711 switch (mode & GPIO_INTR_MASK) {
712 case GPIO_INTR_EDGE_RISING:
713 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0);
714 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1);
715 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1);
717 case GPIO_INTR_EDGE_FALLING:
718 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0);
719 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1);
720 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0);
722 case GPIO_INTR_EDGE_BOTH:
723 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0);
724 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1);
725 if (sc->version == RK_GPIO_TYPE_V1) {
726 if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin))
727 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY,
730 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY,
733 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_BOTH, pin, 1);
735 case GPIO_INTR_LEVEL_HIGH:
736 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0);
737 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0);
738 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1);
740 case GPIO_INTR_LEVEL_LOW:
741 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0);
742 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0);
743 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0);
746 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 1);
747 rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 0);
751 rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, pin, 1);
752 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 0);
753 rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 1);
760 rk_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
761 struct resource *res, struct intr_map_data *data)
763 struct rk_gpio_softc *sc = device_get_softc(dev);
764 struct rk_pin_irqsrc *irqsrc;
766 irqsrc = (struct rk_pin_irqsrc *)isrc;
768 if (isrc->isrc_handlers == 0) {
769 irqsrc->mode = GPIO_INTR_CONFORM;
771 rk_gpio_write_bit(sc, RK_GPIO_INTEN, irqsrc->irq, 0);
772 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, irqsrc->irq, 0);
773 rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, irqsrc->irq, 0);
779 static device_method_t rk_gpio_methods[] = {
780 /* Device interface */
781 DEVMETHOD(device_probe, rk_gpio_probe),
782 DEVMETHOD(device_attach, rk_gpio_attach),
783 DEVMETHOD(device_detach, rk_gpio_detach),
786 DEVMETHOD(gpio_get_bus, rk_gpio_get_bus),
787 DEVMETHOD(gpio_pin_max, rk_gpio_pin_max),
788 DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname),
789 DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags),
790 DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps),
791 DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags),
792 DEVMETHOD(gpio_pin_get, rk_gpio_pin_get),
793 DEVMETHOD(gpio_pin_set, rk_gpio_pin_set),
794 DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle),
795 DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32),
796 DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32),
797 DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios),
799 /* Interrupt controller interface */
800 DEVMETHOD(pic_map_intr, rk_pic_map_intr),
801 DEVMETHOD(pic_setup_intr, rk_pic_setup_intr),
802 DEVMETHOD(pic_teardown_intr, rk_pic_teardown_intr),
804 /* ofw_bus interface */
805 DEVMETHOD(ofw_bus_get_node, rk_gpio_get_node),
810 static driver_t rk_gpio_driver = {
813 sizeof(struct rk_gpio_softc),
817 * GPIO driver is always a child of rk_pinctrl driver and should be probed
818 * and attached within rk_pinctrl_attach function. Due to this, bus pass order
819 * must be same as bus pass order of rk_pinctrl driver.
821 EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver, 0, 0,
822 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);