2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
41 #include <sys/mutex.h>
44 #include <machine/bus.h>
45 #include <machine/resource.h>
46 #include <machine/intr.h>
48 #include <dev/gpio/gpiobusvar.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51 #include <dev/extres/clk/clk.h>
57 #define RK_GPIO_SWPORTA_DR 0x00 /* Data register */
58 #define RK_GPIO_SWPORTA_DDR 0x04 /* Data direction register */
60 #define RK_GPIO_INTEN 0x30 /* Interrupt enable register */
61 #define RK_GPIO_INTMASK 0x34 /* Interrupt mask register */
62 #define RK_GPIO_INTTYPE_LEVEL 0x38 /* Interrupt level register */
63 #define RK_GPIO_INT_POLARITY 0x3C /* Interrupt polarity register */
64 #define RK_GPIO_INT_STATUS 0x40 /* Interrupt status register */
65 #define RK_GPIO_INT_RAWSTATUS 0x44 /* Raw Interrupt status register */
67 #define RK_GPIO_DEBOUNCE 0x48 /* Debounce enable register */
69 #define RK_GPIO_PORTA_EOI 0x4C /* Clear interrupt register */
70 #define RK_GPIO_EXT_PORTA 0x50 /* External port register */
72 #define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */
74 struct rk_gpio_softc {
78 struct resource *sc_res[2];
79 bus_space_tag_t sc_bst;
80 bus_space_handle_t sc_bsh;
84 static struct ofw_compat_data compat_data[] = {
85 {"rockchip,gpio-bank", 1},
89 static struct resource_spec rk_gpio_spec[] = {
90 { SYS_RES_MEMORY, 0, RF_ACTIVE },
91 { SYS_RES_IRQ, 0, RF_ACTIVE },
95 static int rk_gpio_detach(device_t dev);
97 #define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
98 #define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
99 #define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
101 #define RK_GPIO_WRITE(_sc, _off, _val) \
102 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
103 #define RK_GPIO_READ(_sc, _off) \
104 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
107 rk_gpio_probe(device_t dev)
110 if (!ofw_bus_status_okay(dev))
113 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
116 device_set_desc(dev, "RockChip GPIO Bank controller");
117 return (BUS_PROBE_DEFAULT);
121 rk_gpio_attach(device_t dev)
123 struct rk_gpio_softc *sc;
127 sc = device_get_softc(dev);
130 node = ofw_bus_get_node(sc->sc_dev);
131 if (!OF_hasprop(node, "gpio-controller"))
134 mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN);
136 if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) {
137 device_printf(dev, "could not allocate resources\n");
138 bus_release_resources(dev, rk_gpio_spec, sc->sc_res);
139 mtx_destroy(&sc->sc_mtx);
143 sc->sc_bst = rman_get_bustag(sc->sc_res[0]);
144 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]);
146 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) {
147 device_printf(dev, "Cannot get clock\n");
151 err = clk_enable(sc->clk);
153 device_printf(dev, "Could not enable clock %s\n",
154 clk_get_name(sc->clk));
159 sc->sc_busdev = gpiobus_attach_bus(dev);
160 if (sc->sc_busdev == NULL) {
169 rk_gpio_detach(device_t dev)
171 struct rk_gpio_softc *sc;
173 sc = device_get_softc(dev);
176 gpiobus_detach_bus(dev);
177 bus_release_resources(dev, rk_gpio_spec, sc->sc_res);
178 mtx_destroy(&sc->sc_mtx);
179 clk_disable(sc->clk);
185 rk_gpio_get_bus(device_t dev)
187 struct rk_gpio_softc *sc;
189 sc = device_get_softc(dev);
191 return (sc->sc_busdev);
195 rk_gpio_pin_max(device_t dev, int *maxpin)
198 /* Each bank have always 32 pins */
204 rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
206 struct rk_gpio_softc *sc;
208 sc = device_get_softc(dev);
214 snprintf(name, GPIOMAXNAME, "gpio%d", pin);
221 rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
223 struct rk_gpio_softc *sc;
226 sc = device_get_softc(dev);
229 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR);
232 if (reg & (1 << pin))
233 *flags = GPIO_PIN_OUTPUT;
235 *flags = GPIO_PIN_INPUT;
241 rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
244 /* Caps are managed by the pinctrl device */
250 rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
252 struct rk_gpio_softc *sc;
255 sc = device_get_softc(dev);
259 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR);
260 if (flags & GPIO_PIN_INPUT)
262 else if (flags & GPIO_PIN_OUTPUT)
265 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg);
272 rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
274 struct rk_gpio_softc *sc;
277 sc = device_get_softc(dev);
280 reg = RK_GPIO_READ(sc, RK_GPIO_EXT_PORTA);
283 *val = reg & (1 << pin) ? 1 : 0;
289 rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
291 struct rk_gpio_softc *sc;
294 sc = device_get_softc(dev);
297 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR);
302 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg);
309 rk_gpio_pin_toggle(device_t dev, uint32_t pin)
311 struct rk_gpio_softc *sc;
314 sc = device_get_softc(dev);
317 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR);
318 if (reg & (1 << pin))
322 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg);
329 rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
330 uint32_t change_pins, uint32_t *orig_pins)
332 struct rk_gpio_softc *sc;
335 sc = device_get_softc(dev);
338 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR);
342 if ((clear_pins | change_pins) != 0) {
343 reg = (reg & ~clear_pins) ^ change_pins;
344 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg);
352 rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
355 struct rk_gpio_softc *sc;
356 uint32_t reg, set, mask, flags;
359 sc = device_get_softc(dev);
361 if (first_pin != 0 || num_pins > 32)
366 for (i = 0; i < num_pins; i++) {
367 mask = (mask << 1) | 1;
368 flags = pin_flags[i];
369 if (flags & GPIO_PIN_INPUT) {
371 } else if (flags & GPIO_PIN_OUTPUT) {
377 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR);
380 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg);
387 rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
388 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
391 /* The gpios are mapped as <gpio-phandle pin flags> */
397 static device_method_t rk_gpio_methods[] = {
398 /* Device interface */
399 DEVMETHOD(device_probe, rk_gpio_probe),
400 DEVMETHOD(device_attach, rk_gpio_attach),
401 DEVMETHOD(device_detach, rk_gpio_detach),
404 DEVMETHOD(gpio_get_bus, rk_gpio_get_bus),
405 DEVMETHOD(gpio_pin_max, rk_gpio_pin_max),
406 DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname),
407 DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags),
408 DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps),
409 DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags),
410 DEVMETHOD(gpio_pin_get, rk_gpio_pin_get),
411 DEVMETHOD(gpio_pin_set, rk_gpio_pin_set),
412 DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle),
413 DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32),
414 DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32),
415 DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios),
420 static driver_t rk_gpio_driver = {
423 sizeof(struct rk_gpio_softc),
426 static devclass_t rk_gpio_devclass;
428 EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver,
429 rk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);