2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/mutex.h>
37 #include <machine/bus.h>
39 #include <dev/ofw/ofw_bus.h>
40 #include <dev/ofw/ofw_bus_subr.h>
42 #include <dev/iicbus/iiconf.h>
43 #include <dev/iicbus/iicbus.h>
45 #include <dev/extres/clk/clk.h>
47 #include "iicbus_if.h"
52 #define RK_I2C_CON 0x00
53 #define RK_I2C_CON_EN (1 << 0)
54 #define RK_I2C_CON_MODE_SHIFT 1
55 #define RK_I2C_CON_MODE_TX 0
56 #define RK_I2C_CON_MODE_RRX 1
57 #define RK_I2C_CON_MODE_RX 2
58 #define RK_I2C_CON_MODE_RTX 3
59 #define RK_I2C_CON_MODE_MASK 0x6
60 #define RK_I2C_CON_START (1 << 3)
61 #define RK_I2C_CON_STOP (1 << 4)
62 #define RK_I2C_CON_LASTACK (1 << 5)
63 #define RK_I2C_CON_NAKSTOP (1 << 6)
65 #define RK_I2C_CLKDIV 0x04
66 #define RK_I2C_CLKDIVL_MASK 0xFFFF
67 #define RK_I2C_CLKDIVL_SHIFT 0
68 #define RK_I2C_CLKDIVH_MASK 0xFFFF0000
69 #define RK_I2C_CLKDIVH_SHIFT 16
70 #define RK_I2C_CLKDIV_MUL 8
72 #define RK_I2C_MRXADDR 0x08
73 #define RK_I2C_MRXADDR_SADDR_MASK 0xFFFFFF
74 #define RK_I2C_MRXADDR_VALID(x) (1 << (24 + x))
76 #define RK_I2C_MRXRADDR 0x0C
77 #define RK_I2C_MRXRADDR_SRADDR_MASK 0xFFFFFF
78 #define RK_I2C_MRXRADDR_VALID(x) (1 << (24 + x))
80 #define RK_I2C_MTXCNT 0x10
81 #define RK_I2C_MTXCNT_MASK 0x3F
83 #define RK_I2C_MRXCNT 0x14
84 #define RK_I2C_MRXCNT_MASK 0x3F
86 #define RK_I2C_IEN 0x18
87 #define RK_I2C_IEN_BTFIEN (1 << 0)
88 #define RK_I2C_IEN_BRFIEN (1 << 1)
89 #define RK_I2C_IEN_MBTFIEN (1 << 2)
90 #define RK_I2C_IEN_MBRFIEN (1 << 3)
91 #define RK_I2C_IEN_STARTIEN (1 << 4)
92 #define RK_I2C_IEN_STOPIEN (1 << 5)
93 #define RK_I2C_IEN_NAKRCVIEN (1 << 6)
94 #define RK_I2C_IEN_ALL (RK_I2C_IEN_BTFIEN | \
95 RK_I2C_IEN_BRFIEN | RK_I2C_IEN_MBTFIEN | RK_I2C_IEN_MBRFIEN | \
96 RK_I2C_IEN_STARTIEN | RK_I2C_IEN_STOPIEN | RK_I2C_IEN_NAKRCVIEN)
98 #define RK_I2C_IPD 0x1C
99 #define RK_I2C_IPD_BTFIPD (1 << 0)
100 #define RK_I2C_IPD_BRFIPD (1 << 1)
101 #define RK_I2C_IPD_MBTFIPD (1 << 2)
102 #define RK_I2C_IPD_MBRFIPD (1 << 3)
103 #define RK_I2C_IPD_STARTIPD (1 << 4)
104 #define RK_I2C_IPD_STOPIPD (1 << 5)
105 #define RK_I2C_IPD_NAKRCVIPD (1 << 6)
106 #define RK_I2C_IPD_ALL (RK_I2C_IPD_BTFIPD | \
107 RK_I2C_IPD_BRFIPD | RK_I2C_IPD_MBTFIPD | RK_I2C_IPD_MBRFIPD | \
108 RK_I2C_IPD_STARTIPD | RK_I2C_IPD_STOPIPD | RK_I2C_IPD_NAKRCVIPD)
110 #define RK_I2C_FNCT 0x20
111 #define RK_I2C_FNCT_MASK 0x3F
113 #define RK_I2C_TXDATA_BASE 0x100
115 #define RK_I2C_RXDATA_BASE 0x200
125 struct rk_i2c_softc {
127 struct resource *res[2];
145 static struct ofw_compat_data compat_data[] = {
146 #ifdef SOC_ROCKCHIP_RK3328
147 {"rockchip,rk3328-i2c", 1},
152 static struct resource_spec rk_i2c_spec[] = {
153 { SYS_RES_MEMORY, 0, RF_ACTIVE },
154 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
158 static int rk_i2c_probe(device_t dev);
159 static int rk_i2c_attach(device_t dev);
160 static int rk_i2c_detach(device_t dev);
162 #define RK_I2C_LOCK(sc) mtx_lock(&(sc)->mtx)
163 #define RK_I2C_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
164 #define RK_I2C_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
165 #define RK_I2C_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
166 #define RK_I2C_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
169 rk_i2c_get_clkdiv(struct rk_i2c_softc *sc, uint64_t speed)
175 err = clk_get_freq(sc->pclk, &pclk_freq);
179 clkdiv = (pclk_freq / speed / RK_I2C_CLKDIV_MUL / 2) - 1;
180 clkdiv &= RK_I2C_CLKDIVL_MASK;
182 clkdiv = clkdiv << RK_I2C_CLKDIVH_SHIFT | clkdiv;
188 rk_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
190 struct rk_i2c_softc *sc;
194 sc = device_get_softc(dev);
196 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
198 clkdiv = rk_i2c_get_clkdiv(sc, busfreq);
202 /* Set the clock divider */
203 RK_I2C_WRITE(sc, RK_I2C_CLKDIV, clkdiv);
205 /* Disable the module */
206 RK_I2C_WRITE(sc, RK_I2C_CON, 0);
214 rk_i2c_fill_tx(struct rk_i2c_softc *sc)
220 if (sc->msg == NULL || sc->msg->len == sc->cnt)
223 len = sc->msg->len - sc->cnt;
227 for (i = 0; i < len; i++) {
229 for (j = 0; j < 4 ; j++) {
230 if (sc->cnt == sc->msg->len)
233 /* Fill the addr if needed */
235 buf = sc->msg->slave;
238 buf = sc->msg->buf[sc->cnt - 1];
240 buf32 |= buf << (j * 8);
245 RK_I2C_WRITE(sc, RK_I2C_TXDATA_BASE + 4 * i, buf32);
247 if (sc->cnt == sc->msg->len)
253 rk_i2c_drain_rx(struct rk_i2c_softc *sc)
260 if (sc->msg == NULL) {
261 device_printf(sc->dev, "No current iic msg\n");
265 len = sc->msg->len - sc->cnt;
269 for (i = 0; i < len; i++) {
271 buf32 = RK_I2C_READ(sc, RK_I2C_RXDATA_BASE + (i / 4) * 4);
273 buf8 = (buf32 >> ((i % 4) * 8)) & 0xFF;
275 sc->msg->buf[sc->cnt++] = buf8;
280 rk_i2c_send_start(struct rk_i2c_softc *sc)
284 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STARTIEN);
286 sc->state = STATE_START;
288 reg = RK_I2C_READ(sc, RK_I2C_CON);
289 reg |= RK_I2C_CON_START;
290 reg |= RK_I2C_CON_EN;
291 reg &= ~RK_I2C_CON_MODE_MASK;
292 reg |= sc->mode << RK_I2C_CON_MODE_SHIFT;
293 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
297 rk_i2c_send_stop(struct rk_i2c_softc *sc)
301 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STOPIEN);
303 sc->state = STATE_STOP;
305 reg = RK_I2C_READ(sc, RK_I2C_CON);
306 reg |= RK_I2C_CON_STOP;
307 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
311 rk_i2c_intr(void *arg)
313 struct rk_i2c_softc *sc;
316 sc = (struct rk_i2c_softc *)arg;
320 sc->ipd = RK_I2C_READ(sc, RK_I2C_IPD);
321 RK_I2C_WRITE(sc, RK_I2C_IPD, sc->ipd);
325 /* Disable start bit */
326 reg = RK_I2C_READ(sc, RK_I2C_CON);
327 reg &= ~RK_I2C_CON_START;
328 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
330 if (sc->mode == RK_I2C_CON_MODE_RRX ||
331 sc->mode == RK_I2C_CON_MODE_RX) {
332 sc->state = STATE_READ;
333 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN |
334 RK_I2C_IEN_NAKRCVIEN);
336 reg = RK_I2C_READ(sc, RK_I2C_CON);
337 reg |= RK_I2C_CON_LASTACK;
338 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
340 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, sc->msg->len);
342 sc->state = STATE_WRITE;
343 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
344 RK_I2C_IEN_NAKRCVIEN);
348 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, sc->msg->len);
354 if (sc->cnt == sc->msg->len)
355 rk_i2c_send_stop(sc);
359 if (sc->cnt == sc->msg->len)
360 rk_i2c_send_stop(sc);
364 /* Disable stop bit */
365 reg = RK_I2C_READ(sc, RK_I2C_CON);
366 reg &= ~RK_I2C_CON_STOP;
367 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
369 sc->transfer_done = 1;
370 sc->state = STATE_IDLE;
381 rk_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
383 struct rk_i2c_softc *sc;
385 int i, j, msgskip, err = 0;
387 sc = device_get_softc(dev);
390 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
394 err = clk_enable(sc->pclk);
396 device_printf(dev, "cannot enable pclk clock\n");
399 err = clk_enable(sc->sclk);
401 device_printf(dev, "cannot enable i2c clock\n");
407 /* Clean stale interrupts */
408 RK_I2C_WRITE(sc, RK_I2C_IPD, RK_I2C_IPD_ALL);
410 for (i = 0; i < nmsgs; i += msgskip) {
411 if (nmsgs - i >= 2 && !(msgs[i].flags & IIC_M_RD) &&
412 msgs[i + 1].flags & IIC_M_RD && msgs[i].len <= 4) {
413 sc->mode = RK_I2C_CON_MODE_RRX;
415 sc->msg = &msgs[i + 1];
417 /* Write slave address */
418 reg = msgs[i].slave | RK_I2C_MRXADDR_VALID(0);
419 RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg);
421 /* Write slave register address */
422 for (j = 0, reg = 0; j < msgs[i].len; j++) {
423 reg |= (msgs[i].buf[j] & 0xff) << (j * 8);
424 reg |= RK_I2C_MRXADDR_VALID(j);
427 RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, reg);
429 if (msgs[i].flags & IIC_M_RD) {
430 sc->mode = RK_I2C_CON_MODE_RX;
431 msgs[i].slave |= LSB;
434 sc->mode = RK_I2C_CON_MODE_TX;
435 msgs[i].slave &= ~LSB;
441 sc->transfer_done = 0;
443 sc->state = STATE_IDLE;
444 rk_i2c_send_start(sc);
446 while (err == 0 && sc->transfer_done != 1) {
447 err = msleep(sc, &sc->mtx, 0, "rk_i2c", 10 * hz);
451 /* Disable the module and interrupts */
452 RK_I2C_WRITE(sc, RK_I2C_CON, 0);
453 RK_I2C_WRITE(sc, RK_I2C_IEN, 0);
459 err = clk_disable(sc->pclk);
461 device_printf(dev, "cannot enable pclk clock\n");
464 err = clk_disable(sc->sclk);
466 device_printf(dev, "cannot enable i2c clock\n");
475 rk_i2c_probe(device_t dev)
478 if (!ofw_bus_status_okay(dev))
480 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
483 device_set_desc(dev, "RockChip I2C");
484 return (BUS_PROBE_DEFAULT);
488 rk_i2c_attach(device_t dev)
490 struct rk_i2c_softc *sc;
493 sc = device_get_softc(dev);
496 mtx_init(&sc->mtx, device_get_nameunit(dev), "rk_i2c", MTX_DEF);
498 if (bus_alloc_resources(dev, rk_i2c_spec, sc->res) != 0) {
499 device_printf(dev, "cannot allocate resources for device\n");
504 if (bus_setup_intr(dev, sc->res[1],
505 INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_i2c_intr, sc,
507 bus_release_resources(dev, rk_i2c_spec, sc->res);
508 device_printf(dev, "cannot setup interrupt handler\n");
512 /* Activate the module clocks. */
513 error = clk_get_by_ofw_name(dev, 0, "i2c", &sc->sclk);
515 device_printf(dev, "cannot get i2c clock\n");
518 error = clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk);
520 device_printf(dev, "cannot get pclk clock\n");
524 sc->iicbus = device_add_child(dev, "iicbus", -1);
525 if (sc->iicbus == NULL) {
526 device_printf(dev, "cannot add iicbus child device\n");
531 bus_generic_attach(dev);
536 if (rk_i2c_detach(dev) != 0)
537 device_printf(dev, "Failed to detach\n");
542 rk_i2c_detach(device_t dev)
544 struct rk_i2c_softc *sc;
547 sc = device_get_softc(dev);
549 if ((error = bus_generic_detach(dev)) != 0)
552 if (sc->iicbus != NULL)
553 if ((error = device_delete_child(dev, sc->iicbus)) != 0)
556 if (sc->sclk != NULL)
557 clk_release(sc->sclk);
558 if (sc->pclk != NULL)
559 clk_release(sc->pclk);
561 if (sc->intrhand != NULL)
562 bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
564 bus_release_resources(dev, rk_i2c_spec, sc->res);
566 mtx_destroy(&sc->mtx);
572 rk_i2c_get_node(device_t bus, device_t dev)
575 return ofw_bus_get_node(bus);
578 static device_method_t rk_i2c_methods[] = {
579 DEVMETHOD(device_probe, rk_i2c_probe),
580 DEVMETHOD(device_attach, rk_i2c_attach),
581 DEVMETHOD(device_detach, rk_i2c_detach),
584 DEVMETHOD(ofw_bus_get_node, rk_i2c_get_node),
586 DEVMETHOD(iicbus_callback, iicbus_null_callback),
587 DEVMETHOD(iicbus_reset, rk_i2c_reset),
588 DEVMETHOD(iicbus_transfer, rk_i2c_transfer),
593 static driver_t rk_i2c_driver = {
596 sizeof(struct rk_i2c_softc),
599 static devclass_t rk_i2c_devclass;
601 EARLY_DRIVER_MODULE(rk_i2c, simplebus, rk_i2c_driver, rk_i2c_devclass, 0, 0,
602 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
603 EARLY_DRIVER_MODULE(ofw_iicbus, rk_i2c, ofw_iicbus_driver, ofw_iicbus_devclass,
604 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
605 MODULE_DEPEND(rk_i2c, iicbus, 1, 1, 1);
606 MODULE_DEPEND(rk_i2c, ofw_iicbus, 1, 1, 1);
607 MODULE_VERSION(rk_i2c, 1);