sys/arm64/rockchip/rk_otp.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2022 Soren Schmidt <sos@deepcore.dk>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 #include <sys/param.h>
  30 #include <sys/bus.h>
  31 #include <sys/kernel.h>
  32 #include <sys/module.h>
  33 #include <sys/mutex.h>
  34 #include <sys/rman.h>
  35 #include <machine/bus.h>
  36
  37 #include <dev/ofw/openfirm.h>
  38 #include <dev/ofw/ofw_bus.h>
  39 #include <dev/ofw/ofw_bus_subr.h>
  40
  41 #include <dev/extres/syscon/syscon.h>
  42 #include <dev/fdt/simple_mfd.h>
  43
  44 #include "rk_otp.h"
  45 #include "rk_otp_if.h"
  46
  47 #define OTPC_SBPI_CTRL                  0x0020
  48 #define  SBPI_ENABLE_MASK               0x00010000
  49 #define  SBPI_ENABLE                    1
  50 #define  SBPI_DAP_ADDR_MASK             0xff000000
  51 #define  SBPI_DAP_ADDR                  0x02
  52 #define  SBPI_DAP_ADDR_SHIFT            8
  53 #define OTPC_SBPI_CMD_VALID_PRE         0x0024
  54 #define  SBPI_CMD_VALID_MASK            0xffff0000
  55 #define OTPC_SBPI_INT_STATUS            0x0304
  56 #define  OTPC_SBPI_DONE                 2
  57 #define  OTPC_USER_DONE                 4
  58 #define OTPC_USER_CTRL                  0x0100
  59 #define  OTPC_USER_MASK                 0xffff0000
  60 #define  OTPC_USER                      1
  61 #define OTPC_USER_ADDR                  0x0104
  62 #define  OTPC_USER_ADDR_MASK            0xffff0000
  63 #define OTPC_USER_ENABLE                0x0108
  64 #define  OTPC_USER_FSM_ENABLE_MASK      0xffff0000
  65 #define  OTPC_USER_FSM_ENABLE           1
  66 #define OTPC_USER_Q                     0x0124
  67 #define OTPC_SBPI_CMD0_OFFSET           0x1000
  68 #define  SBPI_DAP_CMD_WRF               0xc0
  69 #define  SBPI_DAP_REG_ECC               0x3a
  70 #define OTPC_SBPI_CMD1_OFFSET           0x1004
  71 #define  SBPI_ECC_ENABLE                0x00
  72 #define  SBPI_ECC_DISABLE               0x09
  73
  74
  75 static struct ofw_compat_data compat_data[] = {
  76         {"rockchip,rk3568-otp", 1},
  77         {NULL,                  0}
  78 };
  79
  80 static struct rk_otp_softc {
  81         struct resource *mem;
  82 } rk_otp_sc;
  83
  84
  85 static int
  86 rk_otp_wait(struct rk_otp_softc *sc, uint32_t status)
  87 {
  88         int retry = 10000;
  89
  90         while (!(bus_read_4(sc->mem, OTPC_SBPI_INT_STATUS) & status)) {
  91                 DELAY(10);
  92                 if (--retry == 0)
  93                         return (ETIMEDOUT);
  94         }
  95
  96         /* clear status */
  97         bus_write_4(sc->mem, OTPC_SBPI_INT_STATUS, status);
  98
  99         return (0);
 100 }
 101
 102 static int
 103 rk_otp_ecc(struct rk_otp_softc *sc, int enable)
 104 {
 105         bus_write_4(sc->mem, OTPC_SBPI_CTRL,
 106             SBPI_DAP_ADDR_MASK | (SBPI_DAP_ADDR << SBPI_DAP_ADDR_SHIFT));
 107         bus_write_4(sc->mem, OTPC_SBPI_CMD_VALID_PRE,
 108             SBPI_CMD_VALID_MASK | 0x1);
 109         bus_write_4(sc->mem, OTPC_SBPI_CMD0_OFFSET,
 110             SBPI_DAP_CMD_WRF | SBPI_DAP_REG_ECC);
 111         if (enable)
 112                 bus_write_4(sc->mem, OTPC_SBPI_CMD1_OFFSET, SBPI_ECC_ENABLE);
 113         else
 114                 bus_write_4(sc->mem, OTPC_SBPI_CMD1_OFFSET, SBPI_ECC_DISABLE);
 115         bus_write_4(sc->mem, OTPC_SBPI_CTRL, SBPI_ENABLE_MASK | SBPI_ENABLE);
 116
 117         return (rk_otp_wait(sc, OTPC_SBPI_DONE));
 118 }
 119
 120 int
 121 rk_otp_read(device_t dev, uint8_t *buffer, int offset, int size)
 122 {
 123         struct rk_otp_softc *sc = &rk_otp_sc;
 124         int error;
 125
 126         /* if not initialized just error out */
 127         if (!sc->mem)
 128                 return (ENXIO);
 129
 130         if ((error = rk_otp_ecc(sc, 1))) {
 131                 device_printf(dev, "timeout waiting for OTP ECC status\n");
 132                 return (error);
 133         }
 134
 135         bus_write_4(sc->mem, OTPC_USER_CTRL, OTPC_USER | OTPC_USER_MASK);
 136         DELAY(5);
 137         while (size--) {
 138                 bus_write_4(sc->mem, OTPC_USER_ADDR,
 139                     offset++ | OTPC_USER_ADDR_MASK);
 140                 bus_write_4(sc->mem, OTPC_USER_ENABLE,
 141                     OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK);
 142
 143                 if ((error = rk_otp_wait(sc, OTPC_USER_DONE))) {
 144                         device_printf(dev, "timeout waiting for OTP data\n");
 145                         break;
 146                 }
 147                 *buffer++ = bus_read_4(sc->mem, OTPC_USER_Q);
 148         }
 149         bus_write_4(sc->mem, OTPC_USER_CTRL, OTPC_USER_MASK);
 150
 151         return (error);
 152 }
 153
 154 static int
 155 rk_otp_probe(device_t dev)
 156 {
 157
 158         if (!ofw_bus_status_okay(dev))
 159                 return (ENXIO);
 160         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
 161                 return (ENXIO);
 162         device_set_desc(dev, "RockChip OTP");
 163         return (BUS_PROBE_DEFAULT);
 164 }
 165
 166 static int
 167 rk_otp_attach(device_t dev)
 168 {
 169         struct rk_otp_softc *sc = &rk_otp_sc;
 170         int rid = 0;
 171
 172         sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
 173         if (!sc->mem) {
 174                 device_printf(dev, "Cannot allocate memory resources\n");
 175                 return (ENXIO);
 176         }
 177         return (0);
 178 }
 179
 180
 181 static device_method_t rk_otp_methods[] = {
 182         /* Device interface */
 183         DEVMETHOD(device_probe,         rk_otp_probe),
 184         DEVMETHOD(device_attach,        rk_otp_attach),
 185
 186         DEVMETHOD_END
 187 };
 188
 189 DEFINE_CLASS_1(rk_otp, rk_otp_driver, rk_otp_methods,
 190     sizeof(struct simple_mfd_softc), simple_mfd_driver);
 191 EARLY_DRIVER_MODULE(rk_otp, simplebus, rk_otp_driver, 0, 0,
 192     BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);