2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
43 #include <machine/bus.h>
45 #include <dev/fdt/fdt_common.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
48 #include <dev/ofw/ofw_subr.h>
50 #include <dev/extres/clk/clk.h>
51 #include <dev/extres/phy/phy.h>
52 #include <dev/extres/phy/phy_internal.h>
53 #include <dev/extres/syscon/syscon.h>
54 #include <dev/extres/hwreset/hwreset.h>
56 #include "syscon_if.h"
58 #define GRF_HIWORD_SHIFT 16
59 #define GRF_SOC_CON_5_PCIE 0xE214
60 #define CON_5_PCIE_IDLE_OFF(x) (1 <<(((x) & 0x3) + 3))
61 #define GRF_SOC_CON8 0xE220
62 #define GRF_SOC_STATUS1 0xE2A4
64 /* PHY config registers - write */
65 #define PHY_CFG_CLK_TEST 0x10
66 #define CLK_TEST_SEPE_RATE (1 << 3)
67 #define PHY_CFG_CLK_SCC 0x12
68 #define CLK_SCC_PLL_100M (1 << 3)
70 /* PHY config registers - read */
71 #define PHY_CFG_PLL_LOCK 0x10
72 #define CLK_PLL_LOCKED (1 << 1)
73 #define PHY_CFG_SCC_LOCK 0x12
74 #define CLK_SCC_100M_GATE (1 << 2)
77 #define STATUS1_PLL_LOCKED (1 << 9)
79 static struct ofw_compat_data compat_data[] = {
80 {"rockchip,rk3399-pcie-phy", 1},
85 struct rk_pcie_phy_softc {
87 struct syscon *syscon;
90 hwreset_t hwreset_phy;
94 #define PHY_LOCK(_sc) mtx_lock(&(_sc)->mtx)
95 #define PHY_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
96 #define PHY_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
97 device_get_nameunit(_sc->dev), "rk_pcie_phyc", MTX_DEF)
98 #define PHY_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx);
99 #define PHY_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED);
100 #define PHY_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED);
103 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg))
104 #define WR4(sc, reg, mask, val) \
105 SYSCON_WRITE_4((sc)->syscon, (reg), ((mask) << GRF_HIWORD_SHIFT) | (val))
111 cfg_write(struct rk_pcie_phy_softc *sc, uint32_t reg, uint32_t data)
113 /* setup register address and data first */
114 WR4(sc, GRF_SOC_CON8, 0x7FF,
115 (reg & 0x3F) << 1 | (data & 0x0F) << 7);
116 /* dummy readback for sync */
117 RD4(sc, GRF_SOC_CON8);
120 WR4(sc, GRF_SOC_CON8, 1, 1);
121 RD4(sc, GRF_SOC_CON8);
123 WR4(sc, GRF_SOC_CON8, 1, 0);
124 RD4(sc, GRF_SOC_CON8);
129 cfg_read(struct rk_pcie_phy_softc *sc, uint32_t reg)
133 WR4(sc, GRF_SOC_CON8, 0x3FF, reg << 1);
134 RD4(sc, GRF_SOC_CON8);
136 val = RD4(sc, GRF_SOC_STATUS1);
137 return ((val >> 8) & 0x0f);
141 rk_pcie_phy_up(struct rk_pcie_phy_softc *sc, int id)
149 if (sc->enable_count != 1) {
154 rv = hwreset_deassert(sc->hwreset_phy);
156 device_printf(sc->dev, "Cannot deassert 'phy' reset\n");
160 /* Un-idle all lanes */
161 for (i = 0; i < MAX_LANE; i++)
162 WR4(sc, GRF_SOC_CON_5_PCIE, CON_5_PCIE_IDLE_OFF(i), 0);
164 /* Wait for PLL lock */
165 for (i = 100; i > 0; i--) {
166 val = cfg_read(sc, PHY_CFG_PLL_LOCK);
167 if (val & CLK_PLL_LOCKED)
172 device_printf(sc->dev, "PLL lock timeouted, 0x%02X\n", val);
176 /* Switch PLL to stable 5GHz, rate adjustment is done by divider */
177 cfg_write(sc, PHY_CFG_CLK_TEST, CLK_TEST_SEPE_RATE);
178 /* Enable 100MHz output for PCIe ref clock */
179 cfg_write(sc, PHY_CFG_CLK_SCC, CLK_SCC_PLL_100M);
181 /* Wait for ungating of ref clock */
182 for (i = 100; i > 0; i--) {
183 val = cfg_read(sc, PHY_CFG_SCC_LOCK);
184 if ((val & CLK_SCC_100M_GATE) == 0)
189 device_printf(sc->dev, "PLL output enable timeouted\n");
194 /* Wait for PLL relock (to 5GHz) */
195 for (i = 100; i > 0; i--) {
196 val = cfg_read(sc, PHY_CFG_PLL_LOCK);
197 if (val & CLK_PLL_LOCKED)
202 device_printf(sc->dev, "PLL relock timeouted\n");
212 rk_pcie_phy_down(struct rk_pcie_phy_softc *sc, int id)
219 if (sc->enable_count <= 0)
220 panic("unpaired enable/disable");
224 /* Idle given lane */
225 WR4(sc, GRF_SOC_CON_5_PCIE,
226 CON_5_PCIE_IDLE_OFF(id),
227 CON_5_PCIE_IDLE_OFF(id));
229 if (sc->enable_count == 0) {
230 rv = hwreset_assert(sc->hwreset_phy);
232 device_printf(sc->dev, "Cannot assert 'phy' reset\n");
239 rk_pcie_phy_enable(struct phynode *phynode, bool enable)
241 struct rk_pcie_phy_softc *sc;
246 dev = phynode_get_device(phynode);
247 phy = phynode_get_id(phynode);
248 sc = device_get_softc(dev);
251 rv = rk_pcie_phy_up(sc, (int)phy);
253 rv = rk_pcie_phy_down(sc, (int) phy);
259 /* Phy class and methods. */
260 static int rk_pcie_phy_enable(struct phynode *phynode, bool enable);
261 static phynode_method_t rk_pcie_phy_phynode_methods[] = {
262 PHYNODEMETHOD(phynode_enable, rk_pcie_phy_enable),
267 DEFINE_CLASS_1( rk_pcie_phy_phynode, rk_pcie_phy_phynode_class,
268 rk_pcie_phy_phynode_methods, 0, phynode_class);
271 rk_pcie_phy_probe(device_t dev)
274 if (!ofw_bus_status_okay(dev))
277 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
280 device_set_desc(dev, "Rockchip RK3399 PCIe PHY");
281 return (BUS_PROBE_DEFAULT);
285 rk_pcie_phy_attach(device_t dev)
287 struct rk_pcie_phy_softc *sc;
288 struct phynode_init_def phy_init;
289 struct phynode *phynode;
293 sc = device_get_softc(dev);
295 node = ofw_bus_get_node(dev);
298 if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 ||
299 sc->syscon == NULL) {
300 device_printf(dev, "cannot get syscon for device\n");
305 rv = clk_get_by_ofw_name(sc->dev, 0, "refclk", &sc->clk_ref);
307 device_printf(sc->dev, "Cannot get 'refclk' clock\n");
311 rv = hwreset_get_by_ofw_name(sc->dev, 0, "phy", &sc->hwreset_phy);
313 device_printf(sc->dev, "Cannot get 'phy' reset\n");
318 rv = hwreset_assert(sc->hwreset_phy);
320 device_printf(sc->dev, "Cannot assert 'phy' reset\n");
325 rv = clk_enable(sc->clk_ref);
327 device_printf(sc->dev, "Cannot enable 'ref' clock\n");
332 for (i = 0; i < MAX_LANE; i++) {
334 phy_init.ofw_node = node;
335 phynode = phynode_create(dev, &rk_pcie_phy_phynode_class,
337 if (phynode == NULL) {
338 device_printf(dev, "Cannot create phy[%d]\n", i);
342 if (phynode_register(phynode) == NULL) {
343 device_printf(dev, "Cannot register phy[%d]\n", i);
355 static device_method_t rk_pcie_phy_methods[] = {
356 /* Device interface */
357 DEVMETHOD(device_probe, rk_pcie_phy_probe),
358 DEVMETHOD(device_attach, rk_pcie_phy_attach),
363 DEFINE_CLASS_0(rk_pcie_phy, rk_pcie_phy_driver, rk_pcie_phy_methods,
364 sizeof(struct rk_pcie_phy_softc));
366 static devclass_t rk_pcie_phy_devclass;
367 EARLY_DRIVER_MODULE(rk_pcie_phy, simplebus, rk_pcie_phy_driver,
368 rk_pcie_phy_devclass, NULL, NULL,
369 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);