2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2019 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
41 #include <sys/resource.h>
42 #include <machine/bus.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
47 #include <dev/spibus/spi.h>
48 #include <dev/spibus/spibusvar.h>
50 #include <dev/extres/clk/clk.h>
51 #include <dev/extres/hwreset/hwreset.h>
53 #include "spibus_if.h"
55 #define RK_SPI_CTRLR0 0x0000
56 #define CTRLR0_OPM_MASTER (0 << 20)
57 #define CTRLR0_XFM_TR (0 << 18)
58 #define CTRLR0_FRF_MOTO (0 << 16)
59 #define CTRLR0_BHT_8BIT (1 << 13)
60 #define CTRLR0_EM_BIG (1 << 11)
61 #define CTRLR0_SSD_ONE (1 << 10)
62 #define CTRLR0_SCPOL (1 << 7)
63 #define CTRLR0_SCPH (1 << 6)
64 #define CTRLR0_DFS_8BIT (1 << 0)
65 #define RK_SPI_CTRLR1 0x0004
66 #define RK_SPI_ENR 0x0008
67 #define RK_SPI_SER 0x000c
68 #define RK_SPI_BAUDR 0x0010
69 #define RK_SPI_TXFTLR 0x0014
70 #define RK_SPI_RXFTLR 0x0018
71 #define RK_SPI_TXFLR 0x001c
72 #define RK_SPI_RXFLR 0x0020
73 #define RK_SPI_SR 0x0024
74 #define SR_BUSY (1 << 0)
75 #define RK_SPI_IPR 0x0028
76 #define RK_SPI_IMR 0x002c
77 #define IMR_RFFIM (1 << 4)
78 #define IMR_TFEIM (1 << 0)
79 #define RK_SPI_ISR 0x0030
80 #define ISR_RFFIS (1 << 4)
81 #define ISR_TFEIS (1 << 0)
82 #define RK_SPI_RISR 0x0034
83 #define RK_SPI_ICR 0x0038
84 #define RK_SPI_DMACR 0x003c
85 #define RK_SPI_DMATDLR 0x0040
86 #define RK_SPI_DMARDLR 0x0044
87 #define RK_SPI_TXDR 0x0400
88 #define RK_SPI_RXDR 0x0800
92 static struct ofw_compat_data compat_data[] = {
93 { "rockchip,rk3399-spi", 1 },
97 static struct resource_spec rk_spi_spec[] = {
98 { SYS_RES_MEMORY, 0, RF_ACTIVE },
99 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
103 struct rk_spi_softc {
106 struct resource *res[2];
124 #define RK_SPI_LOCK(sc) mtx_lock(&(sc)->mtx)
125 #define RK_SPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
126 #define RK_SPI_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))
127 #define RK_SPI_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
129 static int rk_spi_probe(device_t dev);
130 static int rk_spi_attach(device_t dev);
131 static int rk_spi_detach(device_t dev);
132 static void rk_spi_intr(void *arg);
135 rk_spi_enable_chip(struct rk_spi_softc *sc, int enable)
138 RK_SPI_WRITE_4(sc, RK_SPI_ENR, enable ? 1 : 0);
142 rk_spi_set_cs(struct rk_spi_softc *sc, uint32_t cs, bool active)
146 if (cs & SPIBUS_CS_HIGH) {
147 device_printf(sc->dev, "SPIBUS_CS_HIGH is not supported\n");
154 reg = RK_SPI_READ_4(sc, RK_SPI_SER);
159 RK_SPI_WRITE_4(sc, RK_SPI_SER, reg);
165 rk_spi_hw_setup(struct rk_spi_softc *sc, uint32_t mode, uint32_t freq)
170 cr0 = CTRLR0_OPM_MASTER | CTRLR0_XFM_TR | CTRLR0_FRF_MOTO |
171 CTRLR0_BHT_8BIT | CTRLR0_EM_BIG | CTRLR0_SSD_ONE |
174 if (mode & SPIBUS_MODE_CPHA)
176 if (mode & SPIBUS_MODE_CPOL)
179 /* minimum divider is 2 */
180 if (sc->max_freq < freq*2) {
181 clk_set_freq(sc->clk_spi, 2 * freq, CLK_SET_ROUND_DOWN);
182 clk_get_freq(sc->clk_spi, &sc->max_freq);
185 div = ((sc->max_freq + freq - 1) / freq);
186 div = (div + 1) & 0xfffe;
187 RK_SPI_WRITE_4(sc, RK_SPI_BAUDR, div);
189 RK_SPI_WRITE_4(sc, RK_SPI_CTRLR0, cr0);
193 rk_spi_fifo_size(struct rk_spi_softc *sc)
195 uint32_t txftlr, reg;
197 for (txftlr = 2; txftlr < 32; txftlr++) {
198 RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, txftlr);
199 reg = RK_SPI_READ_4(sc, RK_SPI_TXFTLR);
203 RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, 0);
212 rk_spi_empty_rxfifo(struct rk_spi_softc *sc)
215 rxlevel = RK_SPI_READ_4(sc, RK_SPI_RXFLR);
216 while (sc->rxidx < sc->rxlen &&
218 sc->rxbuf[sc->rxidx++] = (uint8_t)RK_SPI_READ_4(sc, RK_SPI_RXDR);
223 rk_spi_fill_txfifo(struct rk_spi_softc *sc)
226 txlevel = RK_SPI_READ_4(sc, RK_SPI_TXFLR);
229 while (sc->txidx < sc->txlen && txlevel < sc->fifo_size) {
230 RK_SPI_WRITE_4(sc, RK_SPI_TXDR, sc->txbuf[sc->txidx++]);
235 if (sc->txidx != sc->txlen)
236 sc->intreg |= (IMR_TFEIM | IMR_RFFIM);
240 rk_spi_xfer_buf(struct rk_spi_softc *sc, void *rxbuf, void *txbuf, uint32_t len)
254 rk_spi_fill_txfifo(sc);
256 RK_SPI_WRITE_4(sc, RK_SPI_IMR, sc->intreg);
259 while (err == 0 && sc->intreg != 0)
260 err = msleep(sc, &sc->mtx, 0, "rk_spi", 10 * hz);
262 while (err == 0 && sc->rxidx != sc->txidx) {
263 /* read residual data from RX fifo */
264 rk_spi_empty_rxfifo(sc);
267 if (sc->rxidx != sc->rxlen || sc->txidx != sc->txlen)
274 rk_spi_probe(device_t dev)
276 if (!ofw_bus_status_okay(dev))
279 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
282 device_set_desc(dev, "Rockchip SPI");
283 return (BUS_PROBE_DEFAULT);
287 rk_spi_attach(device_t dev)
289 struct rk_spi_softc *sc;
292 sc = device_get_softc(dev);
295 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
297 if (bus_alloc_resources(dev, rk_spi_spec, sc->res) != 0) {
298 device_printf(dev, "cannot allocate resources for device\n");
303 if (bus_setup_intr(dev, sc->res[1],
304 INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_spi_intr, sc,
306 bus_release_resources(dev, rk_spi_spec, sc->res);
307 device_printf(dev, "cannot setup interrupt handler\n");
311 /* Activate the module clock. */
312 error = clk_get_by_ofw_name(dev, 0, "apb_pclk", &sc->clk_apb);
314 device_printf(dev, "cannot get apb_pclk clock\n");
317 error = clk_get_by_ofw_name(dev, 0, "spiclk", &sc->clk_spi);
319 device_printf(dev, "cannot get spiclk clock\n");
322 error = clk_enable(sc->clk_apb);
324 device_printf(dev, "cannot enable ahb clock\n");
327 error = clk_enable(sc->clk_spi);
329 device_printf(dev, "cannot enable spiclk clock\n");
332 clk_get_freq(sc->clk_spi, &sc->max_freq);
334 sc->fifo_size = rk_spi_fifo_size(sc);
335 if (sc->fifo_size == 0) {
336 device_printf(dev, "failed to get fifo size\n");
340 sc->spibus = device_add_child(dev, "spibus", -1);
342 RK_SPI_WRITE_4(sc, RK_SPI_IMR, 0);
343 RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, sc->fifo_size/2 - 1);
344 RK_SPI_WRITE_4(sc, RK_SPI_RXFTLR, sc->fifo_size/2 - 1);
346 return (bus_generic_attach(dev));
354 rk_spi_detach(device_t dev)
356 struct rk_spi_softc *sc;
358 sc = device_get_softc(dev);
360 bus_generic_detach(sc->dev);
361 if (sc->spibus != NULL)
362 device_delete_child(dev, sc->spibus);
364 if (sc->clk_spi != NULL)
365 clk_release(sc->clk_spi);
367 clk_release(sc->clk_apb);
369 if (sc->intrhand != NULL)
370 bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
372 bus_release_resources(dev, rk_spi_spec, sc->res);
373 mtx_destroy(&sc->mtx);
379 rk_spi_intr(void *arg)
381 struct rk_spi_softc *sc;
382 uint32_t intreg, isr;
387 intreg = RK_SPI_READ_4(sc, RK_SPI_IMR);
388 isr = RK_SPI_READ_4(sc, RK_SPI_ISR);
389 RK_SPI_WRITE_4(sc, RK_SPI_ICR, isr);
392 rk_spi_empty_rxfifo(sc);
395 rk_spi_fill_txfifo(sc);
397 /* no bytes left, disable interrupt */
398 if (sc->txidx == sc->txlen) {
403 if (sc->intreg != intreg) {
404 (void)RK_SPI_WRITE_4(sc, RK_SPI_IMR, sc->intreg);
405 (void)RK_SPI_READ_4(sc, RK_SPI_IMR);
412 rk_spi_get_node(device_t bus, device_t dev)
415 return ofw_bus_get_node(bus);
419 rk_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
421 struct rk_spi_softc *sc;
422 uint32_t cs, mode, clock;
425 sc = device_get_softc(dev);
427 spibus_get_cs(child, &cs);
428 spibus_get_clock(child, &clock);
429 spibus_get_mode(child, &mode);
432 rk_spi_hw_setup(sc, mode, clock);
433 rk_spi_enable_chip(sc, 1);
434 err = rk_spi_set_cs(sc, cs, true);
436 rk_spi_enable_chip(sc, 0);
441 /* Transfer command then data bytes. */
443 if (cmd->tx_cmd_sz > 0)
444 err = rk_spi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd,
446 if (cmd->tx_data_sz > 0 && err == 0)
447 err = rk_spi_xfer_buf(sc, cmd->rx_data, cmd->tx_data,
450 rk_spi_set_cs(sc, cs, false);
451 rk_spi_enable_chip(sc, 0);
457 static device_method_t rk_spi_methods[] = {
458 /* Device interface */
459 DEVMETHOD(device_probe, rk_spi_probe),
460 DEVMETHOD(device_attach, rk_spi_attach),
461 DEVMETHOD(device_detach, rk_spi_detach),
464 DEVMETHOD(spibus_transfer, rk_spi_transfer),
467 DEVMETHOD(ofw_bus_get_node, rk_spi_get_node),
472 static driver_t rk_spi_driver = {
475 sizeof(struct rk_spi_softc),
478 static devclass_t rk_spi_devclass;
480 DRIVER_MODULE(rk_spi, simplebus, rk_spi_driver, rk_spi_devclass, 0, 0);
481 DRIVER_MODULE(ofw_spibus, rk_spi, ofw_spibus_driver, ofw_spibus_devclass, 0, 0);
482 MODULE_DEPEND(rk_spi, ofw_spibus, 1, 1, 1);
483 OFWBUS_PNP_INFO(compat_data);