2 * Copyright (c) 1996, Sujal M. Patel
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Sujal M. Patel
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #ifndef _I386_ISA_PNP_H_
36 #define _I386_ISA_PNP_H_
38 /* Maximum Number of PnP Devices. 8 should be plenty */
39 #define MAX_PNP_CARDS 8
41 * the following is the maximum number of PnP Logical devices that
42 * userconfig can handle.
44 #define MAX_PNP_LDN 20
46 /* Static ports to access PnP state machine */
49 /* pnp.h is included from pnpinfo.c. */
50 #define _PNP_ADDRESS 0x259
51 #define _PNP_WRITE_DATA 0xa59
53 #define _PNP_ADDRESS 0x279
54 #define _PNP_WRITE_DATA 0xa79
58 /* PnP Registers. Write to ADDRESS and then use WRITE/READ_DATA */
59 #define SET_RD_DATA 0x00
61 Writing to this location modifies the address of the port used for
62 reading from the Plug and Play ISA cards. Bits[7:0] become I/O
63 read port address bits[9:2]. Reads from this register are ignored.
66 #define SERIAL_ISOLATION 0x01
68 A read to this register causes a Plug and Play cards in the Isolation
69 state to compare one bit of the boards ID.
70 This register is read only.
73 #define CONFIG_CONTROL 0x02
76 Bit[1] Return to the Wait for Key state
77 Bit[0] Reset all logical devices and restore configuration
78 registers to their power-up values.
80 A write to bit[0] of this register performs a reset function on
81 all logical devices. This resets the contents of configuration
82 registers to their default state. All card's logical devices
83 enter their default state and the CSN is preserved.
85 A write to bit[1] of this register causes all cards to enter the
86 Wait for Key state but all CSNs are preserved and logical devices
89 A write to bit[2] of this register causes all cards to reset their
92 This register is write-only. The values are not sticky, that is,
93 hardware will automatically clear them and there is no need for
94 software to clear the bits.
99 A write to this port will cause all cards that have a CSN that
100 matches the write data[7:0] to go from the Sleep state to the either
101 the Isolation state if the write data for this command is zero or
102 the Config state if the write data is not zero. Additionally, the
103 pointer to the byte-serial device is reset. This register is
107 #define RESOURCE_DATA 0x04
109 A read from this address reads the next byte of resource information.
110 The Status register must be polled until bit[0] is set before this
111 register may be read. This register is read only.
116 Bit[0] when set indicates it is okay to read the next data byte
117 from the Resource Data register. This register is readonly.
122 A write to this port sets a card's CSN. The CSN is a value uniquely
123 assigned to each ISA card after the serial identification process
124 so that each card may be individually selected during a Wake[CSN]
125 command. This register is read/write.
130 Selects the current logical device. All reads and writes of memory,
131 I/O, interrupt and DMA configuration information access the registers
132 of the logical device written here. In addition, the I/O Range
133 Check and Activate commands operate only on the selected logical
134 device. This register is read/write. If a card has only 1 logical
135 device, this location should be a read-only value of 0x00.
138 /*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/
139 /*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/
141 #define ACTIVATE 0x30
143 For each logical device there is one activate register that controls
144 whether or not the logical device is active on the ISA bus. Bit[0],
145 if set, activates the logical device. Bits[7:1] are reserved and
146 must return 0 on reads. This is a read/write register. Before a
147 logical device is activated, I/O range check must be disabled.
150 #define IO_RANGE_CHECK 0x31
152 This register is used to perform a conflict check on the I/O port
153 range programmed for use by a logical device.
155 Bit[7:2] Reserved and must return 0 on reads
156 Bit[1] Enable I/O Range check, if set then I/O Range Check
157 is enabled. I/O range check is only valid when the logical
160 Bit[0], if set, forces the logical device to respond to I/O reads
161 of the logical device's assigned I/O range with a 0x55 when I/O
162 range check is in operation. If clear, the logical device drives
163 0xAA. This register is read/write.
166 /*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/
167 /*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/
169 #define MEM_CONFIG 0x40
171 Four memory resource registers per range, four ranges.
172 Fill with 0 if no ranges are enabled.
174 Offset 0: RW Memory base address bits[23:16]
175 Offset 1: RW Memory base address bits[15:8]
176 Offset 2: Memory control
177 Bit[1] specifies 8/16-bit control. This bit is set to indicate
178 16-bit memory, and cleared to indicate 8-bit memory.
179 Bit[0], if cleared, indicates the next field can be used as a range
180 length for decode (implies range length and base alignment of memory
181 descriptor are equal).
182 Bit[0], if set, indicates the next field is the upper limit for
183 the address. - - Bit[0] is read-only.
184 Offset 3: RW upper limit or range len, bits[23:16]
185 Offset 4: RW upper limit or range len, bits[15:8]
186 Offset 5-Offset 7: filler, unused.
189 #define IO_CONFIG_BASE 0x60
191 Eight ranges, two bytes per range.
192 Offset 0: I/O port base address bits[15:8]
193 Offset 1: I/O port base address bits[7:0]
196 #define IRQ_CONFIG 0x70
198 Two entries, two bytes per entry.
199 Offset 0: RW interrupt level (1..15, 0=unused).
200 Offset 1: Bit[1]: level(1:hi, 0:low),
201 Bit[0]: type (1:level, 0:edge)
202 byte 1 can be readonly if 1 type of int is used.
205 #define DRQ_CONFIG 0x74
207 Two entries, one byte per entry. Bits[2:0] select
208 which DMA channel is in use for DMA 0. Zero selects DMA channel
209 0, seven selects DMA channel 7. DMA channel 4, the cascade channel
210 is used to indicate no DMA channel is active.
213 /*** 32-bit memory accesses are at 0x76 ***/
215 /* Macros to parse Resource IDs */
216 #define PNP_RES_TYPE(a) (a >> 7)
217 #define PNP_SRES_NUM(a) (a >> 3)
218 #define PNP_SRES_LEN(a) (a & 0x07)
219 #define PNP_LRES_NUM(a) (a & 0x7f)
221 /* Small Resource Item names */
222 #define PNP_VERSION 0x1
223 #define LOG_DEVICE_ID 0x2
224 #define COMP_DEVICE_ID 0x3
225 #define IRQ_FORMAT 0x4
226 #define DMA_FORMAT 0x5
227 #define START_DEPEND_FUNC 0x6
228 #define END_DEPEND_FUNC 0x7
229 #define IO_PORT_DESC 0x8
230 #define FIXED_IO_PORT_DESC 0x9
231 #define SM_RES_RESERVED 0xa-0xd
232 #define SM_VENDOR_DEFINED 0xe
235 /* Large Resource Item names */
236 #define MEMORY_RANGE_DESC 0x1
237 #define ID_STRING_ANSI 0x2
238 #define ID_STRING_UNICODE 0x3
239 #define LG_VENDOR_DEFINED 0x4
240 #define _32BIT_MEM_RANGE_DESC 0x5
241 #define _32BIT_FIXED_LOC_DESC 0x6
242 #define LG_RES_RESERVED 0x7-0x7f
245 * pnp_cinfo contains Configuration Information. They are used
246 * to communicate to the device driver the actual configuration
247 * of the device, and also by the userconfig menu to let the
248 * operating system override any configuration set by the bios.
252 u_int vendor_id; /* board id */
253 u_int serial; /* Board's Serial Number */
254 u_long flags; /* OS-reserved flags */
255 u_char csn; /* assigned Card Select Number */
256 u_char ldn; /* Logical Device Number */
257 u_char enable; /* pnp enable */
258 u_char override; /* override bios parms (in userconfig) */
259 u_char irq[2]; /* IRQ Number */
260 u_char irq_type[2]; /* IRQ Type */
262 u_short port[8]; /* The Base Address of the Port */
264 u_long base; /* Memory Base Address */
265 int control; /* Memory Control Register */
266 u_long range; /* Memory Range *OR* Upper Limit */
274 char * (*pd_probe ) (u_long csn, u_long vendor_id);
275 void (*pd_attach ) (u_long csn, u_long vend_id, char * name,
276 struct isa_device *dev);
287 struct pnp_dlist_node {
288 struct pnp_device *pnp;
289 struct isa_device dev;
290 struct pnp_dlist_node *next;
293 typedef struct _pnp_id pnp_id;
294 extern struct pnp_dlist_node *pnp_device_list;
295 extern pnp_id pnp_devices[MAX_PNP_CARDS];
296 extern struct pnp_cinfo pnp_ldn_overrides[MAX_PNP_LDN];
297 extern int pnp_overrides_valid;
300 * these two functions are for use in drivers
302 int read_pnp_parms(struct pnp_cinfo *d, int ldn);
303 int write_pnp_parms(struct pnp_cinfo *d, int ldn);
304 int enable_pnp_card(void);
307 * used by autoconfigure to actually probe and attach drivers
309 void pnp_configure(void);
313 #endif /* !_I386_ISA_PNP_H_ */