2 * MPC8555 CDS Device Tree Source
4 * Copyright 2006, 2008 Freescale Semiconductor Inc. All rights reserved
6 * Neither the name of Freescale Semiconductor, Inc nor the names of
7 * its contributors may be used to endorse or promote products derived
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40 * GNU General Public License, version 2
42 * This program is free software; you can redistribute it and/or
43 * modify it under the terms of the GNU General Public License
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47 * This program is distributed in the hope that it will be useful,
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58 *------------------------------------------------------------------
67 compatible = "MPC8555CDS", "MPC85xxCDS";
87 d-cache-line-size = <32>; // 32 bytes
88 i-cache-line-size = <32>; // 32 bytes
89 d-cache-size = <0x8000>; // L1, 32K
90 i-cache-size = <0x8000>; // L1, 32K
91 timebase-frequency = <0>; // 33 MHz, from uboot
92 bus-frequency = <0>; // 166 MHz
93 clock-frequency = <0>; // 825 MHz, from uboot
94 next-level-cache = <&L2>;
99 device_type = "memory";
100 reg = <0x0 0x10000000>; // 256M at 0x0
104 #address-cells = <2>;
106 compatible = "fsl,lbc", "fsl,elbc";
107 reg = <0xe0005000 0x1000>;
109 interrupt-parent = <&mpic>;
111 ranges = <0x0 0x0 0xff800000 0x00800000
112 0x1 0x0 0xff000000 0x00800000
113 0x2 0x0 0xf8000000 0x00008000>;
116 #address-cells = <1>;
118 compatible = "cfi-flash";
119 reg = <0x0 0x0 0x00800000>;
125 #address-cells = <1>;
127 compatible = "cfi-flash";
128 reg = <0x1 0x0 0x00800000>;
134 #address-cells = <1>;
136 compatible = "dallas,ds1553";
137 reg = <0x2 0x0 0x00008000>;
144 #address-cells = <1>;
147 compatible = "simple-bus";
148 ranges = <0x0 0xe0000000 0x100000>;
152 compatible = "fsl,ecm-law";
158 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
159 reg = <0x1000 0x1000>;
161 interrupt-parent = <&mpic>;
164 memory-controller@2000 {
165 compatible = "fsl,8555-memory-controller";
166 reg = <0x2000 0x1000>;
167 interrupt-parent = <&mpic>;
171 L2: l2-cache-controller@20000 {
172 compatible = "fsl,8555-l2-cache-controller";
173 reg = <0x20000 0x1000>;
174 cache-line-size = <32>; // 32 bytes
175 cache-size = <0x40000>; // L2, 256K
176 interrupt-parent = <&mpic>;
181 #address-cells = <1>;
184 compatible = "fsl-i2c";
185 reg = <0x3000 0x100>;
187 interrupt-parent = <&mpic>;
192 #address-cells = <1>;
194 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
196 ranges = <0x0 0x21100 0x200>;
199 compatible = "fsl,mpc8555-dma-channel",
200 "fsl,eloplus-dma-channel";
203 interrupt-parent = <&mpic>;
207 compatible = "fsl,mpc8555-dma-channel",
208 "fsl,eloplus-dma-channel";
211 interrupt-parent = <&mpic>;
215 compatible = "fsl,mpc8555-dma-channel",
216 "fsl,eloplus-dma-channel";
219 interrupt-parent = <&mpic>;
223 compatible = "fsl,mpc8555-dma-channel",
224 "fsl,eloplus-dma-channel";
227 interrupt-parent = <&mpic>;
232 enet0: ethernet@24000 {
233 #address-cells = <1>;
236 device_type = "network";
238 compatible = "gianfar";
239 reg = <0x24000 0x1000>;
240 ranges = <0x0 0x24000 0x1000>;
241 local-mac-address = [ 00 00 00 00 00 00 ];
242 interrupts = <29 2 30 2 34 2>;
243 interrupt-parent = <&mpic>;
244 tbi-handle = <&tbi0>;
245 phy-handle = <&phy0>;
248 #address-cells = <1>;
250 compatible = "fsl,gianfar-mdio";
253 phy0: ethernet-phy@0 {
254 interrupt-parent = <&mpic>;
257 device_type = "ethernet-phy";
259 phy1: ethernet-phy@1 {
260 interrupt-parent = <&mpic>;
263 device_type = "ethernet-phy";
267 device_type = "tbi-phy";
272 enet1: ethernet@25000 {
273 #address-cells = <1>;
276 device_type = "network";
278 compatible = "gianfar";
279 reg = <0x25000 0x1000>;
280 ranges = <0x0 0x25000 0x1000>;
281 local-mac-address = [ 00 00 00 00 00 00 ];
282 interrupts = <35 2 36 2 40 2>;
283 interrupt-parent = <&mpic>;
284 tbi-handle = <&tbi1>;
285 phy-handle = <&phy1>;
288 #address-cells = <1>;
290 compatible = "fsl,gianfar-tbi";
295 device_type = "tbi-phy";
300 serial0: serial@4500 {
302 device_type = "serial";
303 compatible = "ns16550";
304 reg = <0x4500 0x100>; // reg base, size
305 clock-frequency = <0>; // should we fill in in uboot?
307 interrupt-parent = <&mpic>;
310 serial1: serial@4600 {
312 device_type = "serial";
313 compatible = "ns16550";
314 reg = <0x4600 0x100>; // reg base, size
315 clock-frequency = <0>; // should we fill in in uboot?
317 interrupt-parent = <&mpic>;
321 compatible = "fsl,sec2.0";
322 reg = <0x30000 0x10000>;
324 interrupt-parent = <&mpic>;
325 fsl,num-channels = <4>;
326 fsl,channel-fifo-len = <24>;
327 fsl,exec-units-mask = <0x7e>;
328 fsl,descriptor-types-mask = <0x01010ebf>;
332 interrupt-controller;
333 #address-cells = <0>;
334 #interrupt-cells = <2>;
335 reg = <0x40000 0x40000>;
336 compatible = "chrp,open-pic";
337 device_type = "open-pic";
341 #address-cells = <1>;
343 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
344 reg = <0x80000 0x20000>;
346 interrupt-parent = <&mpic>;
351 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
355 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
356 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
357 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
358 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
361 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
362 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
363 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
364 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
366 /* IDSEL 0x12 (Slot 1) */
367 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
368 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
369 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
370 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
372 /* IDSEL 0x13 (Slot 2) */
373 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
374 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
375 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
376 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
378 /* IDSEL 0x14 (Slot 3) */
379 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
380 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
381 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
382 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
384 /* IDSEL 0x15 (Slot 4) */
385 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
386 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
387 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
388 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
390 /* Bus 1 (Tundra Bridge) */
391 /* IDSEL 0x12 (ISA bridge) */
392 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
393 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
394 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
395 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
396 interrupt-parent = <&mpic>;
399 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
400 0x1000000 0x0 0x0 0xfee00000 0x0 0x00010000>;
401 clock-frequency = <66666666>;
402 #interrupt-cells = <1>;
404 #address-cells = <3>;
405 reg = <0xe0008000 0x1000>;
406 compatible = "fsl,mpc8540-pci";
410 interrupt-controller;
411 device_type = "interrupt-controller";
412 reg = <0x19000 0x0 0x0 0x0 0x1>;
413 #address-cells = <0>;
414 #interrupt-cells = <2>;
415 compatible = "chrp,iic";
417 interrupt-parent = <&pci0>;
422 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
426 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
427 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
428 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
429 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
430 interrupt-parent = <&mpic>;
433 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
434 0x1000000 0x0 0x0 0xfee10000 0x0 0x00010000>;
435 clock-frequency = <66666666>;
436 #interrupt-cells = <1>;
438 #address-cells = <3>;
439 reg = <0xe0009000 0x1000>;
440 compatible = "fsl,mpc8540-pci";