7 model = "ARM Versatile PB";
10 compatible = "arm,versatile-pb";
13 compatible = "simple-bus";
18 intc: interrupt-controller {
19 compatible = "arm,versatile-vic";
20 reg = <0x10140000 0x1000>;
23 #interrupt-cells = <1>;
26 sic: secondary-interrupt-controller {
27 compatible = "arm,versatile-sic";
28 reg = <0x10003000 0x28>;
31 #interrupt-cells = <1>;
35 compatible = "arm,pl011", "arm,primecell";
36 reg = <0x101f1000 0x1000>;
38 interrupt-parent = <&intc>;
39 clock-frequency = <3000000>;
44 compatible = "arm,pl011", "arm,primecell";
45 reg = <0x101f2000 0x1000>;
47 interrupt-parent = <&intc>;
48 clock-frequency = <3000000>;
53 compatible = "arm,pl011", "arm,primecell";
54 reg = <0x101f3000 0x1000>;
56 interrupt-parent = <&intc>;
57 clock-frequency = <3000000>;
62 compatible = "arm,sp804", "arm,primecell";
63 reg = <0x101e2000 0x40>;
65 interrupt-parent = <&intc>;
70 compatible = "versatile,pci";
74 0x42000000 0x02000000>;
78 compatible = "smsc,lan91c111";
79 reg = <0x10010000 0x10000>;
81 interrupt-parent = <&intc>;
85 compatible = "arm,pl110", "arm,primecell";
89 interrupt-parent = <&intc>;
93 * Cut corner here: we do not have proper interrupt
94 * controllers cascading so just hardwire SIC IRQ 3
98 compatible = "arm,pl050", "arm,primecell";
99 reg = <0x10006000 0x1000>;
100 interrupt-parent = <&intc>;
106 device_type = "memory";
107 reg = <0 0x08000000>; /* 128MB */