2 * Data structures and definitions for CAM Control Blocks (CCBs).
4 * SPDX-License-Identifier: BSD-2-Clause
6 * Copyright (c) 1997, 1998 Justin T. Gibbs.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification, immediately at the beginning of the file.
15 * 2. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef _CAM_CAM_CCB_H
32 #define _CAM_CAM_CCB_H 1
34 #include <sys/queue.h>
36 #include <sys/limits.h>
38 #include <sys/callout.h>
40 #include <cam/cam_debug.h>
41 #include <cam/scsi/scsi_all.h>
42 #include <cam/ata/ata_all.h>
43 #include <cam/nvme/nvme_all.h>
44 #include <cam/mmc/mmc_all.h>
46 /* General allocation length definitions for CCB structures */
47 #define IOCDBLEN CAM_MAX_CDBLEN /* Space for CDB bytes/pointer */
48 #define VUHBALEN 14 /* Vendor Unique HBA length */
49 #define SIM_IDLEN 16 /* ASCII string len for SIM ID */
50 #define HBA_IDLEN 16 /* ASCII string len for HBA ID */
51 #define DEV_IDLEN 16 /* ASCII string len for device names */
52 #define CCB_PERIPH_PRIV_SIZE 2 /* size of peripheral private area */
53 #define CCB_SIM_PRIV_SIZE 2 /* size of sim private area */
55 /* Struct definitions for CAM control blocks */
57 /* Common CCB header */
59 /* CCB memory allocation flags */
61 CAM_CCB_FROM_UMA = 0x00000001,/* CCB from a periph UMA zone */
66 CAM_CDB_POINTER = 0x00000001,/* The CDB field is a pointer */
67 CAM_unused1 = 0x00000002,
68 CAM_unused2 = 0x00000004,
69 CAM_NEGOTIATE = 0x00000008,/*
70 * Perform transport negotiation
73 CAM_DATA_ISPHYS = 0x00000010,/* Data type with physical addrs */
74 CAM_DIS_AUTOSENSE = 0x00000020,/* Disable autosense feature */
75 CAM_DIR_BOTH = 0x00000000,/* Data direction (00:IN/OUT) */
76 CAM_DIR_IN = 0x00000040,/* Data direction (01:DATA IN) */
77 CAM_DIR_OUT = 0x00000080,/* Data direction (10:DATA OUT) */
78 CAM_DIR_NONE = 0x000000C0,/* Data direction (11:no data) */
79 CAM_DIR_MASK = 0x000000C0,/* Data direction Mask */
80 CAM_DATA_VADDR = 0x00000000,/* Data type (000:Virtual) */
81 CAM_DATA_PADDR = 0x00000010,/* Data type (001:Physical) */
82 CAM_DATA_SG = 0x00040000,/* Data type (010:sglist) */
83 CAM_DATA_SG_PADDR = 0x00040010,/* Data type (011:sglist phys) */
84 CAM_DATA_BIO = 0x00200000,/* Data type (100:bio) */
85 CAM_DATA_MASK = 0x00240010,/* Data type mask */
86 CAM_unused3 = 0x00000100,
87 CAM_unused4 = 0x00000200,
88 CAM_DEV_QFRZDIS = 0x00000400,/* Disable DEV Q freezing */
89 CAM_DEV_QFREEZE = 0x00000800,/* Freeze DEV Q on execution */
90 CAM_HIGH_POWER = 0x00001000,/* Command takes a lot of power */
91 CAM_SENSE_PTR = 0x00002000,/* Sense data is a pointer */
92 CAM_SENSE_PHYS = 0x00004000,/* Sense pointer is physical addr*/
93 CAM_TAG_ACTION_VALID = 0x00008000,/* Use the tag action in this ccb*/
94 CAM_PASS_ERR_RECOVER = 0x00010000,/* Pass driver does err. recovery*/
95 CAM_DIS_DISCONNECT = 0x00020000,/* Disable disconnect */
96 CAM_unused5 = 0x00080000,
97 CAM_unused6 = 0x00100000,
98 CAM_CDB_PHYS = 0x00400000,/* CDB poiner is physical */
99 CAM_unused7 = 0x00800000,
101 /* Phase cognizant mode flags */
102 CAM_unused8 = 0x01000000,
103 CAM_unused9 = 0x02000000,
104 CAM_unused10 = 0x04000000,
105 CAM_unused11 = 0x08000000,
106 CAM_unused12 = 0x10000000,
107 CAM_unused13 = 0x20000000,
108 CAM_unused14 = 0x40000000,
110 /* Host target Mode flags */
111 CAM_SEND_SENSE = 0x08000000,/* Send sense data with status */
112 CAM_unused15 = 0x10000000,
113 CAM_unused16 = 0x20000000,
114 CAM_SEND_STATUS = 0x40000000,/* Send status after data phase */
116 CAM_UNLOCKED = 0x80000000 /* Call callback without lock. */
120 CAM_USER_DATA_ADDR = 0x00000002,/* Userspace data pointers */
121 CAM_SG_FORMAT_IOVEC = 0x00000004,/* iovec instead of busdma S/G*/
122 CAM_UNMAPPED_BUF = 0x00000008 /* use unmapped I/O */
125 /* XPT Opcodes for xpt_action */
127 /* Function code flags are bits greater than 0xff */
128 XPT_FC_QUEUED = 0x100,
129 /* Non-immediate function code */
130 XPT_FC_USER_CCB = 0x200,
131 XPT_FC_XPT_ONLY = 0x400,
132 /* Only for the transport layer device */
133 XPT_FC_DEV_QUEUED = 0x800 | XPT_FC_QUEUED,
134 /* Passes through the device queues */
135 /* Common function commands: 0x00->0x0F */
137 /* Execute Nothing */
138 XPT_SCSI_IO = 0x01 | XPT_FC_DEV_QUEUED,
139 /* Execute the requested I/O operation */
140 XPT_GDEV_TYPE = 0x02,
141 /* Get type information for specified device */
143 /* Get a list of peripheral devices */
145 /* Path routing inquiry */
147 /* Release a frozen device queue */
148 XPT_SASYNC_CB = 0x06,
149 /* Set Asynchronous Callback Parameters */
150 XPT_SDEV_TYPE = 0x07,
151 /* Set device type information */
152 XPT_SCAN_BUS = 0x08 | XPT_FC_QUEUED | XPT_FC_USER_CCB
154 /* (Re)Scan the SCSI Bus */
155 XPT_DEV_MATCH = 0x09 | XPT_FC_XPT_ONLY,
156 /* Get EDT entries matching the given pattern */
158 /* Turn on debugging for a bus, target or lun */
159 XPT_PATH_STATS = 0x0b,
160 /* Path statistics (error counts, etc.) */
161 XPT_GDEV_STATS = 0x0c,
162 /* Device statistics (error counts, etc.) */
163 XPT_DEV_ADVINFO = 0x0e,
164 /* Get/Set Device advanced information */
165 XPT_ASYNC = 0x0f | XPT_FC_QUEUED | XPT_FC_USER_CCB
167 /* Asynchronous event */
168 /* SCSI Control Functions: 0x10->0x1F */
170 /* Abort the specified CCB */
171 XPT_RESET_BUS = 0x11 | XPT_FC_XPT_ONLY,
172 /* Reset the specified SCSI bus */
173 XPT_RESET_DEV = 0x12 | XPT_FC_DEV_QUEUED,
174 /* Bus Device Reset the specified SCSI device */
176 /* Terminate the I/O process */
177 XPT_SCAN_LUN = 0x14 | XPT_FC_QUEUED | XPT_FC_USER_CCB
179 /* Scan Logical Unit */
180 XPT_GET_TRAN_SETTINGS = 0x15,
182 * Get default/user transfer settings
185 XPT_SET_TRAN_SETTINGS = 0x16,
187 * Set transfer rate/width
188 * negotiation settings
190 XPT_CALC_GEOMETRY = 0x17,
192 * Calculate the geometry parameters for
193 * a device give the sector size and
196 XPT_ATA_IO = 0x18 | XPT_FC_DEV_QUEUED,
197 /* Execute the requested ATA I/O operation */
199 XPT_GET_SIM_KNOB_OLD = 0x18, /* Compat only */
201 XPT_SET_SIM_KNOB = 0x19,
203 * Set SIM specific knob values.
206 XPT_GET_SIM_KNOB = 0x1a,
208 * Get SIM specific knob values.
211 XPT_SMP_IO = 0x1b | XPT_FC_DEV_QUEUED,
212 /* Serial Management Protocol */
214 XPT_NVME_IO = 0x1c | XPT_FC_DEV_QUEUED,
215 /* Execute the requested NVMe I/O operation */
217 XPT_MMC_IO = 0x1d | XPT_FC_DEV_QUEUED,
218 /* Placeholder for MMC / SD / SDIO I/O stuff */
220 XPT_SCAN_TGT = 0x1e | XPT_FC_QUEUED | XPT_FC_USER_CCB
224 XPT_NVME_ADMIN = 0x1f | XPT_FC_DEV_QUEUED,
225 /* Execute the requested NVMe Admin operation */
227 /* HBA engine commands 0x20->0x2F */
228 XPT_ENG_INQ = 0x20 | XPT_FC_XPT_ONLY,
229 /* HBA engine feature inquiry */
230 XPT_ENG_EXEC = 0x21 | XPT_FC_DEV_QUEUED,
231 /* HBA execute engine request */
233 /* Target mode commands: 0x30->0x3F */
235 /* Enable LUN as a target */
236 XPT_TARGET_IO = 0x31 | XPT_FC_DEV_QUEUED,
237 /* Execute target I/O request */
238 XPT_ACCEPT_TARGET_IO = 0x32 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
239 /* Accept Host Target Mode CDB */
240 XPT_CONT_TARGET_IO = 0x33 | XPT_FC_DEV_QUEUED,
241 /* Continue Host Target I/O Connection */
242 XPT_IMMED_NOTIFY = 0x34 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
243 /* Notify Host Target driver of event (obsolete) */
244 XPT_NOTIFY_ACK = 0x35,
245 /* Acknowledgement of event (obsolete) */
246 XPT_IMMEDIATE_NOTIFY = 0x36 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
247 /* Notify Host Target driver of event */
248 XPT_NOTIFY_ACKNOWLEDGE = 0x37 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
249 /* Acknowledgement of event */
250 XPT_REPROBE_LUN = 0x38 | XPT_FC_QUEUED | XPT_FC_USER_CCB,
251 /* Query device capacity and notify GEOM */
253 XPT_MMC_SET_TRAN_SETTINGS = 0x40 | XPT_FC_DEV_QUEUED,
254 XPT_MMC_GET_TRAN_SETTINGS = 0x41 | XPT_FC_DEV_QUEUED,
256 /* Vendor Unique codes: 0x80->0x8F */
260 #define XPT_FC_GROUP_MASK 0xF0
261 #define XPT_FC_GROUP(op) ((op) & XPT_FC_GROUP_MASK)
262 #define XPT_FC_GROUP_COMMON 0x00
263 #define XPT_FC_GROUP_SCSI_CONTROL 0x10
264 #define XPT_FC_GROUP_HBA_ENGINE 0x20
265 #define XPT_FC_GROUP_TMODE 0x30
266 #define XPT_FC_GROUP_VENDOR_UNIQUE 0x80
268 #define XPT_FC_IS_DEV_QUEUED(ccb) \
269 (((ccb)->ccb_h.func_code & XPT_FC_DEV_QUEUED) == XPT_FC_DEV_QUEUED)
270 #define XPT_FC_IS_QUEUED(ccb) \
271 (((ccb)->ccb_h.func_code & XPT_FC_QUEUED) != 0)
276 PROTO_SCSI, /* Small Computer System Interface */
277 PROTO_ATA, /* AT Attachment */
278 PROTO_ATAPI, /* AT Attachment Packetized Interface */
279 PROTO_SATAPM, /* SATA Port Multiplier */
280 PROTO_SEMB, /* SATA Enclosure Management Bridge */
281 PROTO_NVME, /* NVME */
282 PROTO_MMCSD, /* MMC, SD, SDIO */
288 XPORT_SPI, /* SCSI Parallel Interface */
289 XPORT_FC, /* Fiber Channel */
290 XPORT_SSA, /* Serial Storage Architecture */
291 XPORT_USB, /* Universal Serial Bus */
292 XPORT_PPB, /* Parallel Port Bus */
293 XPORT_ATA, /* AT Attachment */
294 XPORT_SAS, /* Serial Attached SCSI */
295 XPORT_SATA, /* Serial AT Attachment */
296 XPORT_ISCSI, /* iSCSI */
297 XPORT_SRP, /* SCSI RDMA Protocol */
298 XPORT_NVME, /* NVMe over PCIe */
299 XPORT_MMCSD, /* MMC, SD, SDIO card */
302 #define XPORT_IS_NVME(t) ((t) == XPORT_NVME)
303 #define XPORT_IS_ATA(t) ((t) == XPORT_ATA || (t) == XPORT_SATA)
304 #define XPORT_IS_SCSI(t) ((t) != XPORT_UNKNOWN && \
305 (t) != XPORT_UNSPECIFIED && \
306 !XPORT_IS_ATA(t) && !XPORT_IS_NVME(t))
307 #define XPORT_DEVSTAT_TYPE(t) (XPORT_IS_ATA(t) ? DEVSTAT_TYPE_IF_IDE : \
308 XPORT_IS_SCSI(t) ? DEVSTAT_TYPE_IF_SCSI : \
309 DEVSTAT_TYPE_IF_OTHER)
311 #define PROTO_VERSION_UNKNOWN (UINT_MAX - 1)
312 #define PROTO_VERSION_UNSPECIFIED UINT_MAX
313 #define XPORT_VERSION_UNKNOWN (UINT_MAX - 1)
314 #define XPORT_VERSION_UNSPECIFIED UINT_MAX
317 LIST_ENTRY(ccb_hdr) le;
318 SLIST_ENTRY(ccb_hdr) sle;
319 TAILQ_ENTRY(ccb_hdr) tqe;
320 STAILQ_ENTRY(ccb_hdr) stqe;
326 uint8_t bytes[sizeof(uintptr_t)];
330 ccb_priv_entry entries[CCB_PERIPH_PRIV_SIZE];
331 uint8_t bytes[CCB_PERIPH_PRIV_SIZE * sizeof(ccb_priv_entry)];
335 ccb_priv_entry entries[CCB_SIM_PRIV_SIZE];
336 uint8_t bytes[CCB_SIM_PRIV_SIZE * sizeof(ccb_priv_entry)];
340 struct timeval *etime;
342 uintptr_t periph_data;
346 cam_pinfo pinfo; /* Info for priority scheduling */
347 camq_entry xpt_links; /* For chaining in the XPT layer */
348 camq_entry sim_links; /* For chaining in the SIM layer */
349 camq_entry periph_links; /* For chaining in the type driver */
350 #if BYTE_ORDER == LITTLE_ENDIAN
351 uint16_t retry_count;
352 uint16_t alloc_flags; /* ccb_alloc_flags */
354 uint16_t alloc_flags; /* ccb_alloc_flags */
355 uint16_t retry_count;
357 void (*cbfcnp)(struct cam_periph *, union ccb *);
358 /* Callback on completion function */
359 xpt_opcode func_code; /* XPT function code */
360 uint32_t status; /* Status returned by CAM subsystem */
361 struct cam_path *path; /* Compiled path for this ccb */
362 path_id_t path_id; /* Path ID for the request */
363 target_id_t target_id; /* Target device ID */
364 lun_id_t target_lun; /* Target LUN number */
365 uint32_t flags; /* ccb_flags */
366 uint32_t xflags; /* Extended flags */
367 ccb_ppriv_area periph_priv;
368 ccb_spriv_area sim_priv;
370 uint32_t timeout; /* Hard timeout value in mseconds */
371 struct timeval softtimeout; /* Soft timeout value in sec + usec */
374 /* Get Device Information CCB */
376 struct ccb_hdr ccb_h;
378 struct scsi_inquiry_data inq_data;
379 struct ata_params ident_data;
380 uint8_t serial_num[252];
382 uint8_t serial_num_len;
386 /* Device Statistics CCB */
387 struct ccb_getdevstats {
388 struct ccb_hdr ccb_h;
389 int dev_openings; /* Space left for more work on device*/
390 int dev_active; /* Transactions running on the device */
391 int allocated; /* CCBs allocated for the device */
392 int queued; /* CCBs queued to be sent to the device */
394 * CCBs held by peripheral drivers
398 * Boundary conditions for number of
402 struct timeval last_reset; /* Time of last bus reset/loop init */
406 CAM_GDEVLIST_LAST_DEVICE,
407 CAM_GDEVLIST_LIST_CHANGED,
408 CAM_GDEVLIST_MORE_DEVS,
410 } ccb_getdevlist_status_e;
412 struct ccb_getdevlist {
413 struct ccb_hdr ccb_h;
414 char periph_name[DEV_IDLEN];
415 uint32_t unit_number;
416 unsigned int generation;
418 ccb_getdevlist_status_e status;
422 PERIPH_MATCH_ANY = 0x000,
423 PERIPH_MATCH_PATH = 0x001,
424 PERIPH_MATCH_TARGET = 0x002,
425 PERIPH_MATCH_LUN = 0x004,
426 PERIPH_MATCH_NAME = 0x008,
427 PERIPH_MATCH_UNIT = 0x010,
428 } periph_pattern_flags;
430 struct periph_match_pattern {
431 char periph_name[DEV_IDLEN];
432 uint32_t unit_number;
434 target_id_t target_id;
436 periph_pattern_flags flags;
440 DEV_MATCH_ANY = 0x000,
441 DEV_MATCH_PATH = 0x001,
442 DEV_MATCH_TARGET = 0x002,
443 DEV_MATCH_LUN = 0x004,
444 DEV_MATCH_INQUIRY = 0x008,
445 DEV_MATCH_DEVID = 0x010,
448 struct device_id_match_pattern {
453 struct device_match_pattern {
455 target_id_t target_id;
457 dev_pattern_flags flags;
459 struct scsi_static_inquiry_pattern inq_pat;
460 struct device_id_match_pattern devid_pat;
465 BUS_MATCH_ANY = 0x000,
466 BUS_MATCH_PATH = 0x001,
467 BUS_MATCH_NAME = 0x002,
468 BUS_MATCH_UNIT = 0x004,
469 BUS_MATCH_BUS_ID = 0x008,
472 struct bus_match_pattern {
474 char dev_name[DEV_IDLEN];
475 uint32_t unit_number;
477 bus_pattern_flags flags;
480 union match_pattern {
481 struct periph_match_pattern periph_pattern;
482 struct device_match_pattern device_pattern;
483 struct bus_match_pattern bus_pattern;
492 struct dev_match_pattern {
494 union match_pattern pattern;
497 struct periph_match_result {
498 char periph_name[DEV_IDLEN];
499 uint32_t unit_number;
501 target_id_t target_id;
506 DEV_RESULT_NOFLAG = 0x00,
507 DEV_RESULT_UNCONFIGURED = 0x01
510 struct device_match_result {
512 target_id_t target_id;
515 struct scsi_inquiry_data inq_data;
516 struct ata_params ident_data;
517 dev_result_flags flags;
520 struct bus_match_result {
522 char dev_name[DEV_IDLEN];
523 uint32_t unit_number;
528 struct periph_match_result periph_result;
529 struct device_match_result device_result;
530 struct bus_match_result bus_result;
533 struct dev_match_result {
535 union match_result result;
541 CAM_DEV_MATCH_LIST_CHANGED,
542 CAM_DEV_MATCH_SIZE_ERROR,
544 } ccb_dev_match_status;
547 CAM_DEV_POS_NONE = 0x000,
548 CAM_DEV_POS_BUS = 0x001,
549 CAM_DEV_POS_TARGET = 0x002,
550 CAM_DEV_POS_DEVICE = 0x004,
551 CAM_DEV_POS_PERIPH = 0x008,
552 CAM_DEV_POS_PDPTR = 0x010,
553 CAM_DEV_POS_TYPEMASK = 0xf00,
554 CAM_DEV_POS_EDT = 0x100,
555 CAM_DEV_POS_PDRV = 0x200
558 struct ccb_dm_cookie {
566 struct ccb_dev_position {
567 u_int generations[4];
568 #define CAM_BUS_GENERATION 0x00
569 #define CAM_TARGET_GENERATION 0x01
570 #define CAM_DEV_GENERATION 0x02
571 #define CAM_PERIPH_GENERATION 0x03
572 dev_pos_type position_type;
573 struct ccb_dm_cookie cookie;
576 struct ccb_dev_match {
577 struct ccb_hdr ccb_h;
578 ccb_dev_match_status status;
579 uint32_t num_patterns;
580 uint32_t pattern_buf_len;
581 struct dev_match_pattern *patterns;
582 uint32_t num_matches;
583 uint32_t match_buf_len;
584 struct dev_match_result *matches;
585 struct ccb_dev_position pos;
589 * Definitions for the path inquiry CCB fields.
591 #define CAM_VERSION 0x1a /* Hex value for current version */
594 PI_MDP_ABLE = 0x80, /* Supports MDP message */
595 PI_WIDE_32 = 0x40, /* Supports 32 bit wide SCSI */
596 PI_WIDE_16 = 0x20, /* Supports 16 bit wide SCSI */
597 PI_SDTR_ABLE = 0x10, /* Supports SDTR message */
598 PI_LINKED_CDB = 0x08, /* Supports linked CDBs */
599 PI_SATAPM = 0x04, /* Supports SATA PM */
600 PI_TAG_ABLE = 0x02, /* Supports tag queue messages */
601 PI_SOFT_RST = 0x01 /* Supports soft reset alternative */
605 PIT_PROCESSOR = 0x80, /* Target mode processor mode */
606 PIT_PHASE = 0x40, /* Target mode phase cog. mode */
607 PIT_DISCONNECT = 0x20, /* Disconnects supported in target mode */
608 PIT_TERM_IO = 0x10, /* Terminate I/O message supported in TM */
609 PIT_GRP_6 = 0x08, /* Group 6 commands supported */
610 PIT_GRP_7 = 0x04 /* Group 7 commands supported */
614 PIM_ATA_EXT = 0x200,/* ATA requests can understand ata_ext requests */
615 PIM_EXTLUNS = 0x100,/* 64bit extended LUNs supported */
616 PIM_SCANHILO = 0x80, /* Bus scans from high ID to low ID */
617 PIM_NOREMOVE = 0x40, /* Removeable devices not included in scan */
618 PIM_NOINITIATOR = 0x20, /* Initiator role not supported. */
619 PIM_NOBUSRESET = 0x10, /* User has disabled initial BUS RESET */
620 PIM_NO_6_BYTE = 0x08, /* Do not send 6-byte commands */
621 PIM_SEQSCAN = 0x04, /* Do bus scans sequentially, not in parallel */
623 PIM_NOSCAN = 0x01 /* SIM does its own scanning */
626 /* Path Inquiry CCB */
627 struct ccb_pathinq_settings_spi {
631 struct ccb_pathinq_settings_fc {
632 uint64_t wwnn; /* world wide node name */
633 uint64_t wwpn; /* world wide port name */
634 uint32_t port; /* 24 bit port id, if known */
635 uint32_t bitrate; /* Mbps */
638 struct ccb_pathinq_settings_sas {
639 uint32_t bitrate; /* Mbps */
642 #define NVME_DEV_NAME_LEN 52
643 struct ccb_pathinq_settings_nvme {
644 uint32_t nsid; /* Namespace ID for this path */
650 char dev_name[NVME_DEV_NAME_LEN]; /* nvme controller dev name for this device */
652 _Static_assert(sizeof(struct ccb_pathinq_settings_nvme) == 64,
653 "ccb_pathinq_settings_nvme too big");
655 #define PATHINQ_SETTINGS_SIZE 128
658 struct ccb_hdr ccb_h;
659 uint8_t version_num; /* Version number for the SIM/HBA */
660 uint8_t hba_inquiry; /* Mimic of INQ byte 7 for the HBA */
661 uint16_t target_sprt; /* Flags for target mode support */
662 uint32_t hba_misc; /* Misc HBA features */
663 uint16_t hba_eng_cnt; /* HBA engine count */
664 /* Vendor Unique capabilities */
665 uint8_t vuhba_flags[VUHBALEN];
666 uint32_t max_target; /* Maximum supported Target */
667 uint32_t max_lun; /* Maximum supported Lun */
668 uint32_t async_flags; /* Installed Async handlers */
669 path_id_t hpath_id; /* Highest Path ID in the subsystem */
670 target_id_t initiator_id; /* ID of the HBA on the SCSI bus */
671 char sim_vid[SIM_IDLEN]; /* Vendor ID of the SIM */
672 char hba_vid[HBA_IDLEN]; /* Vendor ID of the HBA */
673 char dev_name[DEV_IDLEN];/* Device name for SIM */
674 uint32_t unit_number; /* Unit number for SIM */
675 uint32_t bus_id; /* Bus ID for SIM */
676 uint32_t base_transfer_speed;/* Base bus speed in KB/sec */
678 u_int protocol_version;
680 u_int transport_version;
682 struct ccb_pathinq_settings_spi spi;
683 struct ccb_pathinq_settings_fc fc;
684 struct ccb_pathinq_settings_sas sas;
685 struct ccb_pathinq_settings_nvme nvme;
686 char ccb_pathinq_settings_opaque[PATHINQ_SETTINGS_SIZE];
688 u_int maxio; /* Max supported I/O size, in bytes. */
689 uint16_t hba_vendor; /* HBA vendor ID */
690 uint16_t hba_device; /* HBA device ID */
691 uint16_t hba_subvendor; /* HBA subvendor ID */
692 uint16_t hba_subdevice; /* HBA subdevice ID */
695 /* Path Statistics CCB */
696 struct ccb_pathstats {
697 struct ccb_hdr ccb_h;
698 struct timeval last_reset; /* Time of last bus reset/loop init */
702 SMP_FLAG_NONE = 0x00,
703 SMP_FLAG_REQ_SG = 0x01,
704 SMP_FLAG_RSP_SG = 0x02
705 } ccb_smp_pass_flags;
708 * Serial Management Protocol CCB
709 * XXX Currently the semantics for this CCB are that it is executed either
710 * by the addressed device, or that device's parent (i.e. an expander for
711 * any device on an expander) if the addressed device doesn't support SMP.
712 * Later, once we have the ability to probe SMP-only devices and put them
713 * in CAM's topology, the CCB will only be executed by the addressed device
717 struct ccb_hdr ccb_h;
718 uint8_t *smp_request;
720 uint16_t smp_request_sglist_cnt;
721 uint8_t *smp_response;
722 int smp_response_len;
723 uint16_t smp_response_sglist_cnt;
724 ccb_smp_pass_flags flags;
728 uint8_t *sense_ptr; /*
730 * for sense information
732 /* Storage Area for sense information */
733 struct scsi_sense_data sense_buf;
737 uint8_t *cdb_ptr; /* Pointer to the CDB bytes to send */
738 /* Area for the CDB send */
739 uint8_t cdb_bytes[IOCDBLEN];
743 * SCSI I/O Request CCB used for the XPT_SCSI_IO and XPT_CONT_TARGET_IO
747 struct ccb_hdr ccb_h;
748 union ccb *next_ccb; /* Ptr for next CCB for action */
749 uint8_t *req_map; /* Ptr to mapping info */
750 uint8_t *data_ptr; /* Ptr to the data buf/SG list */
751 uint32_t dxfer_len; /* Data transfer length */
752 /* Autosense storage */
753 struct scsi_sense_data sense_data;
754 uint8_t sense_len; /* Number of bytes to autosense */
755 uint8_t cdb_len; /* Number of bytes for the CDB */
756 uint16_t sglist_cnt; /* Number of SG list entries */
757 uint8_t scsi_status; /* Returned SCSI status */
758 uint8_t sense_resid; /* Autosense resid length: 2's comp */
759 uint32_t resid; /* Transfer residual length: 2's comp */
760 cdb_t cdb_io; /* Union for CDB bytes/pointer */
761 uint8_t *msg_ptr; /* Pointer to the message buffer */
762 uint16_t msg_len; /* Number of bytes for the Message */
763 uint8_t tag_action; /* What to do for tag queueing */
765 * The tag action should be either the define below (to send a
766 * non-tagged transaction) or one of the defined scsi tag messages
767 * from scsi_message.h.
769 #define CAM_TAG_ACTION_NONE 0x00
770 uint8_t priority; /* Command priority for SIMPLE tag */
771 u_int tag_id; /* tag id from initator (target mode) */
772 u_int init_id; /* initiator id of who selected */
773 #if defined(BUF_TRACKING) || defined(FULL_BUF_TRACKING)
774 struct bio *bio; /* Associated bio */
778 static __inline uint8_t *
779 scsiio_cdb_ptr(struct ccb_scsiio *ccb)
781 return ((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
782 ccb->cdb_io.cdb_ptr : ccb->cdb_io.cdb_bytes);
786 * ATA I/O Request CCB used for the XPT_ATA_IO function code.
789 struct ccb_hdr ccb_h;
790 union ccb *next_ccb; /* Ptr for next CCB for action */
791 struct ata_cmd cmd; /* ATA command register set */
792 struct ata_res res; /* ATA result register set */
793 uint8_t *data_ptr; /* Ptr to the data buf/SG list */
794 uint32_t dxfer_len; /* Data transfer length */
795 uint32_t resid; /* Transfer residual length: 2's comp */
796 uint8_t ata_flags; /* Flags for the rest of the buffer */
797 #define ATA_FLAG_AUX 0x1
798 #define ATA_FLAG_ICC 0x2
799 uint8_t icc; /* Isochronous Command Completion */
805 * MMC I/O Request CCB used for the XPT_MMC_IO function code.
808 struct ccb_hdr ccb_h;
809 union ccb *next_ccb; /* Ptr for next CCB for action */
810 struct mmc_command cmd;
811 struct mmc_command stop;
814 struct ccb_accept_tio {
815 struct ccb_hdr ccb_h;
816 cdb_t cdb_io; /* Union for CDB bytes/pointer */
817 uint8_t cdb_len; /* Number of bytes for the CDB */
818 uint8_t tag_action; /* What to do for tag queueing */
819 uint8_t sense_len; /* Number of bytes of Sense Data */
820 uint8_t priority; /* Command priority for SIMPLE tag */
821 u_int tag_id; /* tag id from initator (target mode) */
822 u_int init_id; /* initiator id of who selected */
823 struct scsi_sense_data sense_data;
826 static __inline uint8_t *
827 atio_cdb_ptr(struct ccb_accept_tio *ccb)
829 return ((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
830 ccb->cdb_io.cdb_ptr : ccb->cdb_io.cdb_bytes);
833 /* Release SIM Queue */
835 struct ccb_hdr ccb_h;
836 uint32_t release_flags;
837 #define RELSIM_ADJUST_OPENINGS 0x01
838 #define RELSIM_RELEASE_AFTER_TIMEOUT 0x02
839 #define RELSIM_RELEASE_AFTER_CMDCMPLT 0x04
840 #define RELSIM_RELEASE_AFTER_QEMPTY 0x08
842 uint32_t release_timeout; /* Abstract argument. */
843 uint32_t qfrozen_cnt;
847 * NVMe I/O Request CCB used for the XPT_NVME_IO and XPT_NVME_ADMIN function codes.
850 struct ccb_hdr ccb_h;
851 union ccb *next_ccb; /* Ptr for next CCB for action */
852 struct nvme_command cmd; /* NVME command, per NVME standard */
853 struct nvme_completion cpl; /* NVME completion, per NVME standard */
854 uint8_t *data_ptr; /* Ptr to the data buf/SG list */
855 uint32_t dxfer_len; /* Data transfer length */
856 uint16_t sglist_cnt; /* Number of SG list entries */
857 uint16_t unused; /* padding for removed uint32_t */
861 * Definitions for the asynchronous callback CCB fields.
864 AC_UNIT_ATTENTION = 0x4000,/* Device reported UNIT ATTENTION */
865 AC_ADVINFO_CHANGED = 0x2000,/* Advance info might have changes */
866 AC_CONTRACT = 0x1000,/* A contractual callback */
867 AC_GETDEV_CHANGED = 0x800,/* Getdev info might have changed */
868 AC_INQ_CHANGED = 0x400,/* Inquiry info might have changed */
869 AC_TRANSFER_NEG = 0x200,/* New transfer settings in effect */
870 AC_LOST_DEVICE = 0x100,/* A device went away */
871 AC_FOUND_DEVICE = 0x080,/* A new device was found */
872 AC_PATH_DEREGISTERED = 0x040,/* A path has de-registered */
873 AC_PATH_REGISTERED = 0x020,/* A new path has been registered */
874 AC_SENT_BDR = 0x010,/* A BDR message was sent to target */
875 AC_SCSI_AEN = 0x008,/* A SCSI AEN has been received */
876 AC_UNSOL_RESEL = 0x002,/* Unsolicited reselection occurred */
877 AC_BUS_RESET = 0x001 /* A SCSI bus reset occurred */
880 typedef void ac_callback_t (void *softc, uint32_t code,
881 struct cam_path *path, void *args);
884 * Generic Asynchronous callbacks.
886 * Generic arguments passed bac which are then interpreted between a per-system
889 #define AC_CONTRACT_DATA_MAX (128 - sizeof (uint64_t))
891 uint64_t contract_number;
892 uint8_t contract_data[AC_CONTRACT_DATA_MAX];
895 #define AC_CONTRACT_DEV_CHG 1
896 struct ac_device_changed {
903 /* Set Asynchronous Callback CCB */
904 struct ccb_setasync {
905 struct ccb_hdr ccb_h;
906 uint32_t event_enable; /* Async Event enables */
907 ac_callback_t *callback;
911 /* Set Device Type CCB */
913 struct ccb_hdr ccb_h;
914 uint8_t dev_type; /* Value for dev type field in EDT */
917 /* SCSI Control Functions */
919 /* Abort XPT request CCB */
921 struct ccb_hdr ccb_h;
922 union ccb *abort_ccb; /* Pointer to CCB to abort */
925 /* Reset SCSI Bus CCB */
926 struct ccb_resetbus {
927 struct ccb_hdr ccb_h;
930 /* Reset SCSI Device CCB */
931 struct ccb_resetdev {
932 struct ccb_hdr ccb_h;
935 /* Terminate I/O Process Request CCB */
937 struct ccb_hdr ccb_h;
938 union ccb *termio_ccb; /* Pointer to CCB to terminate */
942 CTS_TYPE_CURRENT_SETTINGS,
943 CTS_TYPE_USER_SETTINGS
946 struct ccb_trans_settings_scsi
948 u_int valid; /* Which fields to honor */
949 #define CTS_SCSI_VALID_TQ 0x01
951 #define CTS_SCSI_FLAGS_TAG_ENB 0x01
954 struct ccb_trans_settings_ata
956 u_int valid; /* Which fields to honor */
957 #define CTS_ATA_VALID_TQ 0x01
959 #define CTS_ATA_FLAGS_TAG_ENB 0x01
962 struct ccb_trans_settings_spi
964 u_int valid; /* Which fields to honor */
965 #define CTS_SPI_VALID_SYNC_RATE 0x01
966 #define CTS_SPI_VALID_SYNC_OFFSET 0x02
967 #define CTS_SPI_VALID_BUS_WIDTH 0x04
968 #define CTS_SPI_VALID_DISC 0x08
969 #define CTS_SPI_VALID_PPR_OPTIONS 0x10
971 #define CTS_SPI_FLAGS_DISC_ENB 0x01
978 struct ccb_trans_settings_fc {
979 u_int valid; /* Which fields to honor */
980 #define CTS_FC_VALID_WWNN 0x8000
981 #define CTS_FC_VALID_WWPN 0x4000
982 #define CTS_FC_VALID_PORT 0x2000
983 #define CTS_FC_VALID_SPEED 0x1000
984 uint64_t wwnn; /* world wide node name */
985 uint64_t wwpn; /* world wide port name */
986 uint32_t port; /* 24 bit port id, if known */
987 uint32_t bitrate; /* Mbps */
990 struct ccb_trans_settings_sas {
991 u_int valid; /* Which fields to honor */
992 #define CTS_SAS_VALID_SPEED 0x1000
993 uint32_t bitrate; /* Mbps */
996 struct ccb_trans_settings_pata {
997 u_int valid; /* Which fields to honor */
998 #define CTS_ATA_VALID_MODE 0x01
999 #define CTS_ATA_VALID_BYTECOUNT 0x02
1000 #define CTS_ATA_VALID_ATAPI 0x20
1001 #define CTS_ATA_VALID_CAPS 0x40
1002 int mode; /* Mode */
1003 u_int bytecount; /* Length of PIO transaction */
1004 u_int atapi; /* Length of ATAPI CDB */
1005 u_int caps; /* Device and host SATA caps. */
1006 #define CTS_ATA_CAPS_H 0x0000ffff
1007 #define CTS_ATA_CAPS_H_DMA48 0x00000001 /* 48-bit DMA */
1008 #define CTS_ATA_CAPS_D 0xffff0000
1011 struct ccb_trans_settings_sata {
1012 u_int valid; /* Which fields to honor */
1013 #define CTS_SATA_VALID_MODE 0x01
1014 #define CTS_SATA_VALID_BYTECOUNT 0x02
1015 #define CTS_SATA_VALID_REVISION 0x04
1016 #define CTS_SATA_VALID_PM 0x08
1017 #define CTS_SATA_VALID_TAGS 0x10
1018 #define CTS_SATA_VALID_ATAPI 0x20
1019 #define CTS_SATA_VALID_CAPS 0x40
1020 int mode; /* Legacy PATA mode */
1021 u_int bytecount; /* Length of PIO transaction */
1022 int revision; /* SATA revision */
1023 u_int pm_present; /* PM is present (XPT->SIM) */
1024 u_int tags; /* Number of allowed tags */
1025 u_int atapi; /* Length of ATAPI CDB */
1026 u_int caps; /* Device and host SATA caps. */
1027 #define CTS_SATA_CAPS_H 0x0000ffff
1028 #define CTS_SATA_CAPS_H_PMREQ 0x00000001
1029 #define CTS_SATA_CAPS_H_APST 0x00000002
1030 #define CTS_SATA_CAPS_H_DMAAA 0x00000010 /* Auto-activation */
1031 #define CTS_SATA_CAPS_H_AN 0x00000020 /* Async. notification */
1032 #define CTS_SATA_CAPS_D 0xffff0000
1033 #define CTS_SATA_CAPS_D_PMREQ 0x00010000
1034 #define CTS_SATA_CAPS_D_APST 0x00020000
1037 struct ccb_trans_settings_nvme
1039 u_int valid; /* Which fields to honor */
1040 #define CTS_NVME_VALID_SPEC 0x01
1041 #define CTS_NVME_VALID_CAPS 0x02
1042 #define CTS_NVME_VALID_LINK 0x04
1043 uint32_t spec; /* NVMe spec implemented -- same as vs register */
1044 uint32_t max_xfer; /* Max transfer size (0 -> unlimited */
1046 uint8_t lanes; /* Number of PCIe lanes */
1047 uint8_t speed; /* PCIe generation for each lane */
1048 uint8_t max_lanes; /* Number of PCIe lanes */
1049 uint8_t max_speed; /* PCIe generation for each lane */
1052 #include <cam/mmc/mmc_bus.h>
1053 struct ccb_trans_settings_mmc {
1055 #define MMC_CLK (1 << 1)
1056 #define MMC_VDD (1 << 2)
1057 #define MMC_CS (1 << 3)
1058 #define MMC_BW (1 << 4)
1059 #define MMC_PM (1 << 5)
1060 #define MMC_BT (1 << 6)
1061 #define MMC_BM (1 << 7)
1062 #define MMC_VCCQ (1 << 8)
1064 /* The folowing is used only for GET_TRAN_SETTINGS */
1068 /* Copied from sys/dev/mmc/bridge.h */
1069 #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can do 4-bit data transfers */
1070 #define MMC_CAP_8_BIT_DATA (1 << 1) /* Can do 8-bit data transfers */
1071 #define MMC_CAP_HSPEED (1 << 2) /* Can do High Speed transfers */
1072 #define MMC_CAP_BOOT_NOACC (1 << 4) /* Cannot access boot partitions */
1073 #define MMC_CAP_WAIT_WHILE_BUSY (1 << 5) /* Host waits for busy responses */
1074 #define MMC_CAP_UHS_SDR12 (1 << 6) /* Can do UHS SDR12 */
1075 #define MMC_CAP_UHS_SDR25 (1 << 7) /* Can do UHS SDR25 */
1076 #define MMC_CAP_UHS_SDR50 (1 << 8) /* Can do UHS SDR50 */
1077 #define MMC_CAP_UHS_SDR104 (1 << 9) /* Can do UHS SDR104 */
1078 #define MMC_CAP_UHS_DDR50 (1 << 10) /* Can do UHS DDR50 */
1079 #define MMC_CAP_MMC_DDR52_120 (1 << 11) /* Can do eMMC DDR52 at 1.2 V */
1080 #define MMC_CAP_MMC_DDR52_180 (1 << 12) /* Can do eMMC DDR52 at 1.8 V */
1081 #define MMC_CAP_MMC_DDR52 (MMC_CAP_MMC_DDR52_120 | MMC_CAP_MMC_DDR52_180)
1082 #define MMC_CAP_MMC_HS200_120 (1 << 13) /* Can do eMMC HS200 at 1.2 V */
1083 #define MMC_CAP_MMC_HS200_180 (1 << 14) /* Can do eMMC HS200 at 1.8 V */
1084 #define MMC_CAP_MMC_HS200 (MMC_CAP_MMC_HS200_120| MMC_CAP_MMC_HS200_180)
1085 #define MMC_CAP_MMC_HS400_120 (1 << 15) /* Can do eMMC HS400 at 1.2 V */
1086 #define MMC_CAP_MMC_HS400_180 (1 << 16) /* Can do eMMC HS400 at 1.8 V */
1087 #define MMC_CAP_MMC_HS400 (MMC_CAP_MMC_HS400_120 | MMC_CAP_MMC_HS400_180)
1088 #define MMC_CAP_MMC_HSX00_120 (MMC_CAP_MMC_HS200_120 | MMC_CAP_MMC_HS400_120)
1089 #define MMC_CAP_MMC_ENH_STROBE (1 << 17) /* Can do eMMC Enhanced Strobe */
1090 #define MMC_CAP_SIGNALING_120 (1 << 18) /* Can do signaling at 1.2 V */
1091 #define MMC_CAP_SIGNALING_180 (1 << 19) /* Can do signaling at 1.8 V */
1092 #define MMC_CAP_SIGNALING_330 (1 << 20) /* Can do signaling at 3.3 V */
1093 #define MMC_CAP_DRIVER_TYPE_A (1 << 21) /* Can do Driver Type A */
1094 #define MMC_CAP_DRIVER_TYPE_C (1 << 22) /* Can do Driver Type C */
1095 #define MMC_CAP_DRIVER_TYPE_D (1 << 23) /* Can do Driver Type D */
1098 uint32_t host_max_data;
1101 /* Get/Set transfer rate/width/disconnection/tag queueing settings */
1102 struct ccb_trans_settings {
1103 struct ccb_hdr ccb_h;
1104 cts_type type; /* Current or User settings */
1106 u_int protocol_version;
1107 cam_xport transport;
1108 u_int transport_version;
1110 u_int valid; /* Which fields to honor */
1111 struct ccb_trans_settings_ata ata;
1112 struct ccb_trans_settings_scsi scsi;
1113 struct ccb_trans_settings_nvme nvme;
1114 struct ccb_trans_settings_mmc mmc;
1117 u_int valid; /* Which fields to honor */
1118 struct ccb_trans_settings_spi spi;
1119 struct ccb_trans_settings_fc fc;
1120 struct ccb_trans_settings_sas sas;
1121 struct ccb_trans_settings_pata ata;
1122 struct ccb_trans_settings_sata sata;
1123 struct ccb_trans_settings_nvme nvme;
1128 * Calculate the geometry parameters for a device
1129 * give the block size and volume size in blocks.
1131 struct ccb_calc_geometry {
1132 struct ccb_hdr ccb_h;
1133 uint32_t block_size;
1134 uint64_t volume_size;
1137 uint8_t secs_per_track;
1141 * Set or get SIM (and transport) specific knobs
1144 #define KNOB_VALID_ADDRESS 0x1
1145 #define KNOB_VALID_ROLE 0x2
1147 #define KNOB_ROLE_NONE 0x0
1148 #define KNOB_ROLE_INITIATOR 0x1
1149 #define KNOB_ROLE_TARGET 0x2
1150 #define KNOB_ROLE_BOTH 0x3
1152 struct ccb_sim_knob_settings_spi {
1158 struct ccb_sim_knob_settings_fc {
1160 uint64_t wwnn; /* world wide node name */
1161 uint64_t wwpn; /* world wide port name */
1165 struct ccb_sim_knob_settings_sas {
1167 uint64_t wwnn; /* world wide node name */
1170 #define KNOB_SETTINGS_SIZE 128
1172 struct ccb_sim_knob {
1173 struct ccb_hdr ccb_h;
1175 u_int valid; /* Which fields to honor */
1176 struct ccb_sim_knob_settings_spi spi;
1177 struct ccb_sim_knob_settings_fc fc;
1178 struct ccb_sim_knob_settings_sas sas;
1179 char pad[KNOB_SETTINGS_SIZE];
1184 * Rescan the given bus, or bus/target/lun
1187 struct ccb_hdr ccb_h;
1192 * Turn on debugging for the given bus, bus/target, or bus/target/lun.
1195 struct ccb_hdr ccb_h;
1196 cam_debug_flags flags;
1199 /* Target mode structures. */
1202 struct ccb_hdr ccb_h;
1203 uint16_t grp6_len; /* Group 6 VU CDB length */
1204 uint16_t grp7_len; /* Group 7 VU CDB length */
1208 /* old, barely used immediate notify, binary compatibility */
1209 struct ccb_immed_notify {
1210 struct ccb_hdr ccb_h;
1211 struct scsi_sense_data sense_data;
1212 uint8_t sense_len; /* Number of bytes in sense buffer */
1213 uint8_t initiator_id; /* Id of initiator that selected */
1214 uint8_t message_args[7]; /* Message Arguments */
1217 struct ccb_notify_ack {
1218 struct ccb_hdr ccb_h;
1219 uint16_t seq_id; /* Sequence identifier */
1220 uint8_t event; /* Event flags */
1223 struct ccb_immediate_notify {
1224 struct ccb_hdr ccb_h;
1225 u_int tag_id; /* Tag for immediate notify */
1226 u_int seq_id; /* Tag for target of notify */
1227 u_int initiator_id; /* Initiator Identifier */
1228 u_int arg; /* Function specific */
1231 struct ccb_notify_acknowledge {
1232 struct ccb_hdr ccb_h;
1233 u_int tag_id; /* Tag for immediate notify */
1234 u_int seq_id; /* Tar for target of notify */
1235 u_int initiator_id; /* Initiator Identifier */
1236 u_int arg; /* Response information */
1238 * Lower byte of arg is one of RESPONSE CODE values defined below
1239 * (subset of response codes from SPL-4 and FCP-4 specifications),
1240 * upper 3 bytes is code-specific ADDITIONAL RESPONSE INFORMATION.
1242 #define CAM_RSP_TMF_COMPLETE 0x00
1243 #define CAM_RSP_TMF_REJECTED 0x04
1244 #define CAM_RSP_TMF_FAILED 0x05
1245 #define CAM_RSP_TMF_SUCCEEDED 0x08
1246 #define CAM_RSP_TMF_INCORRECT_LUN 0x09
1249 /* HBA engine structures. */
1252 EIT_BUFFER, /* Engine type: buffer memory */
1253 EIT_LOSSLESS, /* Engine type: lossless compression */
1254 EIT_LOSSY, /* Engine type: lossy compression */
1255 EIT_ENCRYPT /* Engine type: encryption */
1259 EAD_VUNIQUE, /* Engine algorithm ID: vendor unique */
1260 EAD_LZ1V1, /* Engine algorithm ID: LZ1 var.1 */
1261 EAD_LZ2V1, /* Engine algorithm ID: LZ2 var.1 */
1262 EAD_LZ2V2 /* Engine algorithm ID: LZ2 var.2 */
1265 struct ccb_eng_inq {
1266 struct ccb_hdr ccb_h;
1267 uint16_t eng_num; /* The engine number for this inquiry */
1268 ei_type eng_type; /* Returned engine type */
1269 ei_algo eng_algo; /* Returned engine algorithm type */
1270 uint32_t eng_memeory; /* Returned engine memory size */
1273 struct ccb_eng_exec { /* This structure must match SCSIIO size */
1274 struct ccb_hdr ccb_h;
1275 uint8_t *pdrv_ptr; /* Ptr used by the peripheral driver */
1276 uint8_t *req_map; /* Ptr for mapping info on the req. */
1277 uint8_t *data_ptr; /* Pointer to the data buf/SG list */
1278 uint32_t dxfer_len; /* Data transfer length */
1279 uint8_t *engdata_ptr; /* Pointer to the engine buffer data */
1280 uint16_t sglist_cnt; /* Num of scatter gather list entries */
1281 uint32_t dmax_len; /* Destination data maximum length */
1282 uint32_t dest_len; /* Destination data length */
1283 int32_t src_resid; /* Source residual length: 2's comp */
1284 uint32_t timeout; /* Timeout value */
1285 uint16_t eng_num; /* Engine number for this request */
1286 uint16_t vu_flags; /* Vendor Unique flags */
1290 * Definitions for the timeout field in the SCSI I/O CCB.
1292 #define CAM_TIME_DEFAULT 0x00000000 /* Use SIM default value */
1293 #define CAM_TIME_INFINITY 0xFFFFFFFF /* Infinite timeout */
1295 #define CAM_SUCCESS 0 /* For signaling general success */
1297 #define XPT_CCB_INVALID -1 /* for signaling a bad CCB to free */
1300 * CCB for working with advanced device information. This operates in a fashion
1301 * similar to XPT_GDEV_TYPE. Specify the target in ccb_h, the buffer
1302 * type requested, and provide a buffer size/buffer to write to. If the
1303 * buffer is too small, provsiz will be larger than bufsiz.
1305 struct ccb_dev_advinfo {
1306 struct ccb_hdr ccb_h;
1308 #define CDAI_FLAG_NONE 0x0 /* No flags set */
1309 #define CDAI_FLAG_STORE 0x1 /* If set, action becomes store */
1310 uint32_t buftype; /* IN: Type of data being requested */
1311 /* NB: buftype is interpreted on a per-transport basis */
1312 #define CDAI_TYPE_SCSI_DEVID 1
1313 #define CDAI_TYPE_SERIAL_NUM 2
1314 #define CDAI_TYPE_PHYS_PATH 3
1315 #define CDAI_TYPE_RCAPLONG 4
1316 #define CDAI_TYPE_EXT_INQ 5
1317 #define CDAI_TYPE_NVME_CNTRL 6 /* NVMe Identify Controller data */
1318 #define CDAI_TYPE_NVME_NS 7 /* NVMe Identify Namespace data */
1319 #define CDAI_TYPE_MMC_PARAMS 8 /* MMC/SD ident */
1320 off_t bufsiz; /* IN: Size of external buffer */
1321 #define CAM_SCSI_DEVID_MAXLEN 65536 /* length in buffer is an uint16_t */
1322 off_t provsiz; /* OUT: Size required/used */
1323 uint8_t *buf; /* IN/OUT: Buffer for requested data */
1327 * CCB for sending async events
1330 struct ccb_hdr ccb_h;
1331 uint32_t async_code;
1332 off_t async_arg_size;
1333 void *async_arg_ptr;
1337 * Union of all CCB types for kernel space allocation. This union should
1338 * never be used for manipulating CCBs - its only use is for the allocation
1339 * and deallocation of raw CCB space and is the return type of xpt_ccb_alloc
1340 * and the argument to xpt_ccb_free.
1343 struct ccb_hdr ccb_h; /* For convenience */
1344 struct ccb_scsiio csio;
1345 struct ccb_getdev cgd;
1346 struct ccb_getdevlist cgdl;
1347 struct ccb_pathinq cpi;
1348 struct ccb_relsim crs;
1349 struct ccb_setasync csa;
1350 struct ccb_setdev csd;
1351 struct ccb_pathstats cpis;
1352 struct ccb_getdevstats cgds;
1353 struct ccb_dev_match cdm;
1354 struct ccb_trans_settings cts;
1355 struct ccb_calc_geometry ccg;
1356 struct ccb_sim_knob knob;
1357 struct ccb_abort cab;
1358 struct ccb_resetbus crb;
1359 struct ccb_resetdev crd;
1360 struct ccb_termio tio;
1361 struct ccb_accept_tio atio;
1362 struct ccb_scsiio ctio;
1363 struct ccb_en_lun cel;
1364 struct ccb_immed_notify cin;
1365 struct ccb_notify_ack cna;
1366 struct ccb_immediate_notify cin1;
1367 struct ccb_notify_acknowledge cna2;
1368 struct ccb_eng_inq cei;
1369 struct ccb_eng_exec cee;
1370 struct ccb_smpio smpio;
1371 struct ccb_rescan crcn;
1372 struct ccb_debug cdbg;
1373 struct ccb_ataio ataio;
1374 struct ccb_dev_advinfo cdai;
1375 struct ccb_async casync;
1376 struct ccb_nvmeio nvmeio;
1377 struct ccb_mmcio mmcio;
1380 #define CCB_CLEAR_ALL_EXCEPT_HDR(ccbp) \
1381 bzero((char *)(ccbp) + sizeof((ccbp)->ccb_h), \
1382 sizeof(*(ccbp)) - sizeof((ccbp)->ccb_h))
1385 static __inline void
1386 cam_fill_csio(struct ccb_scsiio *csio, uint32_t retries,
1387 void (*cbfcnp)(struct cam_periph *, union ccb *),
1388 uint32_t flags, uint8_t tag_action,
1389 uint8_t *data_ptr, uint32_t dxfer_len,
1390 uint8_t sense_len, uint8_t cdb_len,
1393 csio->ccb_h.func_code = XPT_SCSI_IO;
1394 csio->ccb_h.flags = flags;
1395 csio->ccb_h.xflags = 0;
1396 csio->ccb_h.retry_count = retries;
1397 csio->ccb_h.cbfcnp = cbfcnp;
1398 csio->ccb_h.timeout = timeout;
1399 csio->data_ptr = data_ptr;
1400 csio->dxfer_len = dxfer_len;
1401 csio->sense_len = sense_len;
1402 csio->cdb_len = cdb_len;
1403 csio->tag_action = tag_action;
1405 #if defined(BUF_TRACKING) || defined(FULL_BUF_TRACKING)
1410 static __inline void
1411 cam_fill_ctio(struct ccb_scsiio *csio, uint32_t retries,
1412 void (*cbfcnp)(struct cam_periph *, union ccb *),
1413 uint32_t flags, u_int tag_action, u_int tag_id,
1414 u_int init_id, u_int scsi_status, uint8_t *data_ptr,
1415 uint32_t dxfer_len, uint32_t timeout)
1417 csio->ccb_h.func_code = XPT_CONT_TARGET_IO;
1418 csio->ccb_h.flags = flags;
1419 csio->ccb_h.xflags = 0;
1420 csio->ccb_h.retry_count = retries;
1421 csio->ccb_h.cbfcnp = cbfcnp;
1422 csio->ccb_h.timeout = timeout;
1423 csio->data_ptr = data_ptr;
1424 csio->dxfer_len = dxfer_len;
1425 csio->scsi_status = scsi_status;
1426 csio->tag_action = tag_action;
1428 csio->tag_id = tag_id;
1429 csio->init_id = init_id;
1432 static __inline void
1433 cam_fill_ataio(struct ccb_ataio *ataio, uint32_t retries,
1434 void (*cbfcnp)(struct cam_periph *, union ccb *),
1435 uint32_t flags, u_int tag_action __unused,
1436 uint8_t *data_ptr, uint32_t dxfer_len,
1439 ataio->ccb_h.func_code = XPT_ATA_IO;
1440 ataio->ccb_h.flags = flags;
1441 ataio->ccb_h.retry_count = retries;
1442 ataio->ccb_h.cbfcnp = cbfcnp;
1443 ataio->ccb_h.timeout = timeout;
1444 ataio->data_ptr = data_ptr;
1445 ataio->dxfer_len = dxfer_len;
1446 ataio->ata_flags = 0;
1449 static __inline void
1450 cam_fill_smpio(struct ccb_smpio *smpio, uint32_t retries,
1451 void (*cbfcnp)(struct cam_periph *, union ccb *), uint32_t flags,
1452 uint8_t *smp_request, int smp_request_len,
1453 uint8_t *smp_response, int smp_response_len,
1457 KASSERT((flags & CAM_DIR_MASK) == CAM_DIR_BOTH,
1458 ("direction != CAM_DIR_BOTH"));
1459 KASSERT((smp_request != NULL) && (smp_response != NULL),
1460 ("need valid request and response buffers"));
1461 KASSERT((smp_request_len != 0) && (smp_response_len != 0),
1462 ("need non-zero request and response lengths"));
1464 smpio->ccb_h.func_code = XPT_SMP_IO;
1465 smpio->ccb_h.flags = flags;
1466 smpio->ccb_h.retry_count = retries;
1467 smpio->ccb_h.cbfcnp = cbfcnp;
1468 smpio->ccb_h.timeout = timeout;
1469 smpio->smp_request = smp_request;
1470 smpio->smp_request_len = smp_request_len;
1471 smpio->smp_response = smp_response;
1472 smpio->smp_response_len = smp_response_len;
1475 static __inline void
1476 cam_fill_mmcio(struct ccb_mmcio *mmcio, uint32_t retries,
1477 void (*cbfcnp)(struct cam_periph *, union ccb *), uint32_t flags,
1478 uint32_t mmc_opcode, uint32_t mmc_arg, uint32_t mmc_flags,
1479 struct mmc_data *mmc_d,
1482 mmcio->ccb_h.func_code = XPT_MMC_IO;
1483 mmcio->ccb_h.flags = flags;
1484 mmcio->ccb_h.retry_count = retries;
1485 mmcio->ccb_h.cbfcnp = cbfcnp;
1486 mmcio->ccb_h.timeout = timeout;
1487 mmcio->cmd.opcode = mmc_opcode;
1488 mmcio->cmd.arg = mmc_arg;
1489 mmcio->cmd.flags = mmc_flags;
1490 mmcio->stop.opcode = 0;
1491 mmcio->stop.arg = 0;
1492 mmcio->stop.flags = 0;
1493 if (mmc_d != NULL) {
1494 mmcio->cmd.data = mmc_d;
1496 mmcio->cmd.data = NULL;
1497 mmcio->cmd.resp[0] = 0;
1498 mmcio->cmd.resp[1] = 0;
1499 mmcio->cmd.resp[2] = 0;
1500 mmcio->cmd.resp[3] = 0;
1503 static __inline void
1504 cam_set_ccbstatus(union ccb *ccb, cam_status status)
1506 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1507 ccb->ccb_h.status |= status;
1510 static __inline cam_status
1511 cam_ccb_status(union ccb *ccb)
1513 return ((cam_status)(ccb->ccb_h.status & CAM_STATUS_MASK));
1517 cam_ccb_success(union ccb *ccb)
1519 return (cam_ccb_status(ccb) == CAM_REQ_CMP);
1522 void cam_calc_geometry(struct ccb_calc_geometry *ccg, int extended);
1524 static __inline void
1525 cam_fill_nvmeio(struct ccb_nvmeio *nvmeio, uint32_t retries,
1526 void (*cbfcnp)(struct cam_periph *, union ccb *),
1527 uint32_t flags, uint8_t *data_ptr, uint32_t dxfer_len,
1530 nvmeio->ccb_h.func_code = XPT_NVME_IO;
1531 nvmeio->ccb_h.flags = flags;
1532 nvmeio->ccb_h.retry_count = retries;
1533 nvmeio->ccb_h.cbfcnp = cbfcnp;
1534 nvmeio->ccb_h.timeout = timeout;
1535 nvmeio->data_ptr = data_ptr;
1536 nvmeio->dxfer_len = dxfer_len;
1539 static __inline void
1540 cam_fill_nvmeadmin(struct ccb_nvmeio *nvmeio, uint32_t retries,
1541 void (*cbfcnp)(struct cam_periph *, union ccb *),
1542 uint32_t flags, uint8_t *data_ptr, uint32_t dxfer_len,
1545 nvmeio->ccb_h.func_code = XPT_NVME_ADMIN;
1546 nvmeio->ccb_h.flags = flags;
1547 nvmeio->ccb_h.retry_count = retries;
1548 nvmeio->ccb_h.cbfcnp = cbfcnp;
1549 nvmeio->ccb_h.timeout = timeout;
1550 nvmeio->data_ptr = data_ptr;
1551 nvmeio->dxfer_len = dxfer_len;
1555 #endif /* _CAM_CAM_CCB_H */