2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013-2015 Mellanox Technologies, Ltd.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <machine/vm.h>
35 #include <sys/endian.h>
36 #include <sys/types.h>
38 #include <linux/compiler.h>
39 #include <linux/types.h>
41 static inline uint32_t
42 __raw_readl(const volatile void *addr)
44 return *(const volatile uint32_t *)addr;
48 __raw_writel(uint32_t b, volatile void *addr)
50 *(volatile uint32_t *)addr = b;
53 static inline uint64_t
54 __raw_readq(const volatile void *addr)
56 return *(const volatile uint64_t *)addr;
60 __raw_writeq(uint64_t b, volatile void *addr)
62 *(volatile uint64_t *)addr = b;
66 * XXX This is all x86 specific. It should be bus space access.
68 #define mmiowb() barrier()
72 writel(uint32_t b, void *addr)
74 *(volatile uint32_t *)addr = b;
79 writel_relaxed(uint32_t b, void *addr)
81 *(volatile uint32_t *)addr = b;
86 writeq(uint64_t b, void *addr)
88 *(volatile uint64_t *)addr = b;
93 writeb(uint8_t b, void *addr)
95 *(volatile uint8_t *)addr = b;
100 writew(uint16_t b, void *addr)
102 *(volatile uint16_t *)addr = b;
106 static inline uint8_t
107 ioread8(const volatile void *addr)
109 return *(const volatile uint8_t *)addr;
113 static inline uint16_t
114 ioread16(const volatile void *addr)
116 return *(const volatile uint16_t *)addr;
120 static inline uint16_t
121 ioread16be(const volatile void *addr)
123 return be16toh(*(const volatile uint16_t *)addr);
127 static inline uint32_t
128 ioread32(const volatile void *addr)
130 return *(const volatile uint32_t *)addr;
134 static inline uint32_t
135 ioread32be(const volatile void *addr)
137 return be32toh(*(const volatile uint32_t *)addr);
142 iowrite8(uint8_t v, volatile void *addr)
144 *(volatile uint8_t *)addr = v;
149 iowrite16(uint16_t v, volatile void *addr)
151 *(volatile uint16_t *)addr = v;
156 iowrite32(uint32_t v, volatile void *addr)
158 *(volatile uint32_t *)addr = v;
163 iowrite32be(uint32_t v, volatile void *addr)
165 *(volatile uint32_t *)addr = htobe32(v);
169 static inline uint8_t
170 readb(const volatile void *addr)
172 return *(const volatile uint8_t *)addr;
176 static inline uint16_t
177 readw(const volatile void *addr)
179 return *(const volatile uint16_t *)addr;
183 static inline uint32_t
184 readl(const volatile void *addr)
186 return *(const volatile uint32_t *)addr;
189 #if defined(__i386__) || defined(__amd64__)
191 _outb(u_char data, u_int port)
193 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
197 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
198 void *_ioremap_attr(vm_paddr_t phys_addr, unsigned long size, int attr);
200 #define _ioremap_attr(...) NULL
203 #define ioremap_nocache(addr, size) \
204 _ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE)
205 #define ioremap_wc(addr, size) \
206 _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_COMBINING)
207 #define ioremap_wb(addr, size) \
208 _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_BACK)
209 #define ioremap_wt(addr, size) \
210 _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_THROUGH)
211 #define ioremap(addr, size) \
212 _ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE)
213 void iounmap(void *addr);
215 #define memset_io(a, b, c) memset((a), (b), (c))
216 #define memcpy_fromio(a, b, c) memcpy((a), (b), (c))
217 #define memcpy_toio(a, b, c) memcpy((a), (b), (c))
220 __iowrite32_copy(void *to, void *from, size_t count)
226 for (i = 0, src = from, dst = to; i < count; i++, src++, dst++)
227 __raw_writel(*src, dst);
231 __iowrite64_copy(void *to, void *from, size_t count)
238 for (i = 0, src = from, dst = to; i < count; i++, src++, dst++)
239 __raw_writeq(*src, dst);
241 __iowrite32_copy(to, from, count * 2);
246 MEMREMAP_WB = 1 << 0,
247 MEMREMAP_WT = 1 << 1,
248 MEMREMAP_WC = 1 << 2,
252 memremap(resource_size_t offset, size_t size, unsigned long flags)
256 if ((flags & MEMREMAP_WB) &&
257 (addr = ioremap_wb(offset, size)) != NULL)
259 if ((flags & MEMREMAP_WT) &&
260 (addr = ioremap_wt(offset, size)) != NULL)
262 if ((flags & MEMREMAP_WC) &&
263 (addr = ioremap_wc(offset, size)) != NULL)
272 /* XXX May need to check if this is RAM */
276 #endif /* _LINUX_IO_H_ */