2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013-2015 Mellanox Technologies, Ltd.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <machine/vm.h>
35 #include <sys/endian.h>
36 #include <sys/types.h>
38 #include <linux/compiler.h>
39 #include <linux/types.h>
42 * XXX This is all x86 specific. It should be bus space access.
45 /* Access MMIO registers atomically without barriers and byte swapping. */
48 __raw_readb(const volatile void *addr)
50 return (*(const volatile uint8_t *)addr);
52 #define __raw_readb(addr) __raw_readb(addr)
55 __raw_writeb(uint8_t v, volatile void *addr)
57 *(volatile uint8_t *)addr = v;
59 #define __raw_writeb(v, addr) __raw_writeb(v, addr)
61 static inline uint16_t
62 __raw_readw(const volatile void *addr)
64 return (*(const volatile uint16_t *)addr);
66 #define __raw_readw(addr) __raw_readw(addr)
69 __raw_writew(uint16_t v, volatile void *addr)
71 *(volatile uint16_t *)addr = v;
73 #define __raw_writew(v, addr) __raw_writew(v, addr)
75 static inline uint32_t
76 __raw_readl(const volatile void *addr)
78 return (*(const volatile uint32_t *)addr);
80 #define __raw_readl(addr) __raw_readl(addr)
83 __raw_writel(uint32_t v, volatile void *addr)
85 *(volatile uint32_t *)addr = v;
87 #define __raw_writel(v, addr) __raw_writel(v, addr)
90 static inline uint64_t
91 __raw_readq(const volatile void *addr)
93 return (*(const volatile uint64_t *)addr);
95 #define __raw_readq(addr) __raw_readq(addr)
98 __raw_writeq(uint64_t v, volatile void *addr)
100 *(volatile uint64_t *)addr = v;
102 #define __raw_writeq(v, addr) __raw_writeq(v, addr)
105 #define mmiowb() barrier()
107 /* Access little-endian MMIO registers atomically with memory barriers. */
110 static inline uint8_t
111 readb(const volatile void *addr)
116 v = *(const volatile uint8_t *)addr;
120 #define readb(addr) readb(addr)
124 writeb(uint8_t v, volatile void *addr)
127 *(volatile uint8_t *)addr = v;
130 #define writeb(v, addr) writeb(v, addr)
133 static inline uint16_t
134 readw(const volatile void *addr)
139 v = *(const volatile uint16_t *)addr;
143 #define readw(addr) readw(addr)
147 writew(uint16_t v, volatile void *addr)
150 *(volatile uint16_t *)addr = v;
153 #define writew(v, addr) writew(v, addr)
156 static inline uint32_t
157 readl(const volatile void *addr)
162 v = *(const volatile uint32_t *)addr;
166 #define readl(addr) readl(addr)
170 writel(uint32_t v, volatile void *addr)
173 *(volatile uint32_t *)addr = v;
176 #define writel(v, addr) writel(v, addr)
181 static inline uint64_t
182 readq(const volatile void *addr)
187 v = *(const volatile uint64_t *)addr;
191 #define readq(addr) readq(addr)
194 writeq(uint64_t v, volatile void *addr)
197 *(volatile uint64_t *)addr = v;
200 #define writeq(v, addr) writeq(v, addr)
203 /* Access little-endian MMIO registers atomically without memory barriers. */
206 static inline uint8_t
207 readb_relaxed(const volatile void *addr)
209 return (*(const volatile uint8_t *)addr);
211 #define readb_relaxed(addr) readb_relaxed(addr)
213 #undef writeb_relaxed
215 writeb_relaxed(uint8_t v, volatile void *addr)
217 *(volatile uint8_t *)addr = v;
219 #define writeb_relaxed(v, addr) writeb_relaxed(v, addr)
222 static inline uint16_t
223 readw_relaxed(const volatile void *addr)
225 return (*(const volatile uint16_t *)addr);
227 #define readw_relaxed(addr) readw_relaxed(addr)
229 #undef writew_relaxed
231 writew_relaxed(uint16_t v, volatile void *addr)
233 *(volatile uint16_t *)addr = v;
235 #define writew_relaxed(v, addr) writew_relaxed(v, addr)
238 static inline uint32_t
239 readl_relaxed(const volatile void *addr)
241 return (*(const volatile uint32_t *)addr);
243 #define readl_relaxed(addr) readl_relaxed(addr)
245 #undef writel_relaxed
247 writel_relaxed(uint32_t v, volatile void *addr)
249 *(volatile uint32_t *)addr = v;
251 #define writel_relaxed(v, addr) writel_relaxed(v, addr)
254 #undef writeq_relaxed
256 static inline uint64_t
257 readq_relaxed(const volatile void *addr)
259 return (*(const volatile uint64_t *)addr);
261 #define readq_relaxed(addr) readq_relaxed(addr)
264 writeq_relaxed(uint64_t v, volatile void *addr)
266 *(volatile uint64_t *)addr = v;
268 #define writeq_relaxed(v, addr) writeq_relaxed(v, addr)
271 /* XXX On Linux ioread and iowrite handle both MMIO and port IO. */
274 static inline uint8_t
275 ioread8(const volatile void *addr)
277 return (readb(addr));
279 #define ioread8(addr) ioread8(addr)
282 static inline uint16_t
283 ioread16(const volatile void *addr)
285 return (readw(addr));
287 #define ioread16(addr) ioread16(addr)
290 static inline uint16_t
291 ioread16be(const volatile void *addr)
293 return (bswap16(readw(addr)));
295 #define ioread16be(addr) ioread16be(addr)
298 static inline uint32_t
299 ioread32(const volatile void *addr)
301 return (readl(addr));
303 #define ioread32(addr) ioread32(addr)
306 static inline uint32_t
307 ioread32be(const volatile void *addr)
309 return (bswap32(readl(addr)));
311 #define ioread32be(addr) ioread32be(addr)
315 iowrite8(uint8_t v, volatile void *addr)
319 #define iowrite8(v, addr) iowrite8(v, addr)
323 iowrite16(uint16_t v, volatile void *addr)
327 #define iowrite16 iowrite16
331 iowrite32(uint32_t v, volatile void *addr)
335 #define iowrite32(v, addr) iowrite32(v, addr)
339 iowrite32be(uint32_t v, volatile void *addr)
341 writel(bswap32(v), addr);
343 #define iowrite32be(v, addr) iowrite32be(v, addr)
345 #if defined(__i386__) || defined(__amd64__)
347 _outb(u_char data, u_int port)
349 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
353 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
354 void *_ioremap_attr(vm_paddr_t phys_addr, unsigned long size, int attr);
356 #define _ioremap_attr(...) NULL
359 #define ioremap_nocache(addr, size) \
360 _ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE)
361 #define ioremap_wc(addr, size) \
362 _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_COMBINING)
363 #define ioremap_wb(addr, size) \
364 _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_BACK)
365 #define ioremap_wt(addr, size) \
366 _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_THROUGH)
367 #define ioremap(addr, size) \
368 _ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE)
369 void iounmap(void *addr);
371 #define memset_io(a, b, c) memset((a), (b), (c))
372 #define memcpy_fromio(a, b, c) memcpy((a), (b), (c))
373 #define memcpy_toio(a, b, c) memcpy((a), (b), (c))
376 __iowrite32_copy(void *to, void *from, size_t count)
382 for (i = 0, src = from, dst = to; i < count; i++, src++, dst++)
383 __raw_writel(*src, dst);
387 __iowrite64_copy(void *to, void *from, size_t count)
394 for (i = 0, src = from, dst = to; i < count; i++, src++, dst++)
395 __raw_writeq(*src, dst);
397 __iowrite32_copy(to, from, count * 2);
402 MEMREMAP_WB = 1 << 0,
403 MEMREMAP_WT = 1 << 1,
404 MEMREMAP_WC = 1 << 2,
408 memremap(resource_size_t offset, size_t size, unsigned long flags)
412 if ((flags & MEMREMAP_WB) &&
413 (addr = ioremap_wb(offset, size)) != NULL)
415 if ((flags & MEMREMAP_WT) &&
416 (addr = ioremap_wt(offset, size)) != NULL)
418 if ((flags & MEMREMAP_WC) &&
419 (addr = ioremap_wc(offset, size)) != NULL)
428 /* XXX May need to check if this is RAM */
432 #endif /* _LINUX_IO_H_ */