2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
7 * Copyright (c) 2020-2021 The FreeBSD Foundation
9 * Portions of this software were developed by Björn Zeeb
10 * under sponsorship from the FreeBSD Foundation.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice unmodified, this list of conditions, and the following
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #ifndef _LINUXKPI_LINUX_PCI_H_
36 #define _LINUXKPI_LINUX_PCI_H_
38 #define CONFIG_PCI_MSI
40 #include <linux/types.h>
42 #include <sys/param.h>
44 #include <sys/module.h>
46 #include <sys/pciio.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pci_private.h>
52 #include <machine/resource.h>
54 #include <linux/list.h>
55 #include <linux/dmapool.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/compiler.h>
58 #include <linux/errno.h>
59 #include <asm/atomic.h>
60 #include <linux/device.h>
61 #include <linux/pci_ids.h>
63 struct pci_device_id {
70 uintptr_t driver_data;
73 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */
74 #define MODULE_DEVICE_TABLE(_bus, _table) \
76 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \
80 static driver_t _ ## _bus ## _ ## _table ## _driver = { \
81 "lkpi_" #_bus #_table, \
82 _ ## _bus ## _ ## _table ## _methods, \
86 static devclass_t _ ## _bus ## _ ## _table ## _devclass; \
88 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\
89 _ ## _bus ## _ ## _table ## _devclass, 0, 0); \
91 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \
92 _bus, lkpi_ ## _table, _table, nitems(_table) - 1)
94 #define PCI_ANY_ID -1U
96 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
97 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
98 #define PCI_FUNC(devfn) ((devfn) & 0x07)
99 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff)
101 #define PCI_VDEVICE(_vendor, _device) \
102 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \
103 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
104 #define PCI_DEVICE(_vendor, _device) \
105 .vendor = (_vendor), .device = (_device), \
106 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
108 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
110 #define PCI_VENDOR_ID PCIR_DEVVENDOR
111 #define PCI_COMMAND PCIR_COMMAND
112 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS
113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */
114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */
115 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S
116 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1
117 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC
118 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */
119 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD
120 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */
121 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */
122 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */
123 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */
124 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */
125 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */
126 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */
127 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */
128 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */
129 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */
130 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */
131 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */
132 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */
133 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE
134 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */
135 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */
136 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */
137 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */
138 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */
139 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */
140 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */
141 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */
142 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */
143 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */
144 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */
145 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */
146 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */
147 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */
148 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */
149 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */
150 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
151 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
152 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
153 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */
154 #define PCI_EXP_LNKCTL2_TLS 0x000f
155 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
156 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
157 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
158 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
159 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
160 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
161 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
163 #define PCI_EXP_LNKCAP_CLKPM 0x00040000
164 #define PCI_EXP_DEVSTA_TRPND 0x0020
166 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY)
167 #define IORESOURCE_IO (1 << SYS_RES_IOPORT)
168 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ)
171 PCI_SPEED_UNKNOWN = -1,
178 enum pcie_link_width {
179 PCIE_LNK_WIDTH_RESRV = 0x00,
187 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
190 #define PCIE_LINK_STATE_L0S 0x00000001
191 #define PCIE_LINK_STATE_L1 0x00000002
192 #define PCIE_LINK_STATE_CLKPM 0x00000004
194 typedef int pci_power_t;
196 #define PCI_D0 PCI_POWERSTATE_D0
197 #define PCI_D1 PCI_POWERSTATE_D1
198 #define PCI_D2 PCI_POWERSTATE_D2
199 #define PCI_D3hot PCI_POWERSTATE_D3
202 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN
204 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD
205 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID
207 #define PCI_EXT_CAP_ID_ERR PCIZ_AER
208 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM
210 #define PCI_L1SS_CTL1 0x8
211 #define PCI_L1SS_CTL1_L1SS_MASK 0xf
213 #define PCI_IRQ_LEGACY 0x01
214 #define PCI_IRQ_MSI 0x02
215 #define PCI_IRQ_MSIX 0x04
220 struct list_head node;
222 const struct pci_device_id *id_table;
223 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
224 void (*remove)(struct pci_dev *dev);
225 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
226 int (*resume) (struct pci_dev *dev); /* Device woken up */
227 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */
230 struct device_driver driver;
231 const struct pci_error_handlers *err_handler;
232 int bsd_probe_return;
233 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs,
234 const nvlist_t *pf_config);
235 void (*bsd_iov_uninit)(device_t dev);
236 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum,
237 const nvlist_t *vf_config);
242 * Pseudo-stable KPI. In 13.0 we neglected to include any spare fields to allow
243 * for growth in struct pci_driver. Those were added in 13.1, but can't be used
244 * until 13.1 is the oldest supported release so that packages built in 13.0
245 * will continue to work on stable/13 and 13.1 release. The 13.0 driver was 92
246 * or 182 bytes on 32 or 64 bit systems (respectively). We added 64 or 32 bytes
247 * of padding, hence the math below (which shouldn't be changed as spare fields
251 #define __PCI_DRIVER_SIZE (184 + 64)
253 #define __PCI_DRIVER_SIZE (92 + 32)
255 _Static_assert(sizeof(struct pci_driver) == __PCI_DRIVER_SIZE,
256 "linuxkpi struct pci_driver: Bad size");
257 #undef __PCI_DRIVER_SIZE
260 struct pci_dev *self;
265 extern struct list_head pci_drivers;
266 extern struct list_head pci_devices;
267 extern spinlock_t pci_lock;
269 #define __devexit_p(x) x
271 #define module_pci_driver(_driver) \
277 return (linux_pci_register_driver(&_driver)); \
284 linux_pci_unregister_driver(&_driver); \
287 module_init(_pci_init); \
288 module_exit(_pci_exit)
291 * If we find drivers accessing this from multiple KPIs we may have to
292 * refcount objects of this structure.
294 struct pci_mmio_region {
295 TAILQ_ENTRY(pci_mmio_region) next;
296 struct resource *res;
303 struct list_head links;
304 struct pci_driver *pdrv;
308 uint16_t subsystem_vendor;
309 uint16_t subsystem_device;
316 TAILQ_HEAD(, pci_mmio_region) mmio;
318 /* Add all new items at the end of the list in 13 */
319 struct pci_dev *root;
322 bool managed; /* devres "pcim_*(). */
327 /* XXX add kassert here on the mmio offset */
329 /* We need some meta-struct to keep track of these for devres. */
332 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */
334 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */
336 struct pcim_iomap_devres {
337 void *mmio_table[PCIR_MAX_BAR_0 + 1];
338 struct resource *res_table[PCIR_MAX_BAR_0 + 1];
341 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name);
343 /* Internal helper function(s). */
344 struct pci_dev *lkpinew_pci_dev(device_t);
345 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev);
346 void lkpi_pci_devres_release(struct device *, void *);
347 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size);
348 void lkpi_pcim_iomap_table_release(struct device *, void *);
351 pci_resource_type(struct pci_dev *pdev, int bar)
355 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar));
359 if (PCI_BAR_IO(pm->pm_value))
360 return (SYS_RES_IOPORT);
362 return (SYS_RES_MEMORY);
365 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev,
366 struct resource_list *rl, int type, int rid);
368 static inline struct resource_list_entry *
369 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar)
371 struct pci_devinfo *dinfo;
372 struct resource_list *rl;
373 struct resource_list_entry *rle;
375 dinfo = device_get_ivars(pdev->dev.bsddev);
376 rl = &dinfo->resources;
377 rle = resource_list_find(rl, type, rid);
378 /* Reserve resources for this BAR if needed. */
379 if (rle == NULL && reserve_bar)
380 rle = linux_pci_reserve_bar(pdev, rl, type, rid);
384 static inline struct resource_list_entry *
385 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve)
389 type = pci_resource_type(pdev, bar);
393 return (linux_pci_get_rle(pdev, type, bar, reserve));
396 static inline struct device *
397 linux_pci_find_irq_dev(unsigned int irq)
399 struct pci_dev *pdev;
400 struct device *found;
403 spin_lock(&pci_lock);
404 list_for_each_entry(pdev, &pci_devices, links) {
405 if (irq == pdev->dev.irq ||
406 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) {
411 spin_unlock(&pci_lock);
416 * All drivers just seem to want to inspect the type not flags.
419 pci_resource_flags(struct pci_dev *pdev, int bar)
423 type = pci_resource_type(pdev, bar);
429 static inline const char *
430 pci_name(struct pci_dev *d)
433 return device_get_desc(d->dev.bsddev);
437 pci_get_drvdata(struct pci_dev *pdev)
440 return dev_get_drvdata(&pdev->dev);
444 pci_set_drvdata(struct pci_dev *pdev, void *data)
447 dev_set_drvdata(&pdev->dev, data);
450 static inline struct pci_dev *
451 pci_dev_get(struct pci_dev *pdev)
455 get_device(&pdev->dev);
460 pci_dev_put(struct pci_dev *pdev)
464 put_device(&pdev->dev);
468 pci_enable_device(struct pci_dev *pdev)
471 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
472 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
477 pci_disable_device(struct pci_dev *pdev)
480 pci_disable_busmaster(pdev->dev.bsddev);
484 pci_set_master(struct pci_dev *pdev)
487 pci_enable_busmaster(pdev->dev.bsddev);
492 pci_set_power_state(struct pci_dev *pdev, int state)
495 pci_set_powerstate(pdev->dev.bsddev, state);
500 pci_clear_master(struct pci_dev *pdev)
503 pci_disable_busmaster(pdev->dev.bsddev);
508 pci_is_root_bus(struct pci_bus *pbus)
511 return (pbus->self == NULL);
514 static inline struct pci_dev *
515 pci_upstream_bridge(struct pci_dev *pdev)
518 if (pci_is_root_bus(pdev->bus))
522 * If we do not have a (proper) "upstream bridge" set, e.g., we point
523 * to ourselves, try to handle this case on the fly like we do
524 * for pcie_find_root_port().
526 if (pdev == pdev->bus->self) {
529 bridge = device_get_parent(pdev->dev.bsddev);
532 bridge = device_get_parent(bridge);
535 if (device_get_devclass(device_get_parent(bridge)) !=
536 devclass_find("pci"))
540 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev
541 * for it so it can be returned.
543 pdev->bus->self = lkpinew_pci_dev(bridge);
546 return (pdev->bus->self);
549 static inline struct pci_devres *
550 lkpi_pci_devres_find(struct pci_dev *pdev)
556 return (lkpi_pci_devres_get_alloc(pdev));
560 pci_release_region(struct pci_dev *pdev, int bar)
562 struct resource_list_entry *rle;
563 struct pci_devres *dr;
564 struct pci_mmio_region *mmio, *p;
566 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL)
570 * As we implicitly track the requests we also need to clear them on
571 * release. Do clear before resource release.
573 dr = lkpi_pci_devres_find(pdev);
575 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d"
576 " region_table res %p != rel->res %p\n", __func__, pdev,
577 bar, dr->region_table[bar], rle->res));
578 dr->region_table[bar] = NULL;
579 dr->region_mask &= ~(1 << bar);
582 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) {
583 if (rle->res != (void *)rman_get_bushandle(mmio->res))
585 TAILQ_REMOVE(&pdev->mmio, mmio, next);
586 free(mmio, M_DEVBUF);
589 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res);
593 pci_release_regions(struct pci_dev *pdev)
597 for (i = 0; i <= PCIR_MAX_BAR_0; i++)
598 pci_release_region(pdev, i);
602 pci_request_regions(struct pci_dev *pdev, const char *res_name)
607 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
608 error = pci_request_region(pdev, i, res_name);
609 if (error && error != -ENODEV) {
610 pci_release_regions(pdev);
618 lkpi_pci_disable_msix(struct pci_dev *pdev)
621 pci_release_msi(pdev->dev.bsddev);
624 * The MSIX IRQ numbers associated with this PCI device are no
625 * longer valid and might be re-assigned. Make sure
626 * linux_pci_find_irq_dev() does no longer see them by
627 * resetting their references to zero:
629 pdev->dev.irq_start = 0;
630 pdev->dev.irq_end = 0;
631 pdev->msix_enabled = false;
633 /* Only for consistency. No conflict on that one. */
634 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev)
637 lkpi_pci_disable_msi(struct pci_dev *pdev)
640 pci_release_msi(pdev->dev.bsddev);
642 pdev->dev.irq_start = 0;
643 pdev->dev.irq_end = 0;
644 pdev->irq = pdev->dev.irq;
645 pdev->msi_enabled = false;
647 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev)
648 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev)
650 unsigned long pci_resource_start(struct pci_dev *pdev, int bar);
651 unsigned long pci_resource_len(struct pci_dev *pdev, int bar);
653 static inline bus_addr_t
654 pci_bus_address(struct pci_dev *pdev, int bar)
657 return (pci_resource_start(pdev, bar));
660 #define PCI_CAP_ID_EXP PCIY_EXPRESS
661 #define PCI_CAP_ID_PCIX PCIY_PCIX
662 #define PCI_CAP_ID_AGP PCIY_AGP
663 #define PCI_CAP_ID_PM PCIY_PMG
665 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
666 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
667 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST
668 #define PCI_EXP_LNKCTL PCIER_LINK_CTL
669 #define PCI_EXP_LNKSTA PCIER_LINK_STA
672 pci_find_capability(struct pci_dev *pdev, int capid)
676 if (pci_find_cap(pdev->dev.bsddev, capid, ®))
681 static inline int pci_pcie_cap(struct pci_dev *dev)
683 return pci_find_capability(dev, PCI_CAP_ID_EXP);
687 pci_find_ext_capability(struct pci_dev *pdev, int capid)
691 if (pci_find_extcap(pdev->dev.bsddev, capid, ®))
696 #define PCIM_PCAP_PME_SHIFT 11
698 pci_pme_capable(struct pci_dev *pdev, uint32_t flag)
700 struct pci_devinfo *dinfo;
703 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT))
706 dinfo = device_get_ivars(pdev->dev.bsddev);
709 if (cfg->pp.pp_cap == 0)
712 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0)
719 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags)
722 if (!pci_enable_aspm)
729 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val)
732 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);
737 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val)
740 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2);
745 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val)
748 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
753 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val)
756 pci_write_config(pdev->dev.bsddev, where, val, 1);
761 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val)
764 pci_write_config(pdev->dev.bsddev, where, val, 2);
769 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val)
772 pci_write_config(pdev->dev.bsddev, where, val, 4);
776 int linux_pci_register_driver(struct pci_driver *pdrv);
777 int linux_pci_register_drm_driver(struct pci_driver *pdrv);
778 void linux_pci_unregister_driver(struct pci_driver *pdrv);
779 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv);
781 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv)
782 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv)
790 * Enable msix, positive errors indicate actual number of available
791 * vectors. Negative errors are failures.
793 * NB: define added to prevent this definition of pci_enable_msix from
794 * clashing with the native FreeBSD version.
796 #define pci_enable_msix(...) \
797 linux_pci_enable_msix(__VA_ARGS__)
800 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq)
802 struct resource_list_entry *rle;
807 avail = pci_msix_count(pdev->dev.bsddev);
814 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0)
817 * Handle case where "pci_alloc_msix()" may allocate less
818 * interrupts than available and return with no error:
821 pci_release_msi(pdev->dev.bsddev);
824 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false);
825 pdev->dev.irq_start = rle->start;
826 pdev->dev.irq_end = rle->start + avail;
827 for (i = 0; i < nreq; i++)
828 entries[i].vector = pdev->dev.irq_start + i;
829 pdev->msix_enabled = true;
833 #define pci_enable_msix_range(...) \
834 linux_pci_enable_msix_range(__VA_ARGS__)
837 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
838 int minvec, int maxvec)
847 rc = pci_enable_msix(dev, entries, nvec);
859 #define pci_enable_msi(pdev) \
860 linux_pci_enable_msi(pdev)
863 pci_enable_msi(struct pci_dev *pdev)
865 struct resource_list_entry *rle;
869 avail = pci_msi_count(pdev->dev.bsddev);
873 avail = 1; /* this function only enable one MSI IRQ */
874 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0)
877 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false);
878 pdev->dev.irq_start = rle->start;
879 pdev->dev.irq_end = rle->start + avail;
880 pdev->irq = rle->start;
881 pdev->msi_enabled = true;
886 pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv,
891 if (flags & PCI_IRQ_MSIX) {
892 struct msix_entry *entries;
895 entries = kcalloc(maxv, sizeof(*entries), GFP_KERNEL);
896 if (entries == NULL) {
900 for (i = 0; i < maxv; ++i)
901 entries[i].entry = i;
902 error = pci_enable_msix(pdev, entries, maxv);
905 if (error == 0 && pdev->msix_enabled)
906 return (pdev->dev.irq_end - pdev->dev.irq_start);
908 if (flags & PCI_IRQ_MSI) {
909 error = pci_enable_msi(pdev);
910 if (error == 0 && pdev->msi_enabled)
911 return (pdev->dev.irq_end - pdev->dev.irq_start);
913 if (flags & PCI_IRQ_LEGACY) {
922 pci_channel_offline(struct pci_dev *pdev)
925 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID);
928 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
933 static inline void pci_disable_sriov(struct pci_dev *dev)
938 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size)
940 struct resource *res;
942 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size);
945 /* This is a FreeBSD extension so we can use bus_*(). */
946 if (pdev->want_iomap_res)
948 return ((void *)rman_get_bushandle(res));
952 pci_iounmap(struct pci_dev *pdev, void *res)
954 struct pci_mmio_region *mmio, *p;
956 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) {
957 if (res != (void *)rman_get_bushandle(mmio->res))
959 bus_release_resource(pdev->dev.bsddev,
960 mmio->type, mmio->rid, mmio->res);
961 TAILQ_REMOVE(&pdev->mmio, mmio, next);
962 free(mmio, M_DEVBUF);
968 lkpi_pci_save_state(struct pci_dev *pdev)
971 pci_save_state(pdev->dev.bsddev);
975 lkpi_pci_restore_state(struct pci_dev *pdev)
978 pci_restore_state(pdev->dev.bsddev);
981 #define pci_save_state(dev) lkpi_pci_save_state(dev)
982 #define pci_restore_state(dev) lkpi_pci_restore_state(dev)
984 #define DEFINE_PCI_DEVICE_TABLE(_table) \
985 const struct pci_device_id _table[] __devinitdata
987 /* XXX This should not be necessary. */
988 #define pcix_set_mmrbc(d, v) 0
989 #define pcix_get_max_mmrbc(d) 0
990 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v))
992 #define PCI_DMA_BIDIRECTIONAL 0
993 #define PCI_DMA_TODEVICE 1
994 #define PCI_DMA_FROMDEVICE 2
995 #define PCI_DMA_NONE 3
997 #define pci_pool dma_pool
998 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__)
999 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__)
1000 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__)
1001 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \
1002 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc)
1003 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \
1004 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
1005 _size, _vaddr, _dma_handle)
1006 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \
1007 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
1008 _sg, _nents, (enum dma_data_direction)_dir)
1009 #define pci_map_single(_hwdev, _ptr, _size, _dir) \
1010 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
1011 (_ptr), (_size), (enum dma_data_direction)_dir)
1012 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \
1013 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
1014 _addr, _size, (enum dma_data_direction)_dir)
1015 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \
1016 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
1017 _sg, _nents, (enum dma_data_direction)_dir)
1018 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \
1019 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\
1020 _offset, _size, (enum dma_data_direction)_dir)
1021 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \
1022 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
1023 _dma_address, _size, (enum dma_data_direction)_dir)
1024 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask))
1025 #define pci_dma_mapping_error(_pdev, _dma_addr) \
1026 dma_mapping_error(&(_pdev)->dev, _dma_addr)
1027 #define pci_set_consistent_dma_mask(_pdev, _mask) \
1028 dma_set_coherent_mask(&(_pdev)->dev, (_mask))
1029 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x);
1030 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x);
1031 #define pci_unmap_addr dma_unmap_addr
1032 #define pci_unmap_addr_set dma_unmap_addr_set
1033 #define pci_unmap_len dma_unmap_len
1034 #define pci_unmap_len_set dma_unmap_len_set
1036 typedef unsigned int __bitwise pci_channel_state_t;
1037 typedef unsigned int __bitwise pci_ers_result_t;
1039 enum pci_channel_state {
1040 pci_channel_io_normal = 1,
1041 pci_channel_io_frozen = 2,
1042 pci_channel_io_perm_failure = 3,
1045 enum pci_ers_result {
1046 PCI_ERS_RESULT_NONE = 1,
1047 PCI_ERS_RESULT_CAN_RECOVER = 2,
1048 PCI_ERS_RESULT_NEED_RESET = 3,
1049 PCI_ERS_RESULT_DISCONNECT = 4,
1050 PCI_ERS_RESULT_RECOVERED = 5,
1053 /* PCI bus error event callbacks */
1054 struct pci_error_handlers {
1055 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
1056 enum pci_channel_state error);
1057 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
1058 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
1059 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
1060 void (*resume)(struct pci_dev *dev);
1063 /* FreeBSD does not support SRIOV - yet */
1064 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
1069 static inline bool pci_is_pcie(struct pci_dev *dev)
1071 return !!pci_pcie_cap(dev);
1074 static inline u16 pcie_flags_reg(struct pci_dev *dev)
1079 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
1083 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);
1088 static inline int pci_pcie_type(struct pci_dev *dev)
1090 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1093 static inline int pcie_cap_version(struct pci_dev *dev)
1095 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS;
1098 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev)
1100 int type = pci_pcie_type(dev);
1102 return pcie_cap_version(dev) > 1 ||
1103 type == PCI_EXP_TYPE_ROOT_PORT ||
1104 type == PCI_EXP_TYPE_ENDPOINT ||
1105 type == PCI_EXP_TYPE_LEG_END;
1108 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
1113 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev)
1115 int type = pci_pcie_type(dev);
1117 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
1118 (type == PCI_EXP_TYPE_DOWNSTREAM &&
1119 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT);
1122 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev)
1124 int type = pci_pcie_type(dev);
1126 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
1127 type == PCI_EXP_TYPE_RC_EC;
1130 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
1132 if (!pci_is_pcie(dev))
1136 case PCI_EXP_FLAGS_TYPE:
1138 case PCI_EXP_DEVCAP:
1139 case PCI_EXP_DEVCTL:
1140 case PCI_EXP_DEVSTA:
1141 return pcie_cap_has_devctl(dev);
1142 case PCI_EXP_LNKCAP:
1143 case PCI_EXP_LNKCTL:
1144 case PCI_EXP_LNKSTA:
1145 return pcie_cap_has_lnkctl(dev);
1146 case PCI_EXP_SLTCAP:
1147 case PCI_EXP_SLTCTL:
1148 case PCI_EXP_SLTSTA:
1149 return pcie_cap_has_sltctl(dev);
1153 return pcie_cap_has_rtctl(dev);
1154 case PCI_EXP_DEVCAP2:
1155 case PCI_EXP_DEVCTL2:
1156 case PCI_EXP_LNKCAP2:
1157 case PCI_EXP_LNKCTL2:
1158 case PCI_EXP_LNKSTA2:
1159 return pcie_cap_version(dev) > 1;
1166 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
1171 if (!pcie_capability_reg_implemented(dev, pos))
1174 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
1178 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
1183 if (!pcie_capability_reg_implemented(dev, pos))
1186 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
1190 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
1195 if (!pcie_capability_reg_implemented(dev, pos))
1198 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
1201 static inline int pcie_get_minimum_link(struct pci_dev *dev,
1202 enum pci_bus_speed *speed, enum pcie_link_width *width)
1204 *speed = PCI_SPEED_UNKNOWN;
1205 *width = PCIE_LNK_WIDTH_UNKNOWN;
1210 pci_num_vf(struct pci_dev *dev)
1215 static inline enum pci_bus_speed
1216 pcie_get_speed_cap(struct pci_dev *dev)
1219 uint32_t lnkcap, lnkcap2;
1222 root = device_get_parent(dev->dev.bsddev);
1224 return (PCI_SPEED_UNKNOWN);
1225 root = device_get_parent(root);
1227 return (PCI_SPEED_UNKNOWN);
1228 root = device_get_parent(root);
1230 return (PCI_SPEED_UNKNOWN);
1232 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA ||
1233 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS)
1234 return (PCI_SPEED_UNKNOWN);
1236 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0)
1237 return (PCI_SPEED_UNKNOWN);
1239 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4);
1241 if (lnkcap2) { /* PCIe r3.0-compliant */
1242 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
1243 return (PCIE_SPEED_2_5GT);
1244 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
1245 return (PCIE_SPEED_5_0GT);
1246 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
1247 return (PCIE_SPEED_8_0GT);
1248 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
1249 return (PCIE_SPEED_16_0GT);
1250 } else { /* pre-r3.0 */
1251 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4);
1252 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
1253 return (PCIE_SPEED_2_5GT);
1254 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
1255 return (PCIE_SPEED_5_0GT);
1256 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
1257 return (PCIE_SPEED_8_0GT);
1258 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
1259 return (PCIE_SPEED_16_0GT);
1261 return (PCI_SPEED_UNKNOWN);
1264 static inline enum pcie_link_width
1265 pcie_get_width_cap(struct pci_dev *dev)
1269 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
1271 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4);
1273 return (PCIE_LNK_WIDTH_UNKNOWN);
1277 pcie_get_mps(struct pci_dev *dev)
1279 return (pci_get_max_payload(dev->dev.bsddev));
1282 static inline uint32_t
1283 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)
1287 case PCIE_SPEED_16_0GT:
1288 return (16000 * 128 / 130);
1289 case PCIE_SPEED_8_0GT:
1290 return (8000 * 128 / 130);
1291 case PCIE_SPEED_5_0GT:
1292 return (5000 * 8 / 10);
1293 case PCIE_SPEED_2_5GT:
1294 return (2500 * 8 / 10);
1300 static inline uint32_t
1301 pcie_bandwidth_available(struct pci_dev *pdev,
1302 struct pci_dev **limiting,
1303 enum pci_bus_speed *speed,
1304 enum pcie_link_width *width)
1306 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev);
1307 enum pcie_link_width nwidth = pcie_get_width_cap(pdev);
1314 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed));
1317 static inline struct pci_dev *
1318 pcie_find_root_port(struct pci_dev *pdev)
1322 if (pdev->root != NULL)
1323 return (pdev->root);
1325 root = pci_find_pcie_root_port(pdev->dev.bsddev);
1329 pdev->root = lkpinew_pci_dev(root);
1330 return (pdev->root);
1333 /* This is needed when people rip out the device "HotPlug". */
1335 pci_lock_rescan_remove(void)
1340 pci_unlock_rescan_remove(void)
1344 static __inline void
1345 pci_stop_and_remove_bus_device(struct pci_dev *pdev)
1350 * The following functions can be used to attach/detach the LinuxKPI's
1351 * PCI device runtime. The pci_driver and pci_device_id pointer is
1352 * allowed to be NULL. Other pointers must be all valid.
1353 * The pci_dev structure should be zero-initialized before passed
1354 * to the linux_pci_attach_device function.
1356 extern int linux_pci_attach_device(device_t, struct pci_driver *,
1357 const struct pci_device_id *, struct pci_dev *);
1358 extern int linux_pci_detach_device(struct pci_dev *);
1361 pci_dev_present(const struct pci_device_id *cur)
1363 while (cur != NULL && (cur->vendor || cur->device)) {
1364 if (pci_find_device(cur->vendor, cur->device) != NULL) {
1372 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain,
1373 unsigned int bus, unsigned int devfn);
1374 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \
1375 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn)
1378 pci_domain_nr(struct pci_bus *pbus)
1381 return (pbus->domain);
1385 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn,
1386 int pos, uint32_t *val, int len)
1389 *val = pci_read_config(bus->self->dev.bsddev, pos, len);
1394 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val)
1399 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2);
1405 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val)
1410 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1);
1416 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos,
1417 uint32_t val, int size)
1420 pci_write_config(bus->self->dev.bsddev, pos, val, size);
1425 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos,
1428 return (pci_bus_write_config(bus, devfn, pos, val, 1));
1432 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos,
1435 return (pci_bus_write_config(bus, devfn, pos, val, 2));
1438 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from);
1439 #define pci_get_class(class, from) lkpi_pci_get_class(class, from)
1441 /* -------------------------------------------------------------------------- */
1444 pcim_enable_device(struct pci_dev *pdev)
1446 struct pci_devres *dr;
1449 /* Here we cannot run through the pdev->managed check. */
1450 dr = lkpi_pci_devres_get_alloc(pdev);
1454 /* If resources were enabled before do not do it again. */
1458 error = pci_enable_device(pdev);
1460 dr->enable_io = true;
1462 /* This device is not managed. */
1463 pdev->managed = true;
1468 static inline struct pcim_iomap_devres *
1469 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev)
1471 struct pcim_iomap_devres *dr;
1473 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release,
1476 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release,
1477 sizeof(*dr), GFP_KERNEL | __GFP_ZERO);
1479 lkpi_devres_add(&pdev->dev, dr);
1483 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__);
1488 static inline void __iomem **
1489 pcim_iomap_table(struct pci_dev *pdev)
1491 struct pcim_iomap_devres *dr;
1493 dr = lkpi_pcim_iomap_devres_find(pdev);
1498 * If the driver has manually set a flag to be able to request the
1499 * resource to use bus_read/write_<n>, return the shadow table.
1501 if (pdev->want_iomap_res)
1502 return ((void **)dr->res_table);
1504 /* This is the Linux default. */
1505 return (dr->mmio_table);
1509 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name)
1511 struct pcim_iomap_devres *dr;
1513 uint32_t mappings, requests, req_mask;
1516 dr = lkpi_pcim_iomap_devres_find(pdev);
1520 /* Request all the BARs ("regions") we do not iomap. */
1521 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask;
1522 for (bar = requests = 0; requests != req_mask; bar++) {
1523 if ((req_mask & (1 << bar)) == 0)
1525 error = pci_request_region(pdev, bar, name);
1526 if (error != 0 && error != -ENODEV)
1528 requests |= (1 << bar);
1531 /* Now iomap all the requested (by "mask") ones. */
1532 for (bar = mappings = 0; mappings != mask; bar++) {
1533 if ((mask & (1 << bar)) == 0)
1536 /* Request double is not allowed. */
1537 if (dr->mmio_table[bar] != NULL) {
1538 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n",
1539 __func__, bar, dr->mmio_table[bar]);
1543 res = _lkpi_pci_iomap(pdev, bar, 0);
1546 dr->mmio_table[bar] = (void *)rman_get_bushandle(res);
1547 dr->res_table[bar] = res;
1549 mappings |= (1 << bar);
1555 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) {
1556 if ((mappings & (1 << bar)) != 0) {
1557 res = dr->mmio_table[bar];
1560 pci_iounmap(pdev, res);
1561 } else if ((requests & (1 << bar)) != 0) {
1562 pci_release_region(pdev, bar);
1569 /* This is a FreeBSD extension so we can use bus_*(). */
1571 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev)
1573 pdev->want_iomap_res = true;
1576 #endif /* _LINUXKPI_LINUX_PCI_H_ */