2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
7 * Copyright (c) 2020-2021 The FreeBSD Foundation
9 * Portions of this software were developed by Björn Zeeb
10 * under sponsorship from the FreeBSD Foundation.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice unmodified, this list of conditions, and the following
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #ifndef _LINUXKPI_LINUX_PCI_H_
36 #define _LINUXKPI_LINUX_PCI_H_
38 #define CONFIG_PCI_MSI
40 #include <linux/types.h>
42 #include <sys/param.h>
44 #include <sys/module.h>
46 #include <sys/pciio.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pci_private.h>
52 #include <machine/resource.h>
54 #include <linux/list.h>
55 #include <linux/dmapool.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/compiler.h>
58 #include <linux/errno.h>
59 #include <asm/atomic.h>
60 #include <linux/device.h>
61 #include <linux/pci_ids.h>
63 struct pci_device_id {
70 uintptr_t driver_data;
73 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */
74 #define MODULE_DEVICE_TABLE(_bus, _table) \
76 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \
80 static driver_t _ ## _bus ## _ ## _table ## _driver = { \
81 "lkpi_" #_bus #_table, \
82 _ ## _bus ## _ ## _table ## _methods, \
86 static devclass_t _ ## _bus ## _ ## _table ## _devclass; \
88 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\
89 _ ## _bus ## _ ## _table ## _devclass, 0, 0); \
91 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \
92 _bus, lkpi_ ## _table, _table, nitems(_table) - 1)
94 #define PCI_ANY_ID -1U
96 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
97 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
98 #define PCI_FUNC(devfn) ((devfn) & 0x07)
99 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff)
101 #define PCI_VDEVICE(_vendor, _device) \
102 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \
103 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
104 #define PCI_DEVICE(_vendor, _device) \
105 .vendor = (_vendor), .device = (_device), \
106 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
108 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
110 #define PCI_VENDOR_ID PCIR_DEVVENDOR
111 #define PCI_COMMAND PCIR_COMMAND
112 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS
113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */
114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */
115 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S
116 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1
117 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC
118 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */
119 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD
120 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */
121 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */
122 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */
123 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */
124 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */
125 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */
126 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */
127 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */
128 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */
129 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */
130 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */
131 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */
132 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */
133 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE
134 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */
135 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */
136 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */
137 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */
138 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */
139 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */
140 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */
141 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */
142 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */
143 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */
144 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */
145 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */
146 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */
147 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */
148 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */
149 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */
150 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
151 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
152 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
153 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */
154 #define PCI_EXP_LNKCTL2_TLS 0x000f
155 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
156 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
157 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
158 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
159 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
160 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
161 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
163 #define PCI_EXP_LNKCAP_CLKPM 0x00040000
164 #define PCI_EXP_DEVSTA_TRPND 0x0020
166 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY)
167 #define IORESOURCE_IO (1 << SYS_RES_IOPORT)
168 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ)
171 PCI_SPEED_UNKNOWN = -1,
178 enum pcie_link_width {
179 PCIE_LNK_WIDTH_RESRV = 0x00,
187 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
190 #define PCIE_LINK_STATE_L0S 0x00000001
191 #define PCIE_LINK_STATE_L1 0x00000002
192 #define PCIE_LINK_STATE_CLKPM 0x00000004
194 typedef int pci_power_t;
196 #define PCI_D0 PCI_POWERSTATE_D0
197 #define PCI_D1 PCI_POWERSTATE_D1
198 #define PCI_D2 PCI_POWERSTATE_D2
199 #define PCI_D3hot PCI_POWERSTATE_D3
202 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN
204 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD
205 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID
207 #define PCI_EXT_CAP_ID_ERR PCIZ_AER
208 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM
210 #define PCI_L1SS_CTL1 0x8
211 #define PCI_L1SS_CTL1_L1SS_MASK 0xf
213 #define PCI_IRQ_LEGACY 0x01
214 #define PCI_IRQ_MSI 0x02
215 #define PCI_IRQ_MSIX 0x04
220 struct list_head node;
222 const struct pci_device_id *id_table;
223 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
224 void (*remove)(struct pci_dev *dev);
225 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
226 int (*resume) (struct pci_dev *dev); /* Device woken up */
227 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */
230 struct device_driver driver;
231 const struct pci_error_handlers *err_handler;
233 int bsd_probe_return;
234 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs,
235 const nvlist_t *pf_config);
236 void (*bsd_iov_uninit)(device_t dev);
237 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum,
238 const nvlist_t *vf_config);
242 struct pci_dev *self;
247 extern struct list_head pci_drivers;
248 extern struct list_head pci_devices;
249 extern spinlock_t pci_lock;
251 #define __devexit_p(x) x
253 #define module_pci_driver(_driver) \
259 return (linux_pci_register_driver(&_driver)); \
266 linux_pci_unregister_driver(&_driver); \
269 module_init(_pci_init); \
270 module_exit(_pci_exit)
273 * If we find drivers accessing this from multiple KPIs we may have to
274 * refcount objects of this structure.
276 struct pci_mmio_region {
277 TAILQ_ENTRY(pci_mmio_region) next;
278 struct resource *res;
285 struct list_head links;
286 struct pci_driver *pdrv;
288 struct pci_dev *root;
291 uint16_t subsystem_vendor;
292 uint16_t subsystem_device;
297 bool managed; /* devres "pcim_*(). */
304 TAILQ_HEAD(, pci_mmio_region) mmio;
307 /* We need some meta-struct to keep track of these for devres. */
310 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */
312 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */
314 struct pcim_iomap_devres {
315 void *mmio_table[PCIR_MAX_BAR_0 + 1];
316 struct resource *res_table[PCIR_MAX_BAR_0 + 1];
319 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name);
321 /* Internal helper function(s). */
322 struct pci_dev *lkpinew_pci_dev(device_t);
323 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev);
324 void lkpi_pci_devres_release(struct device *, void *);
325 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size);
326 void lkpi_pcim_iomap_table_release(struct device *, void *);
329 pci_resource_type(struct pci_dev *pdev, int bar)
333 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar));
337 if (PCI_BAR_IO(pm->pm_value))
338 return (SYS_RES_IOPORT);
340 return (SYS_RES_MEMORY);
343 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev,
344 struct resource_list *rl, int type, int rid);
346 static inline struct resource_list_entry *
347 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar)
349 struct pci_devinfo *dinfo;
350 struct resource_list *rl;
351 struct resource_list_entry *rle;
353 dinfo = device_get_ivars(pdev->dev.bsddev);
354 rl = &dinfo->resources;
355 rle = resource_list_find(rl, type, rid);
356 /* Reserve resources for this BAR if needed. */
357 if (rle == NULL && reserve_bar)
358 rle = linux_pci_reserve_bar(pdev, rl, type, rid);
362 static inline struct resource_list_entry *
363 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve)
367 type = pci_resource_type(pdev, bar);
371 return (linux_pci_get_rle(pdev, type, bar, reserve));
374 static inline struct device *
375 linux_pci_find_irq_dev(unsigned int irq)
377 struct pci_dev *pdev;
378 struct device *found;
381 spin_lock(&pci_lock);
382 list_for_each_entry(pdev, &pci_devices, links) {
383 if (irq == pdev->dev.irq ||
384 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) {
389 spin_unlock(&pci_lock);
394 * All drivers just seem to want to inspect the type not flags.
397 pci_resource_flags(struct pci_dev *pdev, int bar)
401 type = pci_resource_type(pdev, bar);
407 static inline const char *
408 pci_name(struct pci_dev *d)
411 return device_get_desc(d->dev.bsddev);
415 pci_get_drvdata(struct pci_dev *pdev)
418 return dev_get_drvdata(&pdev->dev);
422 pci_set_drvdata(struct pci_dev *pdev, void *data)
425 dev_set_drvdata(&pdev->dev, data);
428 static inline struct pci_dev *
429 pci_dev_get(struct pci_dev *pdev)
433 get_device(&pdev->dev);
438 pci_dev_put(struct pci_dev *pdev)
442 put_device(&pdev->dev);
446 pci_enable_device(struct pci_dev *pdev)
449 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
450 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
455 pci_disable_device(struct pci_dev *pdev)
458 pci_disable_busmaster(pdev->dev.bsddev);
462 pci_set_master(struct pci_dev *pdev)
465 pci_enable_busmaster(pdev->dev.bsddev);
470 pci_set_power_state(struct pci_dev *pdev, int state)
473 pci_set_powerstate(pdev->dev.bsddev, state);
478 pci_clear_master(struct pci_dev *pdev)
481 pci_disable_busmaster(pdev->dev.bsddev);
486 pci_is_root_bus(struct pci_bus *pbus)
489 return (pbus->self == NULL);
492 static inline struct pci_dev *
493 pci_upstream_bridge(struct pci_dev *pdev)
496 if (pci_is_root_bus(pdev->bus))
500 * If we do not have a (proper) "upstream bridge" set, e.g., we point
501 * to ourselves, try to handle this case on the fly like we do
502 * for pcie_find_root_port().
504 if (pdev == pdev->bus->self) {
507 bridge = device_get_parent(pdev->dev.bsddev);
510 bridge = device_get_parent(bridge);
513 if (device_get_devclass(device_get_parent(bridge)) !=
514 devclass_find("pci"))
518 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev
519 * for it so it can be returned.
521 pdev->bus->self = lkpinew_pci_dev(bridge);
524 return (pdev->bus->self);
527 static inline struct pci_devres *
528 lkpi_pci_devres_find(struct pci_dev *pdev)
534 return (lkpi_pci_devres_get_alloc(pdev));
538 pci_release_region(struct pci_dev *pdev, int bar)
540 struct resource_list_entry *rle;
541 struct pci_devres *dr;
542 struct pci_mmio_region *mmio, *p;
544 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL)
548 * As we implicitly track the requests we also need to clear them on
549 * release. Do clear before resource release.
551 dr = lkpi_pci_devres_find(pdev);
553 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d"
554 " region_table res %p != rel->res %p\n", __func__, pdev,
555 bar, dr->region_table[bar], rle->res));
556 dr->region_table[bar] = NULL;
557 dr->region_mask &= ~(1 << bar);
560 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) {
561 if (rle->res != (void *)rman_get_bushandle(mmio->res))
563 TAILQ_REMOVE(&pdev->mmio, mmio, next);
564 free(mmio, M_DEVBUF);
567 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res);
571 pci_release_regions(struct pci_dev *pdev)
575 for (i = 0; i <= PCIR_MAX_BAR_0; i++)
576 pci_release_region(pdev, i);
580 pci_request_regions(struct pci_dev *pdev, const char *res_name)
585 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
586 error = pci_request_region(pdev, i, res_name);
587 if (error && error != -ENODEV) {
588 pci_release_regions(pdev);
596 lkpi_pci_disable_msix(struct pci_dev *pdev)
599 pci_release_msi(pdev->dev.bsddev);
602 * The MSIX IRQ numbers associated with this PCI device are no
603 * longer valid and might be re-assigned. Make sure
604 * linux_pci_find_irq_dev() does no longer see them by
605 * resetting their references to zero:
607 pdev->dev.irq_start = 0;
608 pdev->dev.irq_end = 0;
609 pdev->msix_enabled = false;
611 /* Only for consistency. No conflict on that one. */
612 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev)
615 lkpi_pci_disable_msi(struct pci_dev *pdev)
618 pci_release_msi(pdev->dev.bsddev);
620 pdev->dev.irq_start = 0;
621 pdev->dev.irq_end = 0;
622 pdev->irq = pdev->dev.irq;
623 pdev->msi_enabled = false;
625 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev)
626 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev)
628 unsigned long pci_resource_start(struct pci_dev *pdev, int bar);
629 unsigned long pci_resource_len(struct pci_dev *pdev, int bar);
631 static inline bus_addr_t
632 pci_bus_address(struct pci_dev *pdev, int bar)
635 return (pci_resource_start(pdev, bar));
638 #define PCI_CAP_ID_EXP PCIY_EXPRESS
639 #define PCI_CAP_ID_PCIX PCIY_PCIX
640 #define PCI_CAP_ID_AGP PCIY_AGP
641 #define PCI_CAP_ID_PM PCIY_PMG
643 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
644 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
645 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST
646 #define PCI_EXP_LNKCTL PCIER_LINK_CTL
647 #define PCI_EXP_LNKSTA PCIER_LINK_STA
650 pci_find_capability(struct pci_dev *pdev, int capid)
654 if (pci_find_cap(pdev->dev.bsddev, capid, ®))
659 static inline int pci_pcie_cap(struct pci_dev *dev)
661 return pci_find_capability(dev, PCI_CAP_ID_EXP);
665 pci_find_ext_capability(struct pci_dev *pdev, int capid)
669 if (pci_find_extcap(pdev->dev.bsddev, capid, ®))
674 #define PCIM_PCAP_PME_SHIFT 11
676 pci_pme_capable(struct pci_dev *pdev, uint32_t flag)
678 struct pci_devinfo *dinfo;
681 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT))
684 dinfo = device_get_ivars(pdev->dev.bsddev);
687 if (cfg->pp.pp_cap == 0)
690 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0)
697 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags)
700 if (!pci_enable_aspm)
707 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val)
710 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);
715 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val)
718 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2);
723 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val)
726 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
731 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val)
734 pci_write_config(pdev->dev.bsddev, where, val, 1);
739 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val)
742 pci_write_config(pdev->dev.bsddev, where, val, 2);
747 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val)
750 pci_write_config(pdev->dev.bsddev, where, val, 4);
754 int linux_pci_register_driver(struct pci_driver *pdrv);
755 int linux_pci_register_drm_driver(struct pci_driver *pdrv);
756 void linux_pci_unregister_driver(struct pci_driver *pdrv);
757 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv);
759 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv)
760 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv)
768 * Enable msix, positive errors indicate actual number of available
769 * vectors. Negative errors are failures.
771 * NB: define added to prevent this definition of pci_enable_msix from
772 * clashing with the native FreeBSD version.
774 #define pci_enable_msix(...) \
775 linux_pci_enable_msix(__VA_ARGS__)
778 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq)
780 struct resource_list_entry *rle;
785 avail = pci_msix_count(pdev->dev.bsddev);
792 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0)
795 * Handle case where "pci_alloc_msix()" may allocate less
796 * interrupts than available and return with no error:
799 pci_release_msi(pdev->dev.bsddev);
802 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false);
803 pdev->dev.irq_start = rle->start;
804 pdev->dev.irq_end = rle->start + avail;
805 for (i = 0; i < nreq; i++)
806 entries[i].vector = pdev->dev.irq_start + i;
807 pdev->msix_enabled = true;
811 #define pci_enable_msix_range(...) \
812 linux_pci_enable_msix_range(__VA_ARGS__)
815 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
816 int minvec, int maxvec)
825 rc = pci_enable_msix(dev, entries, nvec);
837 #define pci_enable_msi(pdev) \
838 linux_pci_enable_msi(pdev)
841 pci_enable_msi(struct pci_dev *pdev)
843 struct resource_list_entry *rle;
847 avail = pci_msi_count(pdev->dev.bsddev);
851 avail = 1; /* this function only enable one MSI IRQ */
852 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0)
855 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false);
856 pdev->dev.irq_start = rle->start;
857 pdev->dev.irq_end = rle->start + avail;
858 pdev->irq = rle->start;
859 pdev->msi_enabled = true;
864 pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv,
869 if (flags & PCI_IRQ_MSIX) {
870 struct msix_entry *entries;
873 entries = kcalloc(maxv, sizeof(*entries), GFP_KERNEL);
874 if (entries == NULL) {
878 for (i = 0; i < maxv; ++i)
879 entries[i].entry = i;
880 error = pci_enable_msix(pdev, entries, maxv);
883 if (error == 0 && pdev->msix_enabled)
884 return (pdev->dev.irq_end - pdev->dev.irq_start);
886 if (flags & PCI_IRQ_MSI) {
887 error = pci_enable_msi(pdev);
888 if (error == 0 && pdev->msi_enabled)
889 return (pdev->dev.irq_end - pdev->dev.irq_start);
891 if (flags & PCI_IRQ_LEGACY) {
900 pci_channel_offline(struct pci_dev *pdev)
903 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID);
906 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
911 static inline void pci_disable_sriov(struct pci_dev *dev)
916 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size)
918 struct resource *res;
920 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size);
923 /* This is a FreeBSD extension so we can use bus_*(). */
924 if (pdev->want_iomap_res)
926 return ((void *)rman_get_bushandle(res));
930 pci_iounmap(struct pci_dev *pdev, void *res)
932 struct pci_mmio_region *mmio, *p;
934 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) {
935 if (res != (void *)rman_get_bushandle(mmio->res))
937 bus_release_resource(pdev->dev.bsddev,
938 mmio->type, mmio->rid, mmio->res);
939 TAILQ_REMOVE(&pdev->mmio, mmio, next);
940 free(mmio, M_DEVBUF);
946 lkpi_pci_save_state(struct pci_dev *pdev)
949 pci_save_state(pdev->dev.bsddev);
953 lkpi_pci_restore_state(struct pci_dev *pdev)
956 pci_restore_state(pdev->dev.bsddev);
959 #define pci_save_state(dev) lkpi_pci_save_state(dev)
960 #define pci_restore_state(dev) lkpi_pci_restore_state(dev)
962 #define DEFINE_PCI_DEVICE_TABLE(_table) \
963 const struct pci_device_id _table[] __devinitdata
965 /* XXX This should not be necessary. */
966 #define pcix_set_mmrbc(d, v) 0
967 #define pcix_get_max_mmrbc(d) 0
968 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v))
970 #define PCI_DMA_BIDIRECTIONAL 0
971 #define PCI_DMA_TODEVICE 1
972 #define PCI_DMA_FROMDEVICE 2
973 #define PCI_DMA_NONE 3
975 #define pci_pool dma_pool
976 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__)
977 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__)
978 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__)
979 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \
980 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc)
981 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \
982 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
983 _size, _vaddr, _dma_handle)
984 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \
985 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
986 _sg, _nents, (enum dma_data_direction)_dir)
987 #define pci_map_single(_hwdev, _ptr, _size, _dir) \
988 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
989 (_ptr), (_size), (enum dma_data_direction)_dir)
990 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \
991 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
992 _addr, _size, (enum dma_data_direction)_dir)
993 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \
994 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
995 _sg, _nents, (enum dma_data_direction)_dir)
996 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \
997 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\
998 _offset, _size, (enum dma_data_direction)_dir)
999 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \
1000 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
1001 _dma_address, _size, (enum dma_data_direction)_dir)
1002 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask))
1003 #define pci_dma_mapping_error(_pdev, _dma_addr) \
1004 dma_mapping_error(&(_pdev)->dev, _dma_addr)
1005 #define pci_set_consistent_dma_mask(_pdev, _mask) \
1006 dma_set_coherent_mask(&(_pdev)->dev, (_mask))
1007 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x);
1008 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x);
1009 #define pci_unmap_addr dma_unmap_addr
1010 #define pci_unmap_addr_set dma_unmap_addr_set
1011 #define pci_unmap_len dma_unmap_len
1012 #define pci_unmap_len_set dma_unmap_len_set
1014 typedef unsigned int __bitwise pci_channel_state_t;
1015 typedef unsigned int __bitwise pci_ers_result_t;
1017 enum pci_channel_state {
1018 pci_channel_io_normal = 1,
1019 pci_channel_io_frozen = 2,
1020 pci_channel_io_perm_failure = 3,
1023 enum pci_ers_result {
1024 PCI_ERS_RESULT_NONE = 1,
1025 PCI_ERS_RESULT_CAN_RECOVER = 2,
1026 PCI_ERS_RESULT_NEED_RESET = 3,
1027 PCI_ERS_RESULT_DISCONNECT = 4,
1028 PCI_ERS_RESULT_RECOVERED = 5,
1031 /* PCI bus error event callbacks */
1032 struct pci_error_handlers {
1033 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
1034 enum pci_channel_state error);
1035 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
1036 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
1037 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
1038 void (*resume)(struct pci_dev *dev);
1041 /* FreeBSD does not support SRIOV - yet */
1042 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
1047 static inline bool pci_is_pcie(struct pci_dev *dev)
1049 return !!pci_pcie_cap(dev);
1052 static inline u16 pcie_flags_reg(struct pci_dev *dev)
1057 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
1061 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);
1066 static inline int pci_pcie_type(struct pci_dev *dev)
1068 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1071 static inline int pcie_cap_version(struct pci_dev *dev)
1073 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS;
1076 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev)
1078 int type = pci_pcie_type(dev);
1080 return pcie_cap_version(dev) > 1 ||
1081 type == PCI_EXP_TYPE_ROOT_PORT ||
1082 type == PCI_EXP_TYPE_ENDPOINT ||
1083 type == PCI_EXP_TYPE_LEG_END;
1086 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
1091 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev)
1093 int type = pci_pcie_type(dev);
1095 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
1096 (type == PCI_EXP_TYPE_DOWNSTREAM &&
1097 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT);
1100 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev)
1102 int type = pci_pcie_type(dev);
1104 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
1105 type == PCI_EXP_TYPE_RC_EC;
1108 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
1110 if (!pci_is_pcie(dev))
1114 case PCI_EXP_FLAGS_TYPE:
1116 case PCI_EXP_DEVCAP:
1117 case PCI_EXP_DEVCTL:
1118 case PCI_EXP_DEVSTA:
1119 return pcie_cap_has_devctl(dev);
1120 case PCI_EXP_LNKCAP:
1121 case PCI_EXP_LNKCTL:
1122 case PCI_EXP_LNKSTA:
1123 return pcie_cap_has_lnkctl(dev);
1124 case PCI_EXP_SLTCAP:
1125 case PCI_EXP_SLTCTL:
1126 case PCI_EXP_SLTSTA:
1127 return pcie_cap_has_sltctl(dev);
1131 return pcie_cap_has_rtctl(dev);
1132 case PCI_EXP_DEVCAP2:
1133 case PCI_EXP_DEVCTL2:
1134 case PCI_EXP_LNKCAP2:
1135 case PCI_EXP_LNKCTL2:
1136 case PCI_EXP_LNKSTA2:
1137 return pcie_cap_version(dev) > 1;
1144 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
1149 if (!pcie_capability_reg_implemented(dev, pos))
1152 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
1156 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
1161 if (!pcie_capability_reg_implemented(dev, pos))
1164 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
1168 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
1173 if (!pcie_capability_reg_implemented(dev, pos))
1176 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
1179 static inline int pcie_get_minimum_link(struct pci_dev *dev,
1180 enum pci_bus_speed *speed, enum pcie_link_width *width)
1182 *speed = PCI_SPEED_UNKNOWN;
1183 *width = PCIE_LNK_WIDTH_UNKNOWN;
1188 pci_num_vf(struct pci_dev *dev)
1193 static inline enum pci_bus_speed
1194 pcie_get_speed_cap(struct pci_dev *dev)
1197 uint32_t lnkcap, lnkcap2;
1200 root = device_get_parent(dev->dev.bsddev);
1202 return (PCI_SPEED_UNKNOWN);
1203 root = device_get_parent(root);
1205 return (PCI_SPEED_UNKNOWN);
1206 root = device_get_parent(root);
1208 return (PCI_SPEED_UNKNOWN);
1210 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA ||
1211 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS)
1212 return (PCI_SPEED_UNKNOWN);
1214 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0)
1215 return (PCI_SPEED_UNKNOWN);
1217 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4);
1219 if (lnkcap2) { /* PCIe r3.0-compliant */
1220 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
1221 return (PCIE_SPEED_2_5GT);
1222 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
1223 return (PCIE_SPEED_5_0GT);
1224 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
1225 return (PCIE_SPEED_8_0GT);
1226 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
1227 return (PCIE_SPEED_16_0GT);
1228 } else { /* pre-r3.0 */
1229 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4);
1230 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
1231 return (PCIE_SPEED_2_5GT);
1232 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
1233 return (PCIE_SPEED_5_0GT);
1234 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
1235 return (PCIE_SPEED_8_0GT);
1236 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
1237 return (PCIE_SPEED_16_0GT);
1239 return (PCI_SPEED_UNKNOWN);
1242 static inline enum pcie_link_width
1243 pcie_get_width_cap(struct pci_dev *dev)
1247 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
1249 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4);
1251 return (PCIE_LNK_WIDTH_UNKNOWN);
1255 pcie_get_mps(struct pci_dev *dev)
1257 return (pci_get_max_payload(dev->dev.bsddev));
1260 static inline uint32_t
1261 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)
1265 case PCIE_SPEED_16_0GT:
1266 return (16000 * 128 / 130);
1267 case PCIE_SPEED_8_0GT:
1268 return (8000 * 128 / 130);
1269 case PCIE_SPEED_5_0GT:
1270 return (5000 * 8 / 10);
1271 case PCIE_SPEED_2_5GT:
1272 return (2500 * 8 / 10);
1278 static inline uint32_t
1279 pcie_bandwidth_available(struct pci_dev *pdev,
1280 struct pci_dev **limiting,
1281 enum pci_bus_speed *speed,
1282 enum pcie_link_width *width)
1284 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev);
1285 enum pcie_link_width nwidth = pcie_get_width_cap(pdev);
1292 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed));
1295 static inline struct pci_dev *
1296 pcie_find_root_port(struct pci_dev *pdev)
1300 if (pdev->root != NULL)
1301 return (pdev->root);
1303 root = pci_find_pcie_root_port(pdev->dev.bsddev);
1307 pdev->root = lkpinew_pci_dev(root);
1308 return (pdev->root);
1311 /* This is needed when people rip out the device "HotPlug". */
1313 pci_lock_rescan_remove(void)
1318 pci_unlock_rescan_remove(void)
1322 static __inline void
1323 pci_stop_and_remove_bus_device(struct pci_dev *pdev)
1328 * The following functions can be used to attach/detach the LinuxKPI's
1329 * PCI device runtime. The pci_driver and pci_device_id pointer is
1330 * allowed to be NULL. Other pointers must be all valid.
1331 * The pci_dev structure should be zero-initialized before passed
1332 * to the linux_pci_attach_device function.
1334 extern int linux_pci_attach_device(device_t, struct pci_driver *,
1335 const struct pci_device_id *, struct pci_dev *);
1336 extern int linux_pci_detach_device(struct pci_dev *);
1339 pci_dev_present(const struct pci_device_id *cur)
1341 while (cur != NULL && (cur->vendor || cur->device)) {
1342 if (pci_find_device(cur->vendor, cur->device) != NULL) {
1350 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain,
1351 unsigned int bus, unsigned int devfn);
1352 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \
1353 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn)
1356 pci_domain_nr(struct pci_bus *pbus)
1359 return (pbus->domain);
1363 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn,
1364 int pos, uint32_t *val, int len)
1367 *val = pci_read_config(bus->self->dev.bsddev, pos, len);
1372 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val)
1377 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2);
1383 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val)
1388 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1);
1394 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos,
1395 uint32_t val, int size)
1398 pci_write_config(bus->self->dev.bsddev, pos, val, size);
1403 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos,
1406 return (pci_bus_write_config(bus, devfn, pos, val, 1));
1410 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos,
1413 return (pci_bus_write_config(bus, devfn, pos, val, 2));
1416 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from);
1417 #define pci_get_class(class, from) lkpi_pci_get_class(class, from)
1419 /* -------------------------------------------------------------------------- */
1422 pcim_enable_device(struct pci_dev *pdev)
1424 struct pci_devres *dr;
1427 /* Here we cannot run through the pdev->managed check. */
1428 dr = lkpi_pci_devres_get_alloc(pdev);
1432 /* If resources were enabled before do not do it again. */
1436 error = pci_enable_device(pdev);
1438 dr->enable_io = true;
1440 /* This device is not managed. */
1441 pdev->managed = true;
1446 static inline struct pcim_iomap_devres *
1447 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev)
1449 struct pcim_iomap_devres *dr;
1451 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release,
1454 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release,
1455 sizeof(*dr), GFP_KERNEL | __GFP_ZERO);
1457 lkpi_devres_add(&pdev->dev, dr);
1461 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__);
1466 static inline void __iomem **
1467 pcim_iomap_table(struct pci_dev *pdev)
1469 struct pcim_iomap_devres *dr;
1471 dr = lkpi_pcim_iomap_devres_find(pdev);
1476 * If the driver has manually set a flag to be able to request the
1477 * resource to use bus_read/write_<n>, return the shadow table.
1479 if (pdev->want_iomap_res)
1480 return ((void **)dr->res_table);
1482 /* This is the Linux default. */
1483 return (dr->mmio_table);
1487 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name)
1489 struct pcim_iomap_devres *dr;
1491 uint32_t mappings, requests, req_mask;
1494 dr = lkpi_pcim_iomap_devres_find(pdev);
1498 /* Request all the BARs ("regions") we do not iomap. */
1499 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask;
1500 for (bar = requests = 0; requests != req_mask; bar++) {
1501 if ((req_mask & (1 << bar)) == 0)
1503 error = pci_request_region(pdev, bar, name);
1504 if (error != 0 && error != -ENODEV)
1506 requests |= (1 << bar);
1509 /* Now iomap all the requested (by "mask") ones. */
1510 for (bar = mappings = 0; mappings != mask; bar++) {
1511 if ((mask & (1 << bar)) == 0)
1514 /* Request double is not allowed. */
1515 if (dr->mmio_table[bar] != NULL) {
1516 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n",
1517 __func__, bar, dr->mmio_table[bar]);
1521 res = _lkpi_pci_iomap(pdev, bar, 0);
1524 dr->mmio_table[bar] = (void *)rman_get_bushandle(res);
1525 dr->res_table[bar] = res;
1527 mappings |= (1 << bar);
1533 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) {
1534 if ((mappings & (1 << bar)) != 0) {
1535 res = dr->mmio_table[bar];
1538 pci_iounmap(pdev, res);
1539 } else if ((requests & (1 << bar)) != 0) {
1540 pci_release_region(pdev, bar);
1547 /* This is a FreeBSD extension so we can use bus_*(). */
1549 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev)
1551 pdev->want_iomap_res = true;
1554 #endif /* _LINUXKPI_LINUX_PCI_H_ */