2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #define CONFIG_PCI_MSI
36 #include <linux/types.h>
38 #include <sys/param.h>
41 #include <sys/pciio.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pci_private.h>
48 #include <machine/resource.h>
50 #include <linux/list.h>
51 #include <linux/dmapool.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/compiler.h>
54 #include <linux/errno.h>
55 #include <asm/atomic.h>
56 #include <linux/device.h>
58 struct pci_device_id {
65 uintptr_t driver_data;
68 #define MODULE_DEVICE_TABLE(bus, table)
70 #define PCI_BASE_CLASS_DISPLAY 0x03
71 #define PCI_CLASS_DISPLAY_VGA 0x0300
72 #define PCI_CLASS_DISPLAY_OTHER 0x0380
73 #define PCI_BASE_CLASS_BRIDGE 0x06
74 #define PCI_CLASS_BRIDGE_ISA 0x0601
76 #define PCI_ANY_ID -1U
77 #define PCI_VENDOR_ID_APPLE 0x106b
78 #define PCI_VENDOR_ID_ASUSTEK 0x1043
79 #define PCI_VENDOR_ID_ATI 0x1002
80 #define PCI_VENDOR_ID_DELL 0x1028
81 #define PCI_VENDOR_ID_HP 0x103c
82 #define PCI_VENDOR_ID_IBM 0x1014
83 #define PCI_VENDOR_ID_INTEL 0x8086
84 #define PCI_VENDOR_ID_MELLANOX 0x15b3
85 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
86 #define PCI_VENDOR_ID_SERVERWORKS 0x1166
87 #define PCI_VENDOR_ID_SONY 0x104d
88 #define PCI_VENDOR_ID_TOPSPIN 0x1867
89 #define PCI_VENDOR_ID_VIA 0x1106
90 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
91 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
92 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44
93 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46
94 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278
95 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282
96 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c
97 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274
98 #define PCI_SUBDEVICE_ID_QEMU 0x1100
100 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
101 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
102 #define PCI_FUNC(devfn) ((devfn) & 0x07)
103 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff)
105 #define PCI_VDEVICE(_vendor, _device) \
106 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \
107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
108 #define PCI_DEVICE(_vendor, _device) \
109 .vendor = (_vendor), .device = (_device), \
110 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
112 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
114 #define PCI_VENDOR_ID PCIR_DEVVENDOR
115 #define PCI_COMMAND PCIR_COMMAND
116 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */
117 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */
118 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */
119 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */
120 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */
121 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */
122 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */
123 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */
124 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */
125 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */
126 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */
127 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */
128 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */
129 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */
130 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */
131 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */
132 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */
133 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */
134 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */
135 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */
136 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */
137 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */
138 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */
139 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */
140 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */
141 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */
142 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */
143 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */
144 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */
145 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */
146 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */
147 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
148 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
149 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
150 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */
152 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD
153 #define PCI_EXP_LNKCAP_CLKPM 0x00040000
154 #define PCI_EXP_DEVSTA_TRPND 0x0020
156 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY)
157 #define IORESOURCE_IO (1 << SYS_RES_IOPORT)
158 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ)
161 PCI_SPEED_UNKNOWN = -1,
168 enum pcie_link_width {
169 PCIE_LNK_WIDTH_RESRV = 0x00,
177 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
180 typedef int pci_power_t;
182 #define PCI_D0 PCI_POWERSTATE_D0
183 #define PCI_D1 PCI_POWERSTATE_D1
184 #define PCI_D2 PCI_POWERSTATE_D2
185 #define PCI_D3hot PCI_POWERSTATE_D3
188 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN
193 struct list_head links;
195 const struct pci_device_id *id_table;
196 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
197 void (*remove)(struct pci_dev *dev);
198 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
199 int (*resume) (struct pci_dev *dev); /* Device woken up */
200 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */
203 struct device_driver driver;
204 const struct pci_error_handlers *err_handler;
206 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs,
207 const nvlist_t *pf_config);
208 void (*bsd_iov_uninit)(device_t dev);
209 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum,
210 const nvlist_t *vf_config);
214 struct pci_dev *self;
219 extern struct list_head pci_drivers;
220 extern struct list_head pci_devices;
221 extern spinlock_t pci_lock;
223 #define __devexit_p(x) x
225 struct pci_mmio_region {
226 TAILQ_ENTRY(pci_mmio_region) next;
227 struct resource *res;
234 struct list_head links;
235 struct pci_driver *pdrv;
239 uint16_t subsystem_vendor;
240 uint16_t subsystem_device;
249 TAILQ_HEAD(, pci_mmio_region) mmio;
252 static inline struct resource_list_entry *
253 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid)
255 struct pci_devinfo *dinfo;
256 struct resource_list *rl;
258 dinfo = device_get_ivars(pdev->dev.bsddev);
259 rl = &dinfo->resources;
260 return resource_list_find(rl, type, rid);
263 static inline struct resource_list_entry *
264 linux_pci_get_bar(struct pci_dev *pdev, int bar)
266 struct resource_list_entry *rle;
269 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL)
270 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar);
274 static inline struct device *
275 linux_pci_find_irq_dev(unsigned int irq)
277 struct pci_dev *pdev;
278 struct device *found;
281 spin_lock(&pci_lock);
282 list_for_each_entry(pdev, &pci_devices, links) {
283 if (irq == pdev->dev.irq ||
284 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) {
289 spin_unlock(&pci_lock);
294 pci_resource_type(struct pci_dev *pdev, int bar)
298 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar));
302 if (PCI_BAR_IO(pm->pm_value))
303 return (SYS_RES_IOPORT);
305 return (SYS_RES_MEMORY);
309 * All drivers just seem to want to inspect the type not flags.
312 pci_resource_flags(struct pci_dev *pdev, int bar)
316 type = pci_resource_type(pdev, bar);
322 static inline const char *
323 pci_name(struct pci_dev *d)
326 return device_get_desc(d->dev.bsddev);
330 pci_get_drvdata(struct pci_dev *pdev)
333 return dev_get_drvdata(&pdev->dev);
337 pci_set_drvdata(struct pci_dev *pdev, void *data)
340 dev_set_drvdata(&pdev->dev, data);
344 pci_dev_put(struct pci_dev *pdev)
348 put_device(&pdev->dev);
352 pci_enable_device(struct pci_dev *pdev)
355 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
356 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
361 pci_disable_device(struct pci_dev *pdev)
364 pci_disable_busmaster(pdev->dev.bsddev);
368 pci_set_master(struct pci_dev *pdev)
371 pci_enable_busmaster(pdev->dev.bsddev);
376 pci_set_power_state(struct pci_dev *pdev, int state)
379 pci_set_powerstate(pdev->dev.bsddev, state);
384 pci_clear_master(struct pci_dev *pdev)
387 pci_disable_busmaster(pdev->dev.bsddev);
392 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
397 type = pci_resource_type(pdev, bar);
401 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid,
408 pci_release_region(struct pci_dev *pdev, int bar)
410 struct resource_list_entry *rle;
412 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL)
414 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res);
418 pci_release_regions(struct pci_dev *pdev)
422 for (i = 0; i <= PCIR_MAX_BAR_0; i++)
423 pci_release_region(pdev, i);
427 pci_request_regions(struct pci_dev *pdev, const char *res_name)
432 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
433 error = pci_request_region(pdev, i, res_name);
434 if (error && error != -ENODEV) {
435 pci_release_regions(pdev);
443 pci_disable_msix(struct pci_dev *pdev)
446 pci_release_msi(pdev->dev.bsddev);
449 * The MSIX IRQ numbers associated with this PCI device are no
450 * longer valid and might be re-assigned. Make sure
451 * linux_pci_find_irq_dev() does no longer see them by
452 * resetting their references to zero:
454 pdev->dev.irq_start = 0;
455 pdev->dev.irq_end = 0;
458 #define pci_disable_msi(pdev) \
459 linux_pci_disable_msi(pdev)
462 linux_pci_disable_msi(struct pci_dev *pdev)
465 pci_release_msi(pdev->dev.bsddev);
467 pdev->dev.irq_start = 0;
468 pdev->dev.irq_end = 0;
469 pdev->irq = pdev->dev.irq;
470 pdev->msi_enabled = false;
473 #define pci_free_irq_vectors(pdev) \
474 linux_pci_disable_msi(pdev)
476 unsigned long pci_resource_start(struct pci_dev *pdev, int bar);
477 unsigned long pci_resource_len(struct pci_dev *pdev, int bar);
479 static inline bus_addr_t
480 pci_bus_address(struct pci_dev *pdev, int bar)
483 return (pci_resource_start(pdev, bar));
486 #define PCI_CAP_ID_EXP PCIY_EXPRESS
487 #define PCI_CAP_ID_PCIX PCIY_PCIX
488 #define PCI_CAP_ID_AGP PCIY_AGP
489 #define PCI_CAP_ID_PM PCIY_PMG
491 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
492 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
493 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST
494 #define PCI_EXP_LNKCTL PCIER_LINK_CTL
495 #define PCI_EXP_LNKSTA PCIER_LINK_STA
498 pci_find_capability(struct pci_dev *pdev, int capid)
502 if (pci_find_cap(pdev->dev.bsddev, capid, ®))
507 static inline int pci_pcie_cap(struct pci_dev *dev)
509 return pci_find_capability(dev, PCI_CAP_ID_EXP);
513 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val)
516 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);
521 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val)
524 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2);
529 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val)
532 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
537 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val)
540 pci_write_config(pdev->dev.bsddev, where, val, 1);
545 pci_write_config_word(struct pci_dev *pdev, int where, u16 val)
548 pci_write_config(pdev->dev.bsddev, where, val, 2);
553 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val)
556 pci_write_config(pdev->dev.bsddev, where, val, 4);
560 int linux_pci_register_driver(struct pci_driver *pdrv);
561 int linux_pci_register_drm_driver(struct pci_driver *pdrv);
562 void linux_pci_unregister_driver(struct pci_driver *pdrv);
563 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv);
565 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv)
566 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv)
574 * Enable msix, positive errors indicate actual number of available
575 * vectors. Negative errors are failures.
577 * NB: define added to prevent this definition of pci_enable_msix from
578 * clashing with the native FreeBSD version.
580 #define pci_enable_msix(...) \
581 linux_pci_enable_msix(__VA_ARGS__)
584 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq)
586 struct resource_list_entry *rle;
591 avail = pci_msix_count(pdev->dev.bsddev);
598 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0)
601 * Handle case where "pci_alloc_msix()" may allocate less
602 * interrupts than available and return with no error:
605 pci_release_msi(pdev->dev.bsddev);
608 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1);
609 pdev->dev.irq_start = rle->start;
610 pdev->dev.irq_end = rle->start + avail;
611 for (i = 0; i < nreq; i++)
612 entries[i].vector = pdev->dev.irq_start + i;
616 #define pci_enable_msix_range(...) \
617 linux_pci_enable_msix_range(__VA_ARGS__)
620 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
621 int minvec, int maxvec)
630 rc = pci_enable_msix(dev, entries, nvec);
642 #define pci_enable_msi(pdev) \
643 linux_pci_enable_msi(pdev)
646 pci_enable_msi(struct pci_dev *pdev)
648 struct resource_list_entry *rle;
652 avail = pci_msi_count(pdev->dev.bsddev);
656 avail = 1; /* this function only enable one MSI IRQ */
657 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0)
660 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1);
661 pdev->dev.irq_start = rle->start;
662 pdev->dev.irq_end = rle->start + avail;
663 pdev->irq = rle->start;
664 pdev->msi_enabled = true;
669 pci_channel_offline(struct pci_dev *pdev)
672 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID);
675 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
679 static inline void pci_disable_sriov(struct pci_dev *dev)
684 pci_iomap(struct pci_dev *dev, int mmio_bar, int mmio_size __unused)
686 struct pci_mmio_region *mmio;
688 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO);
689 mmio->rid = PCIR_BAR(mmio_bar);
690 mmio->type = pci_resource_type(dev, mmio_bar);
691 mmio->res = bus_alloc_resource_any(dev->dev.bsddev, mmio->type,
692 &mmio->rid, RF_ACTIVE);
693 if (mmio->res == NULL) {
694 free(mmio, M_DEVBUF);
697 TAILQ_INSERT_TAIL(&dev->mmio, mmio, next);
699 return ((void *)rman_get_bushandle(mmio->res));
703 pci_iounmap(struct pci_dev *dev, void *res)
705 struct pci_mmio_region *mmio, *p;
707 TAILQ_FOREACH_SAFE(mmio, &dev->mmio, next, p) {
708 if (res != (void *)rman_get_bushandle(mmio->res))
710 bus_release_resource(dev->dev.bsddev,
711 mmio->type, mmio->rid, mmio->res);
712 TAILQ_REMOVE(&dev->mmio, mmio, next);
713 free(mmio, M_DEVBUF);
719 lkpi_pci_save_state(struct pci_dev *pdev)
722 pci_save_state(pdev->dev.bsddev);
726 lkpi_pci_restore_state(struct pci_dev *pdev)
729 pci_restore_state(pdev->dev.bsddev);
732 #define pci_save_state(dev) lkpi_pci_save_state(dev)
733 #define pci_restore_state(dev) lkpi_pci_restore_state(dev)
735 #define DEFINE_PCI_DEVICE_TABLE(_table) \
736 const struct pci_device_id _table[] __devinitdata
738 /* XXX This should not be necessary. */
739 #define pcix_set_mmrbc(d, v) 0
740 #define pcix_get_max_mmrbc(d) 0
741 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v))
743 #define PCI_DMA_BIDIRECTIONAL 0
744 #define PCI_DMA_TODEVICE 1
745 #define PCI_DMA_FROMDEVICE 2
746 #define PCI_DMA_NONE 3
748 #define pci_pool dma_pool
749 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__)
750 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__)
751 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__)
752 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \
753 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc)
754 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \
755 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
756 _size, _vaddr, _dma_handle)
757 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \
758 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
759 _sg, _nents, (enum dma_data_direction)_dir)
760 #define pci_map_single(_hwdev, _ptr, _size, _dir) \
761 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
762 (_ptr), (_size), (enum dma_data_direction)_dir)
763 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \
764 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
765 _addr, _size, (enum dma_data_direction)_dir)
766 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \
767 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
768 _sg, _nents, (enum dma_data_direction)_dir)
769 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \
770 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\
771 _offset, _size, (enum dma_data_direction)_dir)
772 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \
773 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
774 _dma_address, _size, (enum dma_data_direction)_dir)
775 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask))
776 #define pci_dma_mapping_error(_pdev, _dma_addr) \
777 dma_mapping_error(&(_pdev)->dev, _dma_addr)
778 #define pci_set_consistent_dma_mask(_pdev, _mask) \
779 dma_set_coherent_mask(&(_pdev)->dev, (_mask))
780 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x);
781 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x);
782 #define pci_unmap_addr dma_unmap_addr
783 #define pci_unmap_addr_set dma_unmap_addr_set
784 #define pci_unmap_len dma_unmap_len
785 #define pci_unmap_len_set dma_unmap_len_set
787 typedef unsigned int __bitwise pci_channel_state_t;
788 typedef unsigned int __bitwise pci_ers_result_t;
790 enum pci_channel_state {
791 pci_channel_io_normal = 1,
792 pci_channel_io_frozen = 2,
793 pci_channel_io_perm_failure = 3,
796 enum pci_ers_result {
797 PCI_ERS_RESULT_NONE = 1,
798 PCI_ERS_RESULT_CAN_RECOVER = 2,
799 PCI_ERS_RESULT_NEED_RESET = 3,
800 PCI_ERS_RESULT_DISCONNECT = 4,
801 PCI_ERS_RESULT_RECOVERED = 5,
804 /* PCI bus error event callbacks */
805 struct pci_error_handlers {
806 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
807 enum pci_channel_state error);
808 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
809 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
810 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
811 void (*resume)(struct pci_dev *dev);
814 /* FreeBSD does not support SRIOV - yet */
815 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
820 static inline bool pci_is_pcie(struct pci_dev *dev)
822 return !!pci_pcie_cap(dev);
825 static inline u16 pcie_flags_reg(struct pci_dev *dev)
830 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
834 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);
839 static inline int pci_pcie_type(struct pci_dev *dev)
841 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
844 static inline int pcie_cap_version(struct pci_dev *dev)
846 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS;
849 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev)
851 int type = pci_pcie_type(dev);
853 return pcie_cap_version(dev) > 1 ||
854 type == PCI_EXP_TYPE_ROOT_PORT ||
855 type == PCI_EXP_TYPE_ENDPOINT ||
856 type == PCI_EXP_TYPE_LEG_END;
859 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
864 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev)
866 int type = pci_pcie_type(dev);
868 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
869 (type == PCI_EXP_TYPE_DOWNSTREAM &&
870 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT);
873 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev)
875 int type = pci_pcie_type(dev);
877 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
878 type == PCI_EXP_TYPE_RC_EC;
881 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
883 if (!pci_is_pcie(dev))
887 case PCI_EXP_FLAGS_TYPE:
892 return pcie_cap_has_devctl(dev);
896 return pcie_cap_has_lnkctl(dev);
900 return pcie_cap_has_sltctl(dev);
904 return pcie_cap_has_rtctl(dev);
905 case PCI_EXP_DEVCAP2:
906 case PCI_EXP_DEVCTL2:
907 case PCI_EXP_LNKCAP2:
908 case PCI_EXP_LNKCTL2:
909 case PCI_EXP_LNKSTA2:
910 return pcie_cap_version(dev) > 1;
917 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
922 if (!pcie_capability_reg_implemented(dev, pos))
925 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
929 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
934 if (!pcie_capability_reg_implemented(dev, pos))
937 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
941 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
946 if (!pcie_capability_reg_implemented(dev, pos))
949 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
952 static inline int pcie_get_minimum_link(struct pci_dev *dev,
953 enum pci_bus_speed *speed, enum pcie_link_width *width)
955 *speed = PCI_SPEED_UNKNOWN;
956 *width = PCIE_LNK_WIDTH_UNKNOWN;
961 pci_num_vf(struct pci_dev *dev)
966 static inline enum pci_bus_speed
967 pcie_get_speed_cap(struct pci_dev *dev)
970 uint32_t lnkcap, lnkcap2;
973 root = device_get_parent(dev->dev.bsddev);
975 return (PCI_SPEED_UNKNOWN);
976 root = device_get_parent(root);
978 return (PCI_SPEED_UNKNOWN);
979 root = device_get_parent(root);
981 return (PCI_SPEED_UNKNOWN);
983 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA ||
984 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS)
985 return (PCI_SPEED_UNKNOWN);
987 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0)
988 return (PCI_SPEED_UNKNOWN);
990 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4);
992 if (lnkcap2) { /* PCIe r3.0-compliant */
993 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
994 return (PCIE_SPEED_2_5GT);
995 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
996 return (PCIE_SPEED_5_0GT);
997 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
998 return (PCIE_SPEED_8_0GT);
999 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
1000 return (PCIE_SPEED_16_0GT);
1001 } else { /* pre-r3.0 */
1002 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4);
1003 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
1004 return (PCIE_SPEED_2_5GT);
1005 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
1006 return (PCIE_SPEED_5_0GT);
1007 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
1008 return (PCIE_SPEED_8_0GT);
1009 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
1010 return (PCIE_SPEED_16_0GT);
1012 return (PCI_SPEED_UNKNOWN);
1015 static inline enum pcie_link_width
1016 pcie_get_width_cap(struct pci_dev *dev)
1020 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
1022 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4);
1024 return (PCIE_LNK_WIDTH_UNKNOWN);
1028 pcie_get_mps(struct pci_dev *dev)
1030 return (pci_get_max_payload(dev->dev.bsddev));
1033 static inline uint32_t
1034 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)
1038 case PCIE_SPEED_16_0GT:
1039 return (16000 * 128 / 130);
1040 case PCIE_SPEED_8_0GT:
1041 return (8000 * 128 / 130);
1042 case PCIE_SPEED_5_0GT:
1043 return (5000 * 8 / 10);
1044 case PCIE_SPEED_2_5GT:
1045 return (2500 * 8 / 10);
1051 static inline uint32_t
1052 pcie_bandwidth_available(struct pci_dev *pdev,
1053 struct pci_dev **limiting,
1054 enum pci_bus_speed *speed,
1055 enum pcie_link_width *width)
1057 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev);
1058 enum pcie_link_width nwidth = pcie_get_width_cap(pdev);
1065 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed));
1069 * The following functions can be used to attach/detach the LinuxKPI's
1070 * PCI device runtime. The pci_driver and pci_device_id pointer is
1071 * allowed to be NULL. Other pointers must be all valid.
1072 * The pci_dev structure should be zero-initialized before passed
1073 * to the linux_pci_attach_device function.
1075 extern int linux_pci_attach_device(device_t, struct pci_driver *,
1076 const struct pci_device_id *, struct pci_dev *);
1077 extern int linux_pci_detach_device(struct pci_dev *);
1080 pci_dev_present(const struct pci_device_id *cur)
1082 while (cur != NULL && (cur->vendor || cur->device)) {
1083 if (pci_find_device(cur->vendor, cur->device) != NULL) {
1092 pci_is_root_bus(struct pci_bus *pbus)
1095 return (pbus->self == NULL);
1098 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain,
1099 unsigned int bus, unsigned int devfn);
1100 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \
1101 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn)
1104 pci_domain_nr(struct pci_bus *pbus)
1107 return (pbus->domain);
1111 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn,
1112 int pos, uint32_t *val, int len)
1115 *val = pci_read_config(bus->self->dev.bsddev, pos, len);
1120 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val)
1125 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2);
1131 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val)
1136 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1);
1142 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos,
1143 uint32_t val, int size)
1146 pci_write_config(bus->self->dev.bsddev, pos, val, size);
1151 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos,
1154 return (pci_bus_write_config(bus, devfn, pos, val, 1));
1158 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos,
1161 return (pci_bus_write_config(bus, devfn, pos, val, 2));
1164 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from);
1165 #define pci_get_class(class, from) lkpi_pci_get_class(class, from)
1167 #endif /* _LINUX_PCI_H_ */