2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #define CONFIG_PCI_MSI
36 #include <linux/types.h>
38 #include <sys/param.h>
40 #include <sys/pciio.h>
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pci_private.h>
46 #include <machine/resource.h>
48 #include <linux/list.h>
49 #include <linux/dmapool.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/compiler.h>
52 #include <linux/errno.h>
53 #include <asm/atomic.h>
54 #include <linux/device.h>
56 struct pci_device_id {
63 uintptr_t driver_data;
66 #define MODULE_DEVICE_TABLE(bus, table)
68 #define PCI_BASE_CLASS_DISPLAY 0x03
69 #define PCI_CLASS_DISPLAY_VGA 0x0300
70 #define PCI_CLASS_DISPLAY_OTHER 0x0380
71 #define PCI_BASE_CLASS_BRIDGE 0x06
72 #define PCI_CLASS_BRIDGE_ISA 0x0601
74 #define PCI_ANY_ID (-1)
75 #define PCI_VENDOR_ID_APPLE 0x106b
76 #define PCI_VENDOR_ID_ASUSTEK 0x1043
77 #define PCI_VENDOR_ID_ATI 0x1002
78 #define PCI_VENDOR_ID_DELL 0x1028
79 #define PCI_VENDOR_ID_HP 0x103c
80 #define PCI_VENDOR_ID_IBM 0x1014
81 #define PCI_VENDOR_ID_INTEL 0x8086
82 #define PCI_VENDOR_ID_MELLANOX 0x15b3
83 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
84 #define PCI_VENDOR_ID_SERVERWORKS 0x1166
85 #define PCI_VENDOR_ID_SONY 0x104d
86 #define PCI_VENDOR_ID_TOPSPIN 0x1867
87 #define PCI_VENDOR_ID_VIA 0x1106
88 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
89 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
90 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44
91 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46
92 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278
93 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282
94 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c
95 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274
96 #define PCI_SUBDEVICE_ID_QEMU 0x1100
98 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
99 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
100 #define PCI_FUNC(devfn) ((devfn) & 0x07)
102 #define PCI_VDEVICE(_vendor, _device) \
103 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \
104 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
105 #define PCI_DEVICE(_vendor, _device) \
106 .vendor = (_vendor), .device = (_device), \
107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
109 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
111 #define PCI_VENDOR_ID PCIR_DEVVENDOR
112 #define PCI_COMMAND PCIR_COMMAND
113 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */
114 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */
115 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */
116 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */
117 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */
118 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */
119 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */
120 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */
121 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */
122 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */
123 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */
124 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */
125 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */
126 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */
127 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */
128 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */
129 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */
130 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */
131 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */
132 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */
133 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */
134 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */
135 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */
136 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */
137 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */
138 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */
139 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */
140 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */
141 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */
142 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
143 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
144 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
146 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD
147 #define PCI_EXP_LNKCAP_CLKPM 0x00040000
148 #define PCI_EXP_DEVSTA_TRPND 0x0020
150 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY)
151 #define IORESOURCE_IO (1 << SYS_RES_IOPORT)
152 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ)
155 PCI_SPEED_UNKNOWN = -1,
161 enum pcie_link_width {
162 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
165 typedef int pci_power_t;
167 #define PCI_D0 PCI_POWERSTATE_D0
168 #define PCI_D1 PCI_POWERSTATE_D1
169 #define PCI_D2 PCI_POWERSTATE_D2
170 #define PCI_D3hot PCI_POWERSTATE_D3
173 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN
178 struct list_head links;
180 const struct pci_device_id *id_table;
181 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
182 void (*remove)(struct pci_dev *dev);
183 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
184 int (*resume) (struct pci_dev *dev); /* Device woken up */
185 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */
188 struct device_driver driver;
189 const struct pci_error_handlers *err_handler;
192 extern struct list_head pci_drivers;
193 extern struct list_head pci_devices;
194 extern spinlock_t pci_lock;
196 #define __devexit_p(x) x
200 struct list_head links;
201 struct pci_driver *pdrv;
211 static inline struct resource_list_entry *
212 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid)
214 struct pci_devinfo *dinfo;
215 struct resource_list *rl;
217 dinfo = device_get_ivars(pdev->dev.bsddev);
218 rl = &dinfo->resources;
219 return resource_list_find(rl, type, rid);
222 static inline struct resource_list_entry *
223 linux_pci_get_bar(struct pci_dev *pdev, int bar)
225 struct resource_list_entry *rle;
228 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL)
229 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar);
233 static inline struct device *
234 linux_pci_find_irq_dev(unsigned int irq)
236 struct pci_dev *pdev;
237 struct device *found;
240 spin_lock(&pci_lock);
241 list_for_each_entry(pdev, &pci_devices, links) {
242 if (irq == pdev->dev.irq ||
243 (irq >= pdev->dev.msix && irq < pdev->dev.msix_max)) {
248 spin_unlock(&pci_lock);
252 static inline unsigned long
253 pci_resource_start(struct pci_dev *pdev, int bar)
255 struct resource_list_entry *rle;
257 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL)
262 static inline unsigned long
263 pci_resource_len(struct pci_dev *pdev, int bar)
265 struct resource_list_entry *rle;
267 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL)
273 pci_resource_type(struct pci_dev *pdev, int bar)
277 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar));
281 if (PCI_BAR_IO(pm->pm_value))
282 return (SYS_RES_IOPORT);
284 return (SYS_RES_MEMORY);
288 * All drivers just seem to want to inspect the type not flags.
291 pci_resource_flags(struct pci_dev *pdev, int bar)
295 type = pci_resource_type(pdev, bar);
301 static inline const char *
302 pci_name(struct pci_dev *d)
305 return device_get_desc(d->dev.bsddev);
309 pci_get_drvdata(struct pci_dev *pdev)
312 return dev_get_drvdata(&pdev->dev);
316 pci_set_drvdata(struct pci_dev *pdev, void *data)
319 dev_set_drvdata(&pdev->dev, data);
323 pci_enable_device(struct pci_dev *pdev)
326 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
327 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
332 pci_disable_device(struct pci_dev *pdev)
335 pci_disable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
336 pci_disable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
340 pci_set_master(struct pci_dev *pdev)
343 pci_enable_busmaster(pdev->dev.bsddev);
348 pci_set_power_state(struct pci_dev *pdev, int state)
351 pci_set_powerstate(pdev->dev.bsddev, state);
356 pci_clear_master(struct pci_dev *pdev)
359 pci_disable_busmaster(pdev->dev.bsddev);
364 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
369 type = pci_resource_type(pdev, bar);
373 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid,
380 pci_release_region(struct pci_dev *pdev, int bar)
382 struct resource_list_entry *rle;
384 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL)
386 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res);
390 pci_release_regions(struct pci_dev *pdev)
394 for (i = 0; i <= PCIR_MAX_BAR_0; i++)
395 pci_release_region(pdev, i);
399 pci_request_regions(struct pci_dev *pdev, const char *res_name)
404 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
405 error = pci_request_region(pdev, i, res_name);
406 if (error && error != -ENODEV) {
407 pci_release_regions(pdev);
415 pci_disable_msix(struct pci_dev *pdev)
418 pci_release_msi(pdev->dev.bsddev);
421 static inline bus_addr_t
422 pci_bus_address(struct pci_dev *pdev, int bar)
425 return (pci_resource_start(pdev, bar));
428 #define PCI_CAP_ID_EXP PCIY_EXPRESS
429 #define PCI_CAP_ID_PCIX PCIY_PCIX
430 #define PCI_CAP_ID_AGP PCIY_AGP
431 #define PCI_CAP_ID_PM PCIY_PMG
433 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
434 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
435 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST
436 #define PCI_EXP_LNKCTL PCIER_LINK_CTL
437 #define PCI_EXP_LNKSTA PCIER_LINK_STA
440 pci_find_capability(struct pci_dev *pdev, int capid)
444 if (pci_find_cap(pdev->dev.bsddev, capid, ®))
449 static inline int pci_pcie_cap(struct pci_dev *dev)
451 return pci_find_capability(dev, PCI_CAP_ID_EXP);
456 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val)
459 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);
464 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val)
467 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2);
472 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val)
475 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
480 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val)
483 pci_write_config(pdev->dev.bsddev, where, val, 1);
488 pci_write_config_word(struct pci_dev *pdev, int where, u16 val)
491 pci_write_config(pdev->dev.bsddev, where, val, 2);
496 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val)
499 pci_write_config(pdev->dev.bsddev, where, val, 4);
503 extern int pci_register_driver(struct pci_driver *pdrv);
504 extern void pci_unregister_driver(struct pci_driver *pdrv);
512 * Enable msix, positive errors indicate actual number of available
513 * vectors. Negative errors are failures.
515 * NB: define added to prevent this definition of pci_enable_msix from
516 * clashing with the native FreeBSD version.
518 #define pci_enable_msix linux_pci_enable_msix
520 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq)
522 struct resource_list_entry *rle;
527 avail = pci_msix_count(pdev->dev.bsddev);
534 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0)
537 * Handle case where "pci_alloc_msix()" may allocate less
538 * interrupts than available and return with no error:
541 pci_release_msi(pdev->dev.bsddev);
544 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1);
545 pdev->dev.msix = rle->start;
546 pdev->dev.msix_max = rle->start + avail;
547 for (i = 0; i < nreq; i++)
548 entries[i].vector = pdev->dev.msix + i;
552 #define pci_enable_msix_range linux_pci_enable_msix_range
554 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
555 int minvec, int maxvec)
564 rc = pci_enable_msix(dev, entries, nvec);
576 static inline int pci_channel_offline(struct pci_dev *pdev)
581 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
585 static inline void pci_disable_sriov(struct pci_dev *dev)
589 #define DEFINE_PCI_DEVICE_TABLE(_table) \
590 const struct pci_device_id _table[] __devinitdata
593 /* XXX This should not be necessary. */
594 #define pcix_set_mmrbc(d, v) 0
595 #define pcix_get_max_mmrbc(d) 0
596 #define pcie_set_readrq(d, v) 0
598 #define PCI_DMA_BIDIRECTIONAL 0
599 #define PCI_DMA_TODEVICE 1
600 #define PCI_DMA_FROMDEVICE 2
601 #define PCI_DMA_NONE 3
603 #define pci_pool dma_pool
604 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__)
605 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__)
606 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__)
607 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \
608 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc)
609 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \
610 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
611 _size, _vaddr, _dma_handle)
612 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \
613 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
614 _sg, _nents, (enum dma_data_direction)_dir)
615 #define pci_map_single(_hwdev, _ptr, _size, _dir) \
616 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
617 (_ptr), (_size), (enum dma_data_direction)_dir)
618 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \
619 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
620 _addr, _size, (enum dma_data_direction)_dir)
621 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \
622 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
623 _sg, _nents, (enum dma_data_direction)_dir)
624 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \
625 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\
626 _offset, _size, (enum dma_data_direction)_dir)
627 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \
628 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
629 _dma_address, _size, (enum dma_data_direction)_dir)
630 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask))
631 #define pci_dma_mapping_error(_pdev, _dma_addr) \
632 dma_mapping_error(&(_pdev)->dev, _dma_addr)
633 #define pci_set_consistent_dma_mask(_pdev, _mask) \
634 dma_set_coherent_mask(&(_pdev)->dev, (_mask))
635 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x);
636 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x);
637 #define pci_unmap_addr dma_unmap_addr
638 #define pci_unmap_addr_set dma_unmap_addr_set
639 #define pci_unmap_len dma_unmap_len
640 #define pci_unmap_len_set dma_unmap_len_set
642 typedef unsigned int __bitwise pci_channel_state_t;
643 typedef unsigned int __bitwise pci_ers_result_t;
645 enum pci_channel_state {
646 pci_channel_io_normal = 1,
647 pci_channel_io_frozen = 2,
648 pci_channel_io_perm_failure = 3,
651 enum pci_ers_result {
652 PCI_ERS_RESULT_NONE = 1,
653 PCI_ERS_RESULT_CAN_RECOVER = 2,
654 PCI_ERS_RESULT_NEED_RESET = 3,
655 PCI_ERS_RESULT_DISCONNECT = 4,
656 PCI_ERS_RESULT_RECOVERED = 5,
660 /* PCI bus error event callbacks */
661 struct pci_error_handlers {
662 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
663 enum pci_channel_state error);
664 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
665 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
666 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
667 void (*resume)(struct pci_dev *dev);
670 /* FreeBSD does not support SRIOV - yet */
671 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
676 static inline bool pci_is_pcie(struct pci_dev *dev)
678 return !!pci_pcie_cap(dev);
681 static inline u16 pcie_flags_reg(struct pci_dev *dev)
686 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
690 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);
696 static inline int pci_pcie_type(struct pci_dev *dev)
698 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
701 static inline int pcie_cap_version(struct pci_dev *dev)
703 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS;
706 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev)
708 int type = pci_pcie_type(dev);
710 return pcie_cap_version(dev) > 1 ||
711 type == PCI_EXP_TYPE_ROOT_PORT ||
712 type == PCI_EXP_TYPE_ENDPOINT ||
713 type == PCI_EXP_TYPE_LEG_END;
716 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
721 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev)
723 int type = pci_pcie_type(dev);
725 return pcie_cap_version(dev) > 1 ||
726 type == PCI_EXP_TYPE_ROOT_PORT ||
727 (type == PCI_EXP_TYPE_DOWNSTREAM &&
728 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT);
731 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev)
733 int type = pci_pcie_type(dev);
735 return pcie_cap_version(dev) > 1 ||
736 type == PCI_EXP_TYPE_ROOT_PORT ||
737 type == PCI_EXP_TYPE_RC_EC;
740 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
742 if (!pci_is_pcie(dev))
746 case PCI_EXP_FLAGS_TYPE:
751 return pcie_cap_has_devctl(dev);
755 return pcie_cap_has_lnkctl(dev);
759 return pcie_cap_has_sltctl(dev);
763 return pcie_cap_has_rtctl(dev);
764 case PCI_EXP_DEVCAP2:
765 case PCI_EXP_DEVCTL2:
766 case PCI_EXP_LNKCAP2:
767 case PCI_EXP_LNKCTL2:
768 case PCI_EXP_LNKSTA2:
769 return pcie_cap_version(dev) > 1;
776 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
781 if (!pcie_capability_reg_implemented(dev, pos))
784 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
788 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
793 if (!pcie_capability_reg_implemented(dev, pos))
796 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
800 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
805 if (!pcie_capability_reg_implemented(dev, pos))
808 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
811 static inline int pcie_get_minimum_link(struct pci_dev *dev,
812 enum pci_bus_speed *speed, enum pcie_link_width *width)
814 *speed = PCI_SPEED_UNKNOWN;
815 *width = PCIE_LNK_WIDTH_UNKNOWN;
820 pci_num_vf(struct pci_dev *dev)
825 #endif /* _LINUX_PCI_H_ */